Wed Jun 12 00:35:34 2013 UTC ()
If the L1 instruction cache policy is PIPT, don't set the prefer_mask.


(matt)
diff -r1.120 -r1.121 src/sys/arch/arm/arm/cpufunc.c
cvs diff -r1.120 -r1.121 src/sys/arch/arm/arm/cpufunc.c (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc.c 2013/05/19 15:37:06 1.120
+++ src/sys/arch/arm/arm/cpufunc.c 2013/06/12 00:35:34 1.121
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc.c,v 1.120 2013/05/19 15:37:06 rkujawa Exp $ */ 1/* $NetBSD: cpufunc.c,v 1.121 2013/06/12 00:35:34 matt Exp $ */
2 2
3/* 3/*
4 * arm7tdmi support code Copyright (c) 2001 John Fremlin 4 * arm7tdmi support code Copyright (c) 2001 John Fremlin
5 * arm8 support code Copyright (c) 1997 ARM Limited 5 * arm8 support code Copyright (c) 1997 ARM Limited
6 * arm8 support code Copyright (c) 1997 Causality Limited 6 * arm8 support code Copyright (c) 1997 Causality Limited
7 * arm9 support code Copyright (C) 2001 ARM Ltd 7 * arm9 support code Copyright (C) 2001 ARM Ltd
8 * arm11 support code Copyright (c) 2007 Microsoft 8 * arm11 support code Copyright (c) 2007 Microsoft
9 * cortexa8 support code Copyright (c) 2008 3am Software Foundry 9 * cortexa8 support code Copyright (c) 2008 3am Software Foundry
10 * cortexa8 improvements Copyright (c) Goeran Weinholt 10 * cortexa8 improvements Copyright (c) Goeran Weinholt
11 * Copyright (c) 1997 Mark Brinicombe. 11 * Copyright (c) 1997 Mark Brinicombe.
12 * Copyright (c) 1997 Causality Limited 12 * Copyright (c) 1997 Causality Limited
13 * All rights reserved. 13 * All rights reserved.
14 * 14 *
@@ -39,27 +39,27 @@ @@ -39,27 +39,27 @@
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE. 40 * SUCH DAMAGE.
41 * 41 *
42 * RiscBSD kernel project 42 * RiscBSD kernel project
43 * 43 *
44 * cpufuncs.c 44 * cpufuncs.c
45 * 45 *
46 * C functions for supporting CPU / MMU / TLB specific operations. 46 * C functions for supporting CPU / MMU / TLB specific operations.
47 * 47 *
48 * Created : 30/01/97 48 * Created : 30/01/97
49 */ 49 */
50 50
51#include <sys/cdefs.h> 51#include <sys/cdefs.h>
52__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.120 2013/05/19 15:37:06 rkujawa Exp $"); 52__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.121 2013/06/12 00:35:34 matt Exp $");
53 53
54#include "opt_compat_netbsd.h" 54#include "opt_compat_netbsd.h"
55#include "opt_cpuoptions.h" 55#include "opt_cpuoptions.h"
56#include "opt_perfctrs.h" 56#include "opt_perfctrs.h"
57 57
58#include <sys/types.h> 58#include <sys/types.h>
59#include <sys/param.h> 59#include <sys/param.h>
60#include <sys/pmc.h> 60#include <sys/pmc.h>
61#include <sys/systm.h> 61#include <sys/systm.h>
62#include <machine/cpu.h> 62#include <machine/cpu.h>
63#include <machine/bootconfig.h> 63#include <machine/bootconfig.h>
64#include <arch/arm/arm/disassem.h> 64#include <arch/arm/arm/disassem.h>
65 65
@@ -1541,27 +1541,29 @@ get_cachetype_cp15(void) @@ -1541,27 +1541,29 @@ get_cachetype_cp15(void)
1541 * ...and thus spake the ARM ARM: 1541 * ...and thus spake the ARM ARM:
1542 * 1542 *
1543 * If an <opcode2> value corresponding to an unimplemented or 1543 * If an <opcode2> value corresponding to an unimplemented or
1544 * reserved ID register is encountered, the System Control 1544 * reserved ID register is encountered, the System Control
1545 * processor returns the value of the main ID register. 1545 * processor returns the value of the main ID register.
1546 */ 1546 */
1547 if (ctype == cpu_id()) 1547 if (ctype == cpu_id())
1548 goto out; 1548 goto out;
1549 1549
1550#if (ARM_MMU_V6 + ARM_MMU_V7) > 0 1550#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
1551 if (CPU_CT_FORMAT(ctype) == 4) { 1551 if (CPU_CT_FORMAT(ctype) == 4) {
1552 u_int clidr = armreg_clidr_read(); 1552 u_int clidr = armreg_clidr_read();
1553 1553
1554 arm_cache_prefer_mask = PAGE_SIZE; 1554 if (CPU_CT4_L1IPOLICY(ctype) != CPU_CT4_L1_PIPT) {
 1555 arm_cache_prefer_mask = PAGE_SIZE;
 1556 }
1555 arm_pcache.cache_type = CPU_CT_CTYPE_WB14; 1557 arm_pcache.cache_type = CPU_CT_CTYPE_WB14;
1556 1558
1557 get_cacheinfo_clidr(&arm_pcache, 0, clidr & 7); 1559 get_cacheinfo_clidr(&arm_pcache, 0, clidr & 7);
1558 arm_dcache_align = arm_pcache.dcache_line_size; 1560 arm_dcache_align = arm_pcache.dcache_line_size;
1559 clidr >>= 3; 1561 clidr >>= 3;
1560 if (clidr & 7) { 1562 if (clidr & 7) {
1561 get_cacheinfo_clidr(&arm_scache, 1, clidr & 7); 1563 get_cacheinfo_clidr(&arm_scache, 1, clidr & 7);
1562 if (arm_scache.dcache_line_size < arm_dcache_align) 1564 if (arm_scache.dcache_line_size < arm_dcache_align)
1563 arm_dcache_align = arm_scache.dcache_line_size; 1565 arm_dcache_align = arm_scache.dcache_line_size;
1564 } 1566 }
1565 goto out; 1567 goto out;
1566 } 1568 }
1567#endif /* ARM_MMU_V6 + ARM_MMU_V7 > 0 */ 1569#endif /* ARM_MMU_V6 + ARM_MMU_V7 > 0 */