Wed Jun 12 02:51:43 2013 UTC ()
regen.


(msaitoh)
diff -r1.118 -r1.119 src/sys/dev/mii/miidevs.h
diff -r1.106 -r1.107 src/sys/dev/mii/miidevs_data.h
cvs diff -r1.118 -r1.119 src/sys/dev/mii/miidevs.h (switch to unified diff)

--- src/sys/dev/mii/miidevs.h 2013/06/02 09:13:27 1.118
+++ src/sys/dev/mii/miidevs.h 2013/06/12 02:51:43 1.119
@@ -1,459 +1,465 @@ @@ -1,459 +1,465 @@
1/* $NetBSD: miidevs.h,v 1.118 2013/06/02 09:13:27 msaitoh Exp $ */ 1/* $NetBSD: miidevs.h,v 1.119 2013/06/12 02:51:43 msaitoh Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.115 2013/06/02 09:13:07 msaitoh Exp 7 * NetBSD: miidevs,v 1.116 2013/06/12 02:51:16 msaitoh Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
21 * 1. Redistributions of source code must retain the above copyright 21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer. 22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright 23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the 24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution. 25 * documentation and/or other materials provided with the distribution.
26 * 26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE. 37 * POSSIBILITY OF SUCH DAMAGE.
38 */ 38 */
39 39
40/* 40/*
41 * List of known MII OUIs. 41 * List of known MII OUIs.
42 * For a complete list see http://standards.ieee.org/regauth/oui/ 42 * For a complete list see http://standards.ieee.org/regauth/oui/
43 * 43 *
44 * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped 44 * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
45 * to the 22 bits available in the id registers. 45 * to the 22 bits available in the id registers.
46 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right 46 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
47 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2. 47 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
48 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998, 48 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
49 * about this.) 49 * about this.)
50 * The MII_OUI() macro in "miivar.h" reflects this. 50 * The MII_OUI() macro in "miivar.h" reflects this.
51 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here 51 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
52 * which is mangled accordingly to compensate. 52 * which is mangled accordingly to compensate.
53 */ 53 */
54 54
55/* 55/*
56 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h 56 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h
57 */ 57 */
58 58
59#define MII_OUI_AGERE 0x00053d /* Agere */ 59#define MII_OUI_AGERE 0x00053d /* Agere */
60#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 60#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
61#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 61#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
62#define MII_OUI_ATHEROS 0x001374 /* Atheros */ 62#define MII_OUI_ATHEROS 0x001374 /* Atheros */
63#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */ 63#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */
64#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 64#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
65#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */ 65#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
66#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */ 66#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */
67#define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */ 67#define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */
68#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 68#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
69#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 69#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */
70#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */ 70#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
71#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 71#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
72#define MII_OUI_INTEL 0x00aa00 /* Intel */ 72#define MII_OUI_INTEL 0x00aa00 /* Intel */
73#define MII_OUI_JMICRON 0x00d831 /* JMicron */ 73#define MII_OUI_JMICRON 0x00d831 /* JMicron */
74#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 74#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
75#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 75#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
76#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 76#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */
77#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 77#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
78#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ 78#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */
79#define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */ 79#define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */
80#define MII_OUI_REALTEK 0x00e04c /* RealTek */ 80#define MII_OUI_REALTEK 0x00e04c /* RealTek */
81#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 81#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
82#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 82#define MII_OUI_SEEQ 0x00a07d /* Seeq */
83#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 83#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
84#define MII_OUI_SMSC 0x00800f /* SMSC */ 84#define MII_OUI_SMSC 0x00800f /* SMSC */
85#define MII_OUI_TI 0x080028 /* Texas Instruments */ 85#define MII_OUI_TI 0x080028 /* Texas Instruments */
86#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 86#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
87#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 87#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
88 88
89/* Some Intel 82553's use an alternative OUI. */ 89/* Some Intel 82553's use an alternative OUI. */
90#define MII_OUI_xxINTEL 0x001f00 /* Intel */ 90#define MII_OUI_xxINTEL 0x001f00 /* Intel */
91 91
92/* Some VIA 6122's use an alternative OUI. */ 92/* Some VIA 6122's use an alternative OUI. */
93#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */ 93#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
94 94
95/* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */ 95/* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */
96#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */ 96#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */
97#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 97#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
98#define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */ 98#define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */
99#define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */ 99#define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */
100#define MII_OUI_yyINTEL 0x005500 /* Intel */ 100#define MII_OUI_yyINTEL 0x005500 /* Intel */
101#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ 101#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
102#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */ 102#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */
103#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */ 103#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */
104#define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */ 104#define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */
105#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */ 105#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */
106 106
107/* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */ 107/* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */
108#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */ 108#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */
109#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */ 109#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */
110 110
111/* Don't know what's going on here. */ 111/* Don't know what's going on here. */
112#define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */ 112#define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */
113#define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */ 113#define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */
114 114
115#define MII_OUI_xxREALTEK 0x000732 /* Realtek */ 115#define MII_OUI_xxREALTEK 0x000732 /* Realtek */
116#define MII_OUI_yyREALTEK 0x000004 /* Realtek */ 116#define MII_OUI_yyREALTEK 0x000004 /* Realtek */
117/* 117/*
118 * List of known models. Grouped by oui. 118 * List of known models. Grouped by oui.
119 */ 119 */
120 120
121/* 121/*
122 * Agere PHYs 122 * Agere PHYs
123 */ 123 */
124#define MII_MODEL_AGERE_ET1011 0x0004 124#define MII_MODEL_AGERE_ET1011 0x0004
125#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY" 125#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY"
126 126
127/* Atheros PHYs */ 127/* Atheros PHYs */
128#define MII_MODEL_ATHEROS_F1 0x0001 128#define MII_MODEL_ATHEROS_F1 0x0001
129#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY" 129#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY"
130#define MII_MODEL_ATHEROS_F2 0x0002 130#define MII_MODEL_ATHEROS_F2 0x0002
131#define MII_STR_ATHEROS_F2 "F2 10/100 PHY" 131#define MII_STR_ATHEROS_F2 "F2 10/100 PHY"
132 132
133/* Attansic PHYs */ 133/* Attansic PHYs */
134#define MII_MODEL_ATTANSIC_L1 0x0001 134#define MII_MODEL_ATTANSIC_L1 0x0001
135#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY" 135#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY"
136#define MII_MODEL_ATTANSIC_L2 0x0002 136#define MII_MODEL_ATTANSIC_L2 0x0002
137#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY" 137#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY"
138#define MII_MODEL_ATTANSIC_AR8021 0x0004 138#define MII_MODEL_ATTANSIC_AR8021 0x0004
139#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY" 139#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY"
140#define MII_MODEL_ATTANSIC_AR8035 0x0007 140#define MII_MODEL_ATTANSIC_AR8035 0x0007
141#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY" 141#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY"
142 142
143/* Altima Communications PHYs */ 143/* Altima Communications PHYs */
144/* Don't know the model for ACXXX */ 144/* Don't know the model for ACXXX */
145#define MII_MODEL_ALTIMA_ACXXX 0x0001 145#define MII_MODEL_ALTIMA_ACXXX 0x0001
146#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface" 146#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface"
147#define MII_MODEL_ALTIMA_AC101 0x0021 147#define MII_MODEL_ALTIMA_AC101 0x0021
148#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" 148#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
149#define MII_MODEL_ALTIMA_AC101L 0x0012 149#define MII_MODEL_ALTIMA_AC101L 0x0012
150#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface" 150#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface"
151/* AMD Am79C87[45] have ALTIMA OUI */ 151/* AMD Am79C87[45] have ALTIMA OUI */
152#define MII_MODEL_ALTIMA_Am79C875 0x0014 152#define MII_MODEL_ALTIMA_Am79C875 0x0014
153#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" 153#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
154#define MII_MODEL_ALTIMA_Am79C874 0x0021 154#define MII_MODEL_ALTIMA_Am79C874 0x0021
155#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface" 155#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface"
156 156
157/* Advanced Micro Devices PHYs */ 157/* Advanced Micro Devices PHYs */
158/* see Davicom DM9101 for Am79C873 */ 158/* see Davicom DM9101 for Am79C873 */
159#define MII_MODEL_yyAMD_79C972_10T 0x0001 159#define MII_MODEL_yyAMD_79C972_10T 0x0001
160#define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface" 160#define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface"
161#define MII_MODEL_yyAMD_79c973phy 0x0036 161#define MII_MODEL_yyAMD_79c973phy 0x0036
162#define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface" 162#define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface"
163#define MII_MODEL_yyAMD_79c901 0x0037 163#define MII_MODEL_yyAMD_79c901 0x0037
164#define MII_STR_yyAMD_79c901 "Am79C901 10BASE-T interface" 164#define MII_STR_yyAMD_79c901 "Am79C901 10BASE-T interface"
165#define MII_MODEL_yyAMD_79c901home 0x0039 165#define MII_MODEL_yyAMD_79c901home 0x0039
166#define MII_STR_yyAMD_79c901home "Am79C901 HomePNA 1.0 interface" 166#define MII_STR_yyAMD_79c901home "Am79C901 HomePNA 1.0 interface"
167 167
168/* Broadcom Corp. PHYs */ 168/* Broadcom Corp. PHYs */
169#define MII_MODEL_xxBROADCOM_3C905B 0x0012 169#define MII_MODEL_xxBROADCOM_3C905B 0x0012
170#define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY" 170#define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY"
171#define MII_MODEL_xxBROADCOM_3C905C 0x0017 171#define MII_MODEL_xxBROADCOM_3C905C 0x0017
172#define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY" 172#define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY"
173#define MII_MODEL_xxBROADCOM_BCM5201 0x0021 173#define MII_MODEL_xxBROADCOM_BCM5201 0x0021
174#define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface" 174#define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface"
175#define MII_MODEL_xxBROADCOM_BCM5214 0x0028 175#define MII_MODEL_xxBROADCOM_BCM5214 0x0028
176#define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface" 176#define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface"
177#define MII_MODEL_xxBROADCOM_BCM5221 0x001e 177#define MII_MODEL_xxBROADCOM_BCM5221 0x001e
178#define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface" 178#define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface"
179#define MII_MODEL_xxBROADCOM_BCM5222 0x0032 179#define MII_MODEL_xxBROADCOM_BCM5222 0x0032
180#define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface" 180#define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface"
181#define MII_MODEL_xxBROADCOM_BCM4401 0x0036 181#define MII_MODEL_xxBROADCOM_BCM4401 0x0036
182#define MII_STR_xxBROADCOM_BCM4401 "BCM4401 10/100 media interface" 182#define MII_STR_xxBROADCOM_BCM4401 "BCM4401 10/100 media interface"
183#define MII_MODEL_xxBROADCOM_BCM5365 0x0037 183#define MII_MODEL_xxBROADCOM_BCM5365 0x0037
184#define MII_STR_xxBROADCOM_BCM5365 "BCM5365 10/100 5-port PHY switch" 184#define MII_STR_xxBROADCOM_BCM5365 "BCM5365 10/100 5-port PHY switch"
185#define MII_MODEL_BROADCOM_BCM5400 0x0004 185#define MII_MODEL_BROADCOM_BCM5400 0x0004
186#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface" 186#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface"
187#define MII_MODEL_BROADCOM_BCM5401 0x0005 187#define MII_MODEL_BROADCOM_BCM5401 0x0005
188#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface" 188#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface"
189#define MII_MODEL_BROADCOM_BCM5411 0x0007 189#define MII_MODEL_BROADCOM_BCM5411 0x0007
190#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface" 190#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface"
191#define MII_MODEL_BROADCOM_BCM5464 0x000b 191#define MII_MODEL_BROADCOM_BCM5464 0x000b
192#define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface" 192#define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface"
193#define MII_MODEL_BROADCOM_BCM5461 0x000c 193#define MII_MODEL_BROADCOM_BCM5461 0x000c
194#define MII_STR_BROADCOM_BCM5461 "BCM5461 1000BASE-T media interface" 194#define MII_STR_BROADCOM_BCM5461 "BCM5461 1000BASE-T media interface"
195#define MII_MODEL_BROADCOM_BCM5462 0x000d 195#define MII_MODEL_BROADCOM_BCM5462 0x000d
196#define MII_STR_BROADCOM_BCM5462 "BCM5462 1000BASE-T media interface" 196#define MII_STR_BROADCOM_BCM5462 "BCM5462 1000BASE-T media interface"
197#define MII_MODEL_BROADCOM_BCM5421 0x000e 197#define MII_MODEL_BROADCOM_BCM5421 0x000e
198#define MII_STR_BROADCOM_BCM5421 "BCM5421 1000BASE-T media interface" 198#define MII_STR_BROADCOM_BCM5421 "BCM5421 1000BASE-T media interface"
199#define MII_MODEL_BROADCOM_BCM5752 0x0010 199#define MII_MODEL_BROADCOM_BCM5752 0x0010
200#define MII_STR_BROADCOM_BCM5752 "BCM5752 1000BASE-T media interface" 200#define MII_STR_BROADCOM_BCM5752 "BCM5752 1000BASE-T media interface"
201#define MII_MODEL_BROADCOM_BCM5701 0x0011 201#define MII_MODEL_BROADCOM_BCM5701 0x0011
202#define MII_STR_BROADCOM_BCM5701 "BCM5701 1000BASE-T media interface" 202#define MII_STR_BROADCOM_BCM5701 "BCM5701 1000BASE-T media interface"
203#define MII_MODEL_BROADCOM_BCM5703 0x0016 203#define MII_MODEL_BROADCOM_BCM5703 0x0016
204#define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface" 204#define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface"
205#define MII_MODEL_BROADCOM_BCM5750 0x0018 205#define MII_MODEL_BROADCOM_BCM5750 0x0018
206#define MII_STR_BROADCOM_BCM5750 "BCM5750 1000BASE-T media interface" 206#define MII_STR_BROADCOM_BCM5750 "BCM5750 1000BASE-T media interface"
207#define MII_MODEL_BROADCOM_BCM5704 0x0019 207#define MII_MODEL_BROADCOM_BCM5704 0x0019
208#define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface" 208#define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface"
209#define MII_MODEL_BROADCOM_BCM5705 0x001a 209#define MII_MODEL_BROADCOM_BCM5705 0x001a
210#define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface" 210#define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface"
211#define MII_MODEL_BROADCOM_BCM54K2 0x002e 211#define MII_MODEL_BROADCOM_BCM54K2 0x002e
212#define MII_STR_BROADCOM_BCM54K2 "BCM54K2 1000BASE-T media interface" 212#define MII_STR_BROADCOM_BCM54K2 "BCM54K2 1000BASE-T media interface"
213#define MII_MODEL_BROADCOM_BCM5714 0x0034 213#define MII_MODEL_BROADCOM_BCM5714 0x0034
214#define MII_STR_BROADCOM_BCM5714 "BCM5714 1000BASE-T media interface" 214#define MII_STR_BROADCOM_BCM5714 "BCM5714 1000BASE-T media interface"
215#define MII_MODEL_BROADCOM_BCM5780 0x0035 215#define MII_MODEL_BROADCOM_BCM5780 0x0035
216#define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T media interface" 216#define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T media interface"
217#define MII_MODEL_BROADCOM_BCM5708C 0x0036 217#define MII_MODEL_BROADCOM_BCM5708C 0x0036
218#define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface" 218#define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface"
219#define MII_MODEL_BROADCOM2_BCM5325 0x0003 219#define MII_MODEL_BROADCOM2_BCM5325 0x0003
220#define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch" 220#define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch"
221#define MII_MODEL_BROADCOM2_BCM5906 0x0004 221#define MII_MODEL_BROADCOM2_BCM5906 0x0004
222#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface" 222#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface"
223#define MII_MODEL_BROADCOM2_BCM5481 0x000a 223#define MII_MODEL_BROADCOM2_BCM5481 0x000a
224#define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface" 224#define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface"
225#define MII_MODEL_BROADCOM2_BCM5482 0x000b 225#define MII_MODEL_BROADCOM2_BCM5482 0x000b
226#define MII_STR_BROADCOM2_BCM5482 "BCM5482 1000BASE-T media interface" 226#define MII_STR_BROADCOM2_BCM5482 "BCM5482 1000BASE-T media interface"
227#define MII_MODEL_BROADCOM2_BCM5755 0x000c 227#define MII_MODEL_BROADCOM2_BCM5755 0x000c
228#define MII_STR_BROADCOM2_BCM5755 "BCM5755 1000BASE-T media interface" 228#define MII_STR_BROADCOM2_BCM5755 "BCM5755 1000BASE-T media interface"
229#define MII_MODEL_BROADCOM2_BCM5756 0x000d 229#define MII_MODEL_BROADCOM2_BCM5756 0x000d
230#define MII_STR_BROADCOM2_BCM5756 "BCM5756 1000BASE-T media interface XXX" 230#define MII_STR_BROADCOM2_BCM5756 "BCM5756 1000BASE-T media interface XXX"
231#define MII_MODEL_BROADCOM2_BCM5754 0x000e 231#define MII_MODEL_BROADCOM2_BCM5754 0x000e
232#define MII_STR_BROADCOM2_BCM5754 "BCM5754/5787 1000BASE-T media interface" 232#define MII_STR_BROADCOM2_BCM5754 "BCM5754/5787 1000BASE-T media interface"
233#define MII_MODEL_BROADCOM2_BCM5708S 0x0015 233#define MII_MODEL_BROADCOM2_BCM5708S 0x0015
234#define MII_STR_BROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY" 234#define MII_STR_BROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY"
235#define MII_MODEL_BROADCOM2_BCM5785 0x0016 235#define MII_MODEL_BROADCOM2_BCM5785 0x0016
236#define MII_STR_BROADCOM2_BCM5785 "BCM5785 1000BASE-T media interface" 236#define MII_STR_BROADCOM2_BCM5785 "BCM5785 1000BASE-T media interface"
237#define MII_MODEL_BROADCOM2_BCM5709CAX 0x002c 237#define MII_MODEL_BROADCOM2_BCM5709CAX 0x002c
238#define MII_STR_BROADCOM2_BCM5709CAX "BCM5709CAX 10/100/1000baseT PHY" 238#define MII_STR_BROADCOM2_BCM5709CAX "BCM5709CAX 10/100/1000baseT PHY"
239#define MII_MODEL_BROADCOM2_BCM5722 0x002d 239#define MII_MODEL_BROADCOM2_BCM5722 0x002d
240#define MII_STR_BROADCOM2_BCM5722 "BCM5722 1000BASE-T media interface" 240#define MII_STR_BROADCOM2_BCM5722 "BCM5722 1000BASE-T media interface"
241#define MII_MODEL_BROADCOM2_BCM5784 0x003a 241#define MII_MODEL_BROADCOM2_BCM5784 0x003a
242#define MII_STR_BROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY" 242#define MII_STR_BROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY"
243#define MII_MODEL_BROADCOM2_BCM5709C 0x003c 243#define MII_MODEL_BROADCOM2_BCM5709C 0x003c
244#define MII_STR_BROADCOM2_BCM5709C "BCM5709 10/100/1000baseT PHY" 244#define MII_STR_BROADCOM2_BCM5709C "BCM5709 10/100/1000baseT PHY"
245#define MII_MODEL_BROADCOM2_BCM5761 0x003d 245#define MII_MODEL_BROADCOM2_BCM5761 0x003d
246#define MII_STR_BROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY" 246#define MII_STR_BROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY"
247#define MII_MODEL_BROADCOM2_BCM5709S 0x003f 247#define MII_MODEL_BROADCOM2_BCM5709S 0x003f
248#define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY" 248#define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY"
249#define MII_MODEL_BROADCOM3_BCM57780 0x0019 249#define MII_MODEL_BROADCOM3_BCM57780 0x0019
250#define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface" 250#define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface"
251#define MII_MODEL_BROADCOM3_BCM5717C 0x0020 251#define MII_MODEL_BROADCOM3_BCM5717C 0x0020
252#define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface" 252#define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface"
253#define MII_MODEL_BROADCOM3_BCM5719C 0x0022 253#define MII_MODEL_BROADCOM3_BCM5719C 0x0022
254#define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface" 254#define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface"
255#define MII_MODEL_BROADCOM3_BCM57765 0x0024 255#define MII_MODEL_BROADCOM3_BCM57765 0x0024
256#define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface" 256#define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface"
257#define MII_MODEL_BROADCOM3_BCM5720C 0x0036 257#define MII_MODEL_BROADCOM3_BCM5720C 0x0036
258#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface" 258#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface"
259#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004 259#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004
260#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface" 260#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface"
261  261
262/* Cicada Semiconductor PHYs (now owned by Vitesse?) */ 262/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
263#define MII_MODEL_CICADA_CS8201 0x0001 263#define MII_MODEL_CICADA_CS8201 0x0001
264#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" 264#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
265#define MII_MODEL_CICADA_CS8204 0x0004 265#define MII_MODEL_CICADA_CS8204 0x0004
266#define MII_STR_CICADA_CS8204 "Cicada CS8204 10/100/1000TX PHY" 266#define MII_STR_CICADA_CS8204 "Cicada CS8204 10/100/1000TX PHY"
267#define MII_MODEL_CICADA_VSC8211 0x000b 267#define MII_MODEL_CICADA_VSC8211 0x000b
268#define MII_STR_CICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY" 268#define MII_STR_CICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY"
269#define MII_MODEL_CICADA_CS8201A 0x0020 269#define MII_MODEL_CICADA_CS8201A 0x0020
270#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY" 270#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY"
271#define MII_MODEL_CICADA_CS8201B 0x0021 271#define MII_MODEL_CICADA_CS8201B 0x0021
272#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 272#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
273#define MII_MODEL_xxCICADA_VSC8221 0x0015 273#define MII_MODEL_xxCICADA_VSC8221 0x0015
274#define MII_STR_xxCICADA_VSC8221 "Vitesse VSC8221 10/100/1000BASE-T PHY" 274#define MII_STR_xxCICADA_VSC8221 "Vitesse VSC8221 10/100/1000BASE-T PHY"
275#define MII_MODEL_xxCICADA_VSC8244 0x002c 275#define MII_MODEL_xxCICADA_VSC8244 0x002c
276#define MII_STR_xxCICADA_VSC8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY" 276#define MII_STR_xxCICADA_VSC8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY"
277#define MII_MODEL_xxCICADA_CS8201B 0x0021 277#define MII_MODEL_xxCICADA_CS8201B 0x0021
278#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" 278#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
279 279
280/* Davicom Semiconductor PHYs */ 280/* Davicom Semiconductor PHYs */
281/* AMD Am79C873 seems to be a relabeled DM9101 */ 281/* AMD Am79C873 seems to be a relabeled DM9101 */
282#define MII_MODEL_xxDAVICOM_DM9101 0x0000 282#define MII_MODEL_xxDAVICOM_DM9101 0x0000
283#define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface" 283#define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface"
284#define MII_MODEL_xxDAVICOM_DM9102 0x0004 284#define MII_MODEL_xxDAVICOM_DM9102 0x0004
285#define MII_STR_xxDAVICOM_DM9102 "DM9102 10/100 media interface" 285#define MII_STR_xxDAVICOM_DM9102 "DM9102 10/100 media interface"
286 286
287/* IC Plus Corp. PHYs */ 287/* IC Plus Corp. PHYs */
 288#define MII_MODEL_ICPLUS_IP100 0x0004
 289#define MII_STR_ICPLUS_IP100 "IP100 10/100 PHY"
288#define MII_MODEL_ICPLUS_IP101 0x0005 290#define MII_MODEL_ICPLUS_IP101 0x0005
289#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY" 291#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
 292#define MII_MODEL_ICPLUS_IP1000A 0x0008
 293#define MII_STR_ICPLUS_IP1000A "IP1000A 10/100/1000 PHY"
 294#define MII_MODEL_ICPLUS_IP1001 0x0019
 295#define MII_STR_ICPLUS_IP1001 "IP1001 10/100/1000 PHY"
290 296
291/* Integrated Circuit Systems PHYs */ 297/* Integrated Circuit Systems PHYs */
292#define MII_MODEL_ICS_1889 0x0001 298#define MII_MODEL_ICS_1889 0x0001
293#define MII_STR_ICS_1889 "ICS1889 10/100 media interface" 299#define MII_STR_ICS_1889 "ICS1889 10/100 media interface"
294#define MII_MODEL_ICS_1890 0x0002 300#define MII_MODEL_ICS_1890 0x0002
295#define MII_STR_ICS_1890 "ICS1890 10/100 media interface" 301#define MII_STR_ICS_1890 "ICS1890 10/100 media interface"
296#define MII_MODEL_ICS_1892 0x0003 302#define MII_MODEL_ICS_1892 0x0003
297#define MII_STR_ICS_1892 "ICS1892 10/100 media interface" 303#define MII_STR_ICS_1892 "ICS1892 10/100 media interface"
298#define MII_MODEL_ICS_1893 0x0004 304#define MII_MODEL_ICS_1893 0x0004
299#define MII_STR_ICS_1893 "ICS1893 10/100 media interface" 305#define MII_STR_ICS_1893 "ICS1893 10/100 media interface"
300 306
301/* Intel PHYs */ 307/* Intel PHYs */
302#define MII_MODEL_xxINTEL_I82553 0x0000 308#define MII_MODEL_xxINTEL_I82553 0x0000
303#define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface" 309#define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface"
304#define MII_MODEL_yyINTEL_I82555 0x0015 310#define MII_MODEL_yyINTEL_I82555 0x0015
305#define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface" 311#define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface"
306#define MII_MODEL_yyINTEL_I82562EH 0x0017 312#define MII_MODEL_yyINTEL_I82562EH 0x0017
307#define MII_STR_yyINTEL_I82562EH "i82562EH HomePNA interface" 313#define MII_STR_yyINTEL_I82562EH "i82562EH HomePNA interface"
308#define MII_MODEL_yyINTEL_I82562G 0x0031 314#define MII_MODEL_yyINTEL_I82562G 0x0031
309#define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface" 315#define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface"
310#define MII_MODEL_yyINTEL_I82562EM 0x0032 316#define MII_MODEL_yyINTEL_I82562EM 0x0032
311#define MII_STR_yyINTEL_I82562EM "i82562EM 10/100 media interface" 317#define MII_STR_yyINTEL_I82562EM "i82562EM 10/100 media interface"
312#define MII_MODEL_yyINTEL_I82562ET 0x0033 318#define MII_MODEL_yyINTEL_I82562ET 0x0033
313#define MII_STR_yyINTEL_I82562ET "i82562ET 10/100 media interface" 319#define MII_STR_yyINTEL_I82562ET "i82562ET 10/100 media interface"
314#define MII_MODEL_yyINTEL_I82553 0x0035 320#define MII_MODEL_yyINTEL_I82553 0x0035
315#define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface" 321#define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface"
316#define MII_MODEL_yyINTEL_I82566 0x0039 322#define MII_MODEL_yyINTEL_I82566 0x0039
317#define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface" 323#define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface"
318#define MII_MODEL_INTEL_I82577 0x0005 324#define MII_MODEL_INTEL_I82577 0x0005
319#define MII_STR_INTEL_I82577 "i82577 10/100/1000 media interface" 325#define MII_STR_INTEL_I82577 "i82577 10/100/1000 media interface"
320#define MII_MODEL_INTEL_I82579 0x0009 326#define MII_MODEL_INTEL_I82579 0x0009
321#define MII_STR_INTEL_I82579 "i82579 10/100/1000 media interface" 327#define MII_STR_INTEL_I82579 "i82579 10/100/1000 media interface"
322#define MII_MODEL_INTEL_I217 0x000a 328#define MII_MODEL_INTEL_I217 0x000a
323#define MII_STR_INTEL_I217 "i217 10/100/1000 media interface" 329#define MII_STR_INTEL_I217 "i217 10/100/1000 media interface"
324#define MII_MODEL_xxMARVELL_I210 0x0000 330#define MII_MODEL_xxMARVELL_I210 0x0000
325#define MII_STR_xxMARVELL_I210 "I210 10/100/1000 media interface" 331#define MII_STR_xxMARVELL_I210 "I210 10/100/1000 media interface"
326#define MII_MODEL_xxMARVELL_I82563 0x000a 332#define MII_MODEL_xxMARVELL_I82563 0x000a
327#define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface" 333#define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface"
328 334
329#define MII_MODEL_yyINTEL_IGP01E1000 0x0038 335#define MII_MODEL_yyINTEL_IGP01E1000 0x0038
330#define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY" 336#define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY"
331 337
332/* JMicron PHYs */ 338/* JMicron PHYs */
333#define MII_MODEL_JMICRON_JMC250 0x0021 339#define MII_MODEL_JMICRON_JMC250 0x0021
334#define MII_STR_JMICRON_JMC250 "JMC250 10/100/1000 media interface" 340#define MII_STR_JMICRON_JMC250 "JMC250 10/100/1000 media interface"
335#define MII_MODEL_JMICRON_JMC260 0x0022 341#define MII_MODEL_JMICRON_JMC260 0x0022
336#define MII_STR_JMICRON_JMC260 "JMC260 10/100 media interface" 342#define MII_STR_JMICRON_JMC260 "JMC260 10/100 media interface"
337 343
338/* Level 1 PHYs */ 344/* Level 1 PHYs */
339#define MII_MODEL_xxLEVEL1_LXT970 0x0000 345#define MII_MODEL_xxLEVEL1_LXT970 0x0000
340#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" 346#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
341#define MII_MODEL_LEVEL1_LXT971 0x000e 347#define MII_MODEL_LEVEL1_LXT971 0x000e
342#define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface" 348#define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface"
343#define MII_MODEL_LEVEL1_LXT973 0x0021 349#define MII_MODEL_LEVEL1_LXT973 0x0021
344#define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY" 350#define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY"
345#define MII_MODEL_LEVEL1_LXT974 0x0004 351#define MII_MODEL_LEVEL1_LXT974 0x0004
346#define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY" 352#define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY"
347#define MII_MODEL_LEVEL1_LXT975 0x0005 353#define MII_MODEL_LEVEL1_LXT975 0x0005
348#define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY" 354#define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY"
349#define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003 355#define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003
350#define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface" 356#define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface"
351#define MII_MODEL_LEVEL1_LXT1000 0x000c 357#define MII_MODEL_LEVEL1_LXT1000 0x000c
352#define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface" 358#define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface"
353 359
354/* Marvell Semiconductor PHYs */ 360/* Marvell Semiconductor PHYs */
355#define MII_MODEL_xxMARVELL_E1011 0x0002 361#define MII_MODEL_xxMARVELL_E1011 0x0002
356#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 362#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
357#define MII_MODEL_xxMARVELL_E1000_3 0x0003 363#define MII_MODEL_xxMARVELL_E1000_3 0x0003
358#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 364#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
359#define MII_MODEL_xxMARVELL_E1000_5 0x0005 365#define MII_MODEL_xxMARVELL_E1000_5 0x0005
360#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 366#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
361#define MII_MODEL_xxMARVELL_E6060 0x0008 367#define MII_MODEL_xxMARVELL_E6060 0x0008
362#define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 10/100 5-port PHY switch" 368#define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 10/100 5-port PHY switch"
363#define MII_MODEL_xxMARVELL_E1149 0x000b 369#define MII_MODEL_xxMARVELL_E1149 0x000b
364#define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY" 370#define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
365#define MII_MODEL_xxMARVELL_E1111 0x000c 371#define MII_MODEL_xxMARVELL_E1111 0x000c
366#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 372#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
367#define MII_MODEL_xxMARVELL_E1145 0x000d 373#define MII_MODEL_xxMARVELL_E1145 0x000d
368#define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY" 374#define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY"
369#define MII_MODEL_xxMARVELL_E1116 0x0021 375#define MII_MODEL_xxMARVELL_E1116 0x0021
370#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY" 376#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
371#define MII_MODEL_xxMARVELL_E1116R 0x0024 377#define MII_MODEL_xxMARVELL_E1116R 0x0024
372#define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY" 378#define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
373#define MII_MODEL_xxMARVELL_E1116R_29 0x0029 379#define MII_MODEL_xxMARVELL_E1116R_29 0x0029
374#define MII_STR_xxMARVELL_E1116R_29 "Marvell 88E1116R Gigabit PHY" 380#define MII_STR_xxMARVELL_E1116R_29 "Marvell 88E1116R Gigabit PHY"
375 381
376/* Myson Technology PHYs */ 382/* Myson Technology PHYs */
377#define MII_MODEL_xxMYSON_MTD972 0x0000 383#define MII_MODEL_xxMYSON_MTD972 0x0000
378#define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface" 384#define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface"
379#define MII_MODEL_MYSON_MTD803 0x0000 385#define MII_MODEL_MYSON_MTD803 0x0000
380#define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface" 386#define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface"
381 387
382/* National Semiconductor PHYs */ 388/* National Semiconductor PHYs */
383#define MII_MODEL_xxNATSEMI_DP83840 0x0000 389#define MII_MODEL_xxNATSEMI_DP83840 0x0000
384#define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface" 390#define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface"
385#define MII_MODEL_xxNATSEMI_DP83843 0x0001 391#define MII_MODEL_xxNATSEMI_DP83843 0x0001
386#define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface" 392#define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface"
387#define MII_MODEL_xxNATSEMI_DP83815 0x0002 393#define MII_MODEL_xxNATSEMI_DP83815 0x0002
388#define MII_STR_xxNATSEMI_DP83815 "DP83815 10/100 media interface" 394#define MII_STR_xxNATSEMI_DP83815 "DP83815 10/100 media interface"
389#define MII_MODEL_xxNATSEMI_DP83847 0x0003 395#define MII_MODEL_xxNATSEMI_DP83847 0x0003
390#define MII_STR_xxNATSEMI_DP83847 "DP83847 10/100 media interface" 396#define MII_STR_xxNATSEMI_DP83847 "DP83847 10/100 media interface"
391#define MII_MODEL_xxNATSEMI_DP83891 0x0005 397#define MII_MODEL_xxNATSEMI_DP83891 0x0005
392#define MII_STR_xxNATSEMI_DP83891 "DP83891 1000BASE-T media interface" 398#define MII_STR_xxNATSEMI_DP83891 "DP83891 1000BASE-T media interface"
393#define MII_MODEL_xxNATSEMI_DP83861 0x0006 399#define MII_MODEL_xxNATSEMI_DP83861 0x0006
394#define MII_STR_xxNATSEMI_DP83861 "DP83861 1000BASE-T media interface" 400#define MII_STR_xxNATSEMI_DP83861 "DP83861 1000BASE-T media interface"
395#define MII_MODEL_xxNATSEMI_DP83865 0x0007 401#define MII_MODEL_xxNATSEMI_DP83865 0x0007
396#define MII_STR_xxNATSEMI_DP83865 "DP83865 1000BASE-T media interface" 402#define MII_STR_xxNATSEMI_DP83865 "DP83865 1000BASE-T media interface"
397#define MII_MODEL_xxNATSEMI_DP83849 0x000a 403#define MII_MODEL_xxNATSEMI_DP83849 0x000a
398#define MII_STR_xxNATSEMI_DP83849 "DP83849 10/100 media interface" 404#define MII_STR_xxNATSEMI_DP83849 "DP83849 10/100 media interface"
399 405
400/* PMC Sierra PHYs */ 406/* PMC Sierra PHYs */
401#define MII_MODEL_xxPMCSIERRA_PM8351 0x0000 407#define MII_MODEL_xxPMCSIERRA_PM8351 0x0000
402#define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface" 408#define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface"
403#define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002 409#define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002
404#define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface" 410#define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface"
405#define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003 411#define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003
406#define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface" 412#define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface"
407#define MII_MODEL_PMCSIERRA_PM8354 0x0004 413#define MII_MODEL_PMCSIERRA_PM8354 0x0004
408#define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface" 414#define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface"
409 415
410/* Quality Semiconductor PHYs */ 416/* Quality Semiconductor PHYs */
411#define MII_MODEL_xxQUALSEMI_QS6612 0x0000 417#define MII_MODEL_xxQUALSEMI_QS6612 0x0000
412#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface" 418#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface"
413 419
414/* RDC Semiconductor PHYs */ 420/* RDC Semiconductor PHYs */
415#define MII_MODEL_RDC_R6040 0x0003 421#define MII_MODEL_RDC_R6040 0x0003
416#define MII_STR_RDC_R6040 "R6040 10/100 media interface" 422#define MII_STR_RDC_R6040 "R6040 10/100 media interface"
417/* RealTek PHYs */ 423/* RealTek PHYs */
418#define MII_MODEL_yyREALTEK_RTL8201L 0x0020 424#define MII_MODEL_yyREALTEK_RTL8201L 0x0020
419#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface" 425#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface"
420#define MII_MODEL_xxREALTEK_RTL8169S 0x0011 426#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
421#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 427#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
422#define MII_MODEL_REALTEK_RTL8169S 0x0011 428#define MII_MODEL_REALTEK_RTL8169S 0x0011
423#define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 429#define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
424 430
425/* Seeq PHYs */ 431/* Seeq PHYs */
426#define MII_MODEL_SEEQ_80220 0x0003 432#define MII_MODEL_SEEQ_80220 0x0003
427#define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface" 433#define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface"
428#define MII_MODEL_SEEQ_84220 0x0004 434#define MII_MODEL_SEEQ_84220 0x0004
429#define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface" 435#define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface"
430#define MII_MODEL_SEEQ_80225 0x0008 436#define MII_MODEL_SEEQ_80225 0x0008
431#define MII_STR_SEEQ_80225 "Seeq 80225 10/100 media interface" 437#define MII_STR_SEEQ_80225 "Seeq 80225 10/100 media interface"
432 438
433/* Silicon Integrated Systems PHYs */ 439/* Silicon Integrated Systems PHYs */
434#define MII_MODEL_SIS_900 0x0000 440#define MII_MODEL_SIS_900 0x0000
435#define MII_STR_SIS_900 "SiS 900 10/100 media interface" 441#define MII_STR_SIS_900 "SiS 900 10/100 media interface"
436 442
437/* SMSC PHYs */ 443/* SMSC PHYs */
438#define MII_MODEL_SMSC_LAN8700 0x000c 444#define MII_MODEL_SMSC_LAN8700 0x000c
439#define MII_STR_SMSC_LAN8700 "SMSC LAN8700 10/100 Ethernet Transceiver" 445#define MII_STR_SMSC_LAN8700 "SMSC LAN8700 10/100 Ethernet Transceiver"
440#define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f 446#define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f
441#define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver" 447#define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver"
442 448
443/* Texas Instruments PHYs */ 449/* Texas Instruments PHYs */
444#define MII_MODEL_TI_TLAN10T 0x0001 450#define MII_MODEL_TI_TLAN10T 0x0001
445#define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface" 451#define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface"
446#define MII_MODEL_TI_100VGPMI 0x0002 452#define MII_MODEL_TI_100VGPMI 0x0002
447#define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" 453#define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
448#define MII_MODEL_TI_TNETE2101 0x0003 454#define MII_MODEL_TI_TNETE2101 0x0003
449#define MII_STR_TI_TNETE2101 "TNETE2101 media interface" 455#define MII_STR_TI_TNETE2101 "TNETE2101 media interface"
450 456
451/* TDK Semiconductor PHYs */ 457/* TDK Semiconductor PHYs */
452#define MII_MODEL_xxTSC_78Q2120 0x0014 458#define MII_MODEL_xxTSC_78Q2120 0x0014
453#define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface" 459#define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface"
454#define MII_MODEL_xxTSC_78Q2121 0x0015 460#define MII_MODEL_xxTSC_78Q2121 0x0015
455#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface" 461#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface"
456 462
457/* XaQti Corp. PHYs */ 463/* XaQti Corp. PHYs */
458#define MII_MODEL_xxXAQTI_XMACII 0x0000 464#define MII_MODEL_xxXAQTI_XMACII 0x0000
459#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" 465#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
cvs diff -r1.106 -r1.107 src/sys/dev/mii/miidevs_data.h (switch to unified diff)

--- src/sys/dev/mii/miidevs_data.h 2013/06/02 09:13:27 1.106
+++ src/sys/dev/mii/miidevs_data.h 2013/06/12 02:51:43 1.107
@@ -1,182 +1,185 @@ @@ -1,182 +1,185 @@
1/* $NetBSD: miidevs_data.h,v 1.106 2013/06/02 09:13:27 msaitoh Exp $ */ 1/* $NetBSD: miidevs_data.h,v 1.107 2013/06/12 02:51:43 msaitoh Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.115 2013/06/02 09:13:07 msaitoh Exp 7 * NetBSD: miidevs,v 1.116 2013/06/12 02:51:16 msaitoh Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
21 * 1. Redistributions of source code must retain the above copyright 21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer. 22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright 23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the 24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution. 25 * documentation and/or other materials provided with the distribution.
26 * 26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE. 37 * POSSIBILITY OF SUCH DAMAGE.
38 */ 38 */
39struct mii_knowndev mii_knowndevs[] = { 39struct mii_knowndev mii_knowndevs[] = {
40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 }, 40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
41 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 }, 41 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 },
42 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 }, 42 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 },
43 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 }, 43 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
44 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 }, 44 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
45 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 }, 45 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 },
46 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, MII_STR_ATTANSIC_AR8035 }, 46 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, MII_STR_ATTANSIC_AR8035 },
47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX }, 47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 }, 48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L }, 49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },
50 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 }, 50 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 },
51 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 }, 51 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
52 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T }, 52 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T },
53 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy }, 53 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy },
54 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 }, 54 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 },
55 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home }, 55 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home },
56 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B }, 56 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B },
57 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C }, 57 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C },
58 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 }, 58 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 },
59 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 }, 59 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 },
60 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 }, 60 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 },
61 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5222, MII_STR_xxBROADCOM_BCM5222 }, 61 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5222, MII_STR_xxBROADCOM_BCM5222 },
62 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM4401, MII_STR_xxBROADCOM_BCM4401 }, 62 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM4401, MII_STR_xxBROADCOM_BCM4401 },
63 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5365, MII_STR_xxBROADCOM_BCM5365 }, 63 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5365, MII_STR_xxBROADCOM_BCM5365 },
64 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, MII_STR_BROADCOM_BCM5400 }, 64 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, MII_STR_BROADCOM_BCM5400 },
65 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, MII_STR_BROADCOM_BCM5401 }, 65 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, MII_STR_BROADCOM_BCM5401 },
66 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, MII_STR_BROADCOM_BCM5411 }, 66 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, MII_STR_BROADCOM_BCM5411 },
67 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, MII_STR_BROADCOM_BCM5464 }, 67 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, MII_STR_BROADCOM_BCM5464 },
68 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, MII_STR_BROADCOM_BCM5461 }, 68 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, MII_STR_BROADCOM_BCM5461 },
69 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, MII_STR_BROADCOM_BCM5462 }, 69 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, MII_STR_BROADCOM_BCM5462 },
70 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, MII_STR_BROADCOM_BCM5421 }, 70 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, MII_STR_BROADCOM_BCM5421 },
71 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, MII_STR_BROADCOM_BCM5752 }, 71 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, MII_STR_BROADCOM_BCM5752 },
72 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, MII_STR_BROADCOM_BCM5701 }, 72 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, MII_STR_BROADCOM_BCM5701 },
73 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, MII_STR_BROADCOM_BCM5703 }, 73 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, MII_STR_BROADCOM_BCM5703 },
74 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, MII_STR_BROADCOM_BCM5750 }, 74 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, MII_STR_BROADCOM_BCM5750 },
75 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, MII_STR_BROADCOM_BCM5704 }, 75 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, MII_STR_BROADCOM_BCM5704 },
76 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, MII_STR_BROADCOM_BCM5705 }, 76 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, MII_STR_BROADCOM_BCM5705 },
77 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, MII_STR_BROADCOM_BCM54K2 }, 77 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, MII_STR_BROADCOM_BCM54K2 },
78 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, MII_STR_BROADCOM_BCM5714 }, 78 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, MII_STR_BROADCOM_BCM5714 },
79 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, MII_STR_BROADCOM_BCM5780 }, 79 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, MII_STR_BROADCOM_BCM5780 },
80 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, MII_STR_BROADCOM_BCM5708C }, 80 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, MII_STR_BROADCOM_BCM5708C },
81 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5325, MII_STR_BROADCOM2_BCM5325 }, 81 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5325, MII_STR_BROADCOM2_BCM5325 },
82 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5906, MII_STR_BROADCOM2_BCM5906 }, 82 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5906, MII_STR_BROADCOM2_BCM5906 },
83 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, MII_STR_BROADCOM2_BCM5481 }, 83 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, MII_STR_BROADCOM2_BCM5481 },
84 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, MII_STR_BROADCOM2_BCM5482 }, 84 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, MII_STR_BROADCOM2_BCM5482 },
85 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, MII_STR_BROADCOM2_BCM5755 }, 85 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, MII_STR_BROADCOM2_BCM5755 },
86 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, MII_STR_BROADCOM2_BCM5756 }, 86 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, MII_STR_BROADCOM2_BCM5756 },
87 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, MII_STR_BROADCOM2_BCM5754 }, 87 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, MII_STR_BROADCOM2_BCM5754 },
88 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, MII_STR_BROADCOM2_BCM5708S }, 88 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, MII_STR_BROADCOM2_BCM5708S },
89 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, MII_STR_BROADCOM2_BCM5785 }, 89 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, MII_STR_BROADCOM2_BCM5785 },
90 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, MII_STR_BROADCOM2_BCM5709CAX }, 90 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, MII_STR_BROADCOM2_BCM5709CAX },
91 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, MII_STR_BROADCOM2_BCM5722 }, 91 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, MII_STR_BROADCOM2_BCM5722 },
92 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, MII_STR_BROADCOM2_BCM5784 }, 92 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, MII_STR_BROADCOM2_BCM5784 },
93 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, MII_STR_BROADCOM2_BCM5709C }, 93 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, MII_STR_BROADCOM2_BCM5709C },
94 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, MII_STR_BROADCOM2_BCM5761 }, 94 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, MII_STR_BROADCOM2_BCM5761 },
95 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, MII_STR_BROADCOM2_BCM5709S }, 95 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, MII_STR_BROADCOM2_BCM5709S },
96 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, MII_STR_BROADCOM3_BCM57780 }, 96 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, MII_STR_BROADCOM3_BCM57780 },
97 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, MII_STR_BROADCOM3_BCM5717C }, 97 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, MII_STR_BROADCOM3_BCM5717C },
98 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, MII_STR_BROADCOM3_BCM5719C }, 98 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, MII_STR_BROADCOM3_BCM5719C },
99 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 }, 99 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 },
100 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C }, 100 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C },
101 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 }, 101 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 },
102 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201, MII_STR_CICADA_CS8201 }, 102 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201, MII_STR_CICADA_CS8201 },
103 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8204, MII_STR_CICADA_CS8204 }, 103 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8204, MII_STR_CICADA_CS8204 },
104 { MII_OUI_CICADA, MII_MODEL_CICADA_VSC8211, MII_STR_CICADA_VSC8211 }, 104 { MII_OUI_CICADA, MII_MODEL_CICADA_VSC8211, MII_STR_CICADA_VSC8211 },
105 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201A, MII_STR_CICADA_CS8201A }, 105 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201A, MII_STR_CICADA_CS8201A },
106 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201B, MII_STR_CICADA_CS8201B }, 106 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201B, MII_STR_CICADA_CS8201B },
107 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8221, MII_STR_xxCICADA_VSC8221 }, 107 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8221, MII_STR_xxCICADA_VSC8221 },
108 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8244, MII_STR_xxCICADA_VSC8244 }, 108 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8244, MII_STR_xxCICADA_VSC8244 },
109 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CS8201B, MII_STR_xxCICADA_CS8201B }, 109 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CS8201B, MII_STR_xxCICADA_CS8201B },
110 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 }, 110 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 },
111 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9102, MII_STR_xxDAVICOM_DM9102 }, 111 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9102, MII_STR_xxDAVICOM_DM9102 },
 112 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP100, MII_STR_ICPLUS_IP100 },
112 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP101, MII_STR_ICPLUS_IP101 }, 113 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP101, MII_STR_ICPLUS_IP101 },
 114 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP1000A, MII_STR_ICPLUS_IP1000A },
 115 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP1001, MII_STR_ICPLUS_IP1001 },
113 { MII_OUI_ICS, MII_MODEL_ICS_1889, MII_STR_ICS_1889 }, 116 { MII_OUI_ICS, MII_MODEL_ICS_1889, MII_STR_ICS_1889 },
114 { MII_OUI_ICS, MII_MODEL_ICS_1890, MII_STR_ICS_1890 }, 117 { MII_OUI_ICS, MII_MODEL_ICS_1890, MII_STR_ICS_1890 },
115 { MII_OUI_ICS, MII_MODEL_ICS_1892, MII_STR_ICS_1892 }, 118 { MII_OUI_ICS, MII_MODEL_ICS_1892, MII_STR_ICS_1892 },
116 { MII_OUI_ICS, MII_MODEL_ICS_1893, MII_STR_ICS_1893 }, 119 { MII_OUI_ICS, MII_MODEL_ICS_1893, MII_STR_ICS_1893 },
117 { MII_OUI_xxINTEL, MII_MODEL_xxINTEL_I82553, MII_STR_xxINTEL_I82553 }, 120 { MII_OUI_xxINTEL, MII_MODEL_xxINTEL_I82553, MII_STR_xxINTEL_I82553 },
118 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82555, MII_STR_yyINTEL_I82555 }, 121 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82555, MII_STR_yyINTEL_I82555 },
119 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562EH, MII_STR_yyINTEL_I82562EH }, 122 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562EH, MII_STR_yyINTEL_I82562EH },
120 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562G, MII_STR_yyINTEL_I82562G }, 123 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562G, MII_STR_yyINTEL_I82562G },
121 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562EM, MII_STR_yyINTEL_I82562EM }, 124 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562EM, MII_STR_yyINTEL_I82562EM },
122 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562ET, MII_STR_yyINTEL_I82562ET }, 125 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562ET, MII_STR_yyINTEL_I82562ET },
123 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82553, MII_STR_yyINTEL_I82553 }, 126 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82553, MII_STR_yyINTEL_I82553 },
124 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82566, MII_STR_yyINTEL_I82566 }, 127 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82566, MII_STR_yyINTEL_I82566 },
125 { MII_OUI_INTEL, MII_MODEL_INTEL_I82577, MII_STR_INTEL_I82577 }, 128 { MII_OUI_INTEL, MII_MODEL_INTEL_I82577, MII_STR_INTEL_I82577 },
126 { MII_OUI_INTEL, MII_MODEL_INTEL_I82579, MII_STR_INTEL_I82579 }, 129 { MII_OUI_INTEL, MII_MODEL_INTEL_I82579, MII_STR_INTEL_I82579 },
127 { MII_OUI_INTEL, MII_MODEL_INTEL_I217, MII_STR_INTEL_I217 }, 130 { MII_OUI_INTEL, MII_MODEL_INTEL_I217, MII_STR_INTEL_I217 },
128 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I210, MII_STR_xxMARVELL_I210 }, 131 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I210, MII_STR_xxMARVELL_I210 },
129 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I82563, MII_STR_xxMARVELL_I82563 }, 132 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I82563, MII_STR_xxMARVELL_I82563 },
130 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_IGP01E1000, MII_STR_yyINTEL_IGP01E1000 }, 133 { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_IGP01E1000, MII_STR_yyINTEL_IGP01E1000 },
131 { MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC250, MII_STR_JMICRON_JMC250 }, 134 { MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC250, MII_STR_JMICRON_JMC250 },
132 { MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC260, MII_STR_JMICRON_JMC260 }, 135 { MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC260, MII_STR_JMICRON_JMC260 },
133 { MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 }, 136 { MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 },
134 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 }, 137 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 },
135 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 }, 138 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 },
136 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT974, MII_STR_LEVEL1_LXT974 }, 139 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT974, MII_STR_LEVEL1_LXT974 },
137 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 }, 140 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 },
138 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD }, 141 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD },
139 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 }, 142 { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 },
140 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 }, 143 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 },
141 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 }, 144 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 },
142 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5, MII_STR_xxMARVELL_E1000_5 }, 145 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5, MII_STR_xxMARVELL_E1000_5 },
143 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E6060, MII_STR_xxMARVELL_E6060 }, 146 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E6060, MII_STR_xxMARVELL_E6060 },
144 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149, MII_STR_xxMARVELL_E1149 }, 147 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149, MII_STR_xxMARVELL_E1149 },
145 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111, MII_STR_xxMARVELL_E1111 }, 148 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111, MII_STR_xxMARVELL_E1111 },
146 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145, MII_STR_xxMARVELL_E1145 }, 149 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145, MII_STR_xxMARVELL_E1145 },
147 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116, MII_STR_xxMARVELL_E1116 }, 150 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116, MII_STR_xxMARVELL_E1116 },
148 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R, MII_STR_xxMARVELL_E1116R }, 151 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R, MII_STR_xxMARVELL_E1116R },
149 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R_29, MII_STR_xxMARVELL_E1116R_29 }, 152 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R_29, MII_STR_xxMARVELL_E1116R_29 },
150 { MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 }, 153 { MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
151 { MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 }, 154 { MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 },
152 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 }, 155 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
153 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 }, 156 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 },
154 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 }, 157 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 },
155 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 }, 158 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 },
156 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 }, 159 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 },
157 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 }, 160 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 },
158 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 }, 161 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 },
159 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83849, MII_STR_xxNATSEMI_DP83849 }, 162 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83849, MII_STR_xxNATSEMI_DP83849 },
160 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 }, 163 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 },
161 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 }, 164 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 },
162 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8353, MII_STR_xxPMCSIERRA2_PM8353 }, 165 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8353, MII_STR_xxPMCSIERRA2_PM8353 },
163 { MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 }, 166 { MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 },
164 { MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 }, 167 { MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 },
165 { MII_OUI_RDC, MII_MODEL_RDC_R6040, MII_STR_RDC_R6040 }, 168 { MII_OUI_RDC, MII_MODEL_RDC_R6040, MII_STR_RDC_R6040 },
166 { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L }, 169 { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L },
167 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S }, 170 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S },
168 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, MII_STR_REALTEK_RTL8169S }, 171 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, MII_STR_REALTEK_RTL8169S },
169 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 }, 172 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 },
170 { MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 }, 173 { MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 },
171 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80225, MII_STR_SEEQ_80225 }, 174 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80225, MII_STR_SEEQ_80225 },
172 { MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 }, 175 { MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 },
173 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8700, MII_STR_SMSC_LAN8700 }, 176 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8700, MII_STR_SMSC_LAN8700 },
174 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8710_LAN8720, MII_STR_SMSC_LAN8710_LAN8720 }, 177 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8710_LAN8720, MII_STR_SMSC_LAN8710_LAN8720 },
175 { MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T }, 178 { MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T },
176 { MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI }, 179 { MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI },
177 { MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 }, 180 { MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 },
178 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 }, 181 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 },
179 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 }, 182 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 },
180 { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII }, 183 { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII },
181 { 0, 0, NULL } 184 { 0, 0, NULL }
182}; 185};