Wed Jun 12 05:25:58 2013 UTC ()
Fix ARM_PRF1_SEC_MASK value.


(matt)
diff -r1.77 -r1.78 src/sys/arch/arm/include/armreg.h
cvs diff -r1.77 -r1.78 src/sys/arch/arm/include/armreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/include/armreg.h 2013/06/12 02:08:02 1.77
+++ src/sys/arch/arm/include/armreg.h 2013/06/12 05:25:58 1.78
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armreg.h,v 1.77 2013/06/12 02:08:02 matt Exp $ */ 1/* $NetBSD: armreg.h,v 1.78 2013/06/12 05:25:58 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1998, 2001 Ben Harris 4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini. 6 * Copyright (c) 1994 Brini.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * This code is derived from software written for Brini by Mark Brinicombe 9 * This code is derived from software written for Brini by Mark Brinicombe
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -251,27 +251,27 @@ @@ -251,27 +251,27 @@
251#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 251#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
252#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 252#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
253#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 253#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
254#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 254#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
255/* Marvell's CPUIDs with ARM ID in implementor field */ 255/* Marvell's CPUIDs with ARM ID in implementor field */
256#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 256#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
257#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 257#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
258#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 258#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
259 259
260/* CPUID registers */ 260/* CPUID registers */
261#define ARM_PFR0_THUMBEE_MASK 0x0000f000 261#define ARM_PFR0_THUMBEE_MASK 0x0000f000
262#define ARM_PFR1_GTIMER_MASK 0x000f0000 262#define ARM_PFR1_GTIMER_MASK 0x000f0000
263#define ARM_PFR1_VIRT_MASK 0x0000f000 263#define ARM_PFR1_VIRT_MASK 0x0000f000
264#define ARM_PFR1_SEC_MASK 0x00000f00 264#define ARM_PFR1_SEC_MASK 0x000000f0
265 265
266/* ARM3-specific coprocessor 15 registers */ 266/* ARM3-specific coprocessor 15 registers */
267#define ARM3_CP15_FLUSH 1 267#define ARM3_CP15_FLUSH 1
268#define ARM3_CP15_CONTROL 2 268#define ARM3_CP15_CONTROL 2
269#define ARM3_CP15_CACHEABLE 3 269#define ARM3_CP15_CACHEABLE 3
270#define ARM3_CP15_UPDATEABLE 4 270#define ARM3_CP15_UPDATEABLE 4
271#define ARM3_CP15_DISRUPTIVE 5  271#define ARM3_CP15_DISRUPTIVE 5
272 272
273/* ARM3 Control register bits */ 273/* ARM3 Control register bits */
274#define ARM3_CTL_CACHE_ON 0x00000001 274#define ARM3_CTL_CACHE_ON 0x00000001
275#define ARM3_CTL_SHARED 0x00000002 275#define ARM3_CTL_SHARED 0x00000002
276#define ARM3_CTL_MONITOR 0x00000004 276#define ARM3_CTL_MONITOR 0x00000004
277 277