Wed Jun 12 15:10:13 2013 UTC ()
Deal with __ARM_FIQ_INDIRECT


(matt)
diff -r1.5 -r1.6 src/sys/arch/arm/arm/vectors.S
cvs diff -r1.5 -r1.6 src/sys/arch/arm/arm/vectors.S (expand / switch to unified diff)

--- src/sys/arch/arm/arm/vectors.S 2013/06/12 07:17:23 1.5
+++ src/sys/arch/arm/arm/vectors.S 2013/06/12 15:10:13 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: vectors.S,v 1.5 2013/06/12 07:17:23 matt Exp $ */ 1/* $NetBSD: vectors.S,v 1.6 2013/06/12 15:10:13 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (C) 1994-1997 Mark Brinicombe 4 * Copyright (C) 1994-1997 Mark Brinicombe
5 * Copyright (C) 1994 Brini 5 * Copyright (C) 1994 Brini
6 * All rights reserved.  6 * All rights reserved.
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
10 * are met: 10 * are met:
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
@@ -55,27 +55,31 @@ @@ -55,27 +55,31 @@
55 * Since we are in kernel, we can just do a relative branch to the 55 * Since we are in kernel, we can just do a relative branch to the
56 * exception code and avoid the intermediate load. 56 * exception code and avoid the intermediate load.
57 */ 57 */
58 .global _C_LABEL(page0rel) 58 .global _C_LABEL(page0rel)
59 .p2align 5 59 .p2align 5
60_C_LABEL(page0rel): 60_C_LABEL(page0rel):
61 b reset_entry 61 b reset_entry
62 b undefined_entry 62 b undefined_entry
63 b swi_entry 63 b swi_entry
64 b prefetch_abort_entry 64 b prefetch_abort_entry
65 b data_abort_entry 65 b data_abort_entry
66 b address_exception_entry 66 b address_exception_entry
67 b irq_entry 67 b irq_entry
 68#ifdef __ARM_FIQ_INDIRECT
68 b _C_LABEL(fiqvector) 69 b _C_LABEL(fiqvector)
 70#else
 71 b .Lfiqvector
 72#endif
69#endif 73#endif
70 74
71_C_LABEL(page0): 75_C_LABEL(page0):
72 ldr pc, .Lreset_target 76 ldr pc, .Lreset_target
73 ldr pc, .Lundefined_target 77 ldr pc, .Lundefined_target
74 ldr pc, .Lswi_target 78 ldr pc, .Lswi_target
75 ldr pc, .Lprefetch_abort_target 79 ldr pc, .Lprefetch_abort_target
76 ldr pc, .Ldata_abort_target 80 ldr pc, .Ldata_abort_target
77 ldr pc, .Laddress_exception_target 81 ldr pc, .Laddress_exception_target
78 ldr pc, .Lirq_target 82 ldr pc, .Lirq_target
79#ifdef __ARM_FIQ_INDIRECT 83#ifdef __ARM_FIQ_INDIRECT
80 ldr pc, .Lfiq_target 84 ldr pc, .Lfiq_target
81#else 85#else