 @@ -1,14 +1,14 @@
-/*	$NetBSD: fiq.c,v 1.6 2008/11/19 06:29:48 matt Exp $	*/
+/*	$NetBSD: fiq.c,v 1.7 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -26,52 +26,53 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.6 2008/11/19 06:29:48 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.7 2013/06/12 21:34:12 matt Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <arm/cpufunc.h>
 #include <arm/fiq.h>
 #ifdef __PROG32
 #include <uvm/uvm.h>
 #endif
 TAILQ_HEAD(, fiqhandler) fiqhandler_stack =
     TAILQ_HEAD_INITIALIZER(fiqhandler_stack);
 extern char fiqvector[];
 extern char fiq_nullhandler[], fiq_nullhandler_end[];
 #ifdef __PROG32
 #define	IRQ_BIT		I32_bit
 #define	FIQ_BIT		F32_bit
 #else
 #define	IRQ_BIT		R15_IRQ_DISABLE
 #define	FIQ_BIT		R15_FIQ_DISABLE
 #endif /* __PROG32 */
 #ifndef ARM_HAS_VBAR
 /*
  * fiq_installhandler:
+ *
  *	Actually install the FIQ handler down at the FIQ vector.
+ *
  *	Note: If the FIQ is invoked via an extra layer of
  *	indirection, the actual FIQ code store lives in the
  *	data segment, so there is no need to manipulate
  *	the vector page's protection.
  */
 static void
 fiq_installhandler(void *func, size_t size)
+{
 @@ -166,13 +167,14 @@ fiq_release(struct fiqhandler *fh)
 	if (TAILQ_FIRST(&fiqhandler_stack) == NULL) {
 		/* Copy the NULL handler back down into the vector. */
 		fiq_installhandler(fiq_nullhandler,
 		    (size_t)(fiq_nullhandler_end - fiq_nullhandler));
 		/* Make sure FIQs are disabled when we return. */
 		oldirqstate |= FIQ_BIT;
+	}
 	oldirqstate &= ~FIQ_BIT;
 	restore_interrupts(oldirqstate);
+}
 #endif /* !ARM_HAS_VBAR */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: vectors.S,v 1.6 2013/06/12 15:10:13 matt Exp $	*/
+/*	$NetBSD: vectors.S,v 1.7 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright (C) 1994-1997 Mark Brinicombe
  * Copyright (C) 1994 Brini
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -23,82 +23,91 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include "assym.h"
 #include "opt_cputypes.h"
 #include "opt_cpuoptions.h"
 #include <machine/asm.h>
 /*
  * These are the exception vectors copied down to page 0.
+ *
  * Note that FIQs are special; rather than using a level of
  * indirection, we actually copy the FIQ code down into the
  * vector page.
  */
 	.text
 	.align	0
 	.global	_C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
 	.global _C_LABEL(fiqvector)
-#if defined(CPU_ARMV7) || defined(CPU_ARM11)
+#if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR)
 	/*
 	 * ARMv[67] processors with the Security Extension have the VBAR
 	 * which redirects the low vector to any 32-byte aligned address.
 	 * Since we are in kernel, we can just do a relative branch to the
 	 * exception code and avoid the intermediate load.
 	 */
 	.global	_C_LABEL(page0rel)
 	.p2align 5
 _C_LABEL(page0rel):
 	b	reset_entry
 	b	undefined_entry
 	b	swi_entry
 	b	prefetch_abort_entry
 	b	data_abort_entry
 	b	address_exception_entry
 	b	irq_entry
 #ifdef __ARM_FIQ_INDIRECT
 	b	_C_LABEL(fiqvector)
-#else
+#elif !defined(ARM_HAS_VBAR)
 	b	.Lfiqvector
 #endif
-#endif
+#endif /* CPU_ARMV7 || CPU_ARM11 || ARM_HAS_VBAR */
 #ifndef ARM_HAS_VBAR
 	.global	_C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
 	.align	0
 _C_LABEL(page0):
 	ldr	pc, .Lreset_target
 	ldr	pc, .Lundefined_target
 	ldr	pc, .Lswi_target
 	ldr	pc, .Lprefetch_abort_target
 	ldr	pc, .Ldata_abort_target
 	ldr	pc, .Laddress_exception_target
 	ldr	pc, .Lirq_target
 #ifdef __ARM_FIQ_INDIRECT
 	ldr	pc, .Lfiq_target
-#else
+#endif
 #endif /* !ARM_HAS_VBAR */
 #ifndef __ARM_FIQ_INDIRECT
 .Lfiqvector:
 #ifdef ARM_HAS_VBAR
 	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0rel)
 #else
 	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0)
 #endif
 	subs	pc, lr, #4
 	.org	.Lfiqvector + 0x100
 #endif
 #ifndef ARM_HAS_VBAR
 _C_LABEL(page0_data):
 .Lreset_target:
 	.word	reset_entry
 .Lundefined_target:
 	.word	undefined_entry
 .Lswi_target:
 	.word	swi_entry
 .Lprefetch_abort_target:
 	.word	prefetch_abort_entry
 @@ -108,21 +117,22 @@ _C_LABEL(page0_data):
 .Laddress_exception_target:
 	.word	address_exception_entry
 .Lirq_target:
 	.word	irq_entry
 #ifdef __ARM_FIQ_INDIRECT
 .Lfiq_target:
 	.word	_C_LABEL(fiqvector)
 #else
 	.word	0	/* pad it out */
 #endif
 _C_LABEL(page0_end):
 #endif /* ARM_HAS_VBAR */
 #ifdef __ARM_FIQ_INDIRECT
 	.data
 	.align	0
 _C_LABEL(fiqvector):
 	subs	pc, lr, #4
 	.org	_C_LABEL(fiqvector) + 0x100
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: arm32_kvminit.c,v 1.19 2013/06/12 17:13:05 matt Exp $	*/
+/*	$NetBSD: arm32_kvminit.c,v 1.20 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright (c) 2002, 2003, 2005  Genetec Corporation.  All rights reserved.
  * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -112,27 +112,27 @@
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.19 2013/06/12 17:13:05 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.20 2013/06/12 21:34:12 matt Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/reboot.h>
 #include <sys/bus.h>
 #include <dev/cons.h>
 #include <uvm/uvm_extern.h>
 #include <arm/db_machdep.h>
 #include <arm/undefined.h>
 @@ -362,27 +362,29 @@ valloc_pages(struct bootmem_info *bmi, p
 		memset((void *)pv->pv_va, 0, nbytes);
+}
 void
 arm32_kernel_vm_init(vaddr_t kernel_vm_base, vaddr_t vectors, vaddr_t iovbase,
 	const struct pmap_devmap *devmap, bool mapallmem_p)
+{
 	struct bootmem_info * const bmi = &bootmem_info;
 #ifdef MULTIPROCESSOR
 	const size_t cpu_num = arm_cpu_max + 1;
 #else
 	const size_t cpu_num = 1;
 #endif
-#if defined(CPU_ARMV7) || defined(CPU_ARM11)
+#ifdef ARM_HAS_VBAR
 	const bool map_vectors_p = false;
 #elif defined(CPU_ARMV7) || defined(CPU_ARM11)
 	const bool map_vectors_p = vectors == ARM_VECTORS_LOW
 	    && !(armreg_pfr1_read() & ARM_PFR1_SEC_MASK);
 #else
 	const bool map_vectors_p = true;
 #endif
 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
 	KASSERT(mapallmem_p);
 #endif
 	/*
 	 * Calculate the number of L2 pages needed for mapping the
 	 * kernel + data + stuff.  Assume 2 L2 pages for kernel, 1 for vectors,

 @@ -1,14 +1,14 @@
-/*	$NetBSD: arm32_machdep.c,v 1.93 2013/06/12 17:13:05 matt Exp $	*/
+/*	$NetBSD: arm32_machdep.c,v 1.94 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright (c) 1994-1998 Mark Brinicombe.
  * Copyright (c) 1994 Brini.
  * All rights reserved.
+ *
  * This code is derived from software written for Brini by Mark Brinicombe
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -32,27 +32,27 @@
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * Machine dependent functions for kernel setup
+ *
  * Created      : 17/09/94
  * Updated	: 18/04/01 updated for new wscons
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.93 2013/06/12 17:13:05 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.94 2013/06/12 21:34:12 matt Exp $");
 #include "opt_modular.h"
 #include "opt_md.h"
 #include "opt_pmap_debug.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/reboot.h>
 #include <sys/proc.h>
 #include <sys/kauth.h>
 #include <sys/kernel.h>
 #include <sys/mbuf.h>
 #include <sys/mount.h>
 @@ -120,45 +120,50 @@ extern void configure(void);
 /*
  * arm32_vector_init:
+ *
  *	Initialize the vector page, and select whether or not to
  *	relocate the vectors.
+ *
  *	NOTE: We expect the vector page to be mapped at its expected
  *	destination.
  */
 void
 arm32_vector_init(vaddr_t va, int which)
+{
-#if defined(CPU_ARMV7) || defined(CPU_ARM11)
+#if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR)
 	/*
 	 * If this processor has the security extension, don't bother
 	 * to move/map the vector page.  Simply point VBAR to the copy
 	 * that exists in the .text segment.
 	 */
 #ifndef ARM_HAS_VBAR
 	if (va == ARM_VECTORS_LOW
 	    && (armreg_pfr1_read() && ARM_PFR1_SEC_MASK) != 0) {
 #endif
 		extern const uint32_t page0rel[];
 		vector_page = (vaddr_t)page0rel;
 		KASSERT((vector_page & 0x1f) == 0);
 		armreg_vbar_write(vector_page);
 #ifdef VERBOSE_INIT_ARM
 		printf(" vbar=%p", page0rel);
 #endif
 		cpu_control(CPU_CONTROL_VECRELOC, 0);
 		return;
 #ifndef ARM_HAS_VBAR
+	}
 #endif
 #endif
 #ifndef ARM_HAS_VBAR
 	if (CPU_IS_PRIMARY(curcpu())) {
 		extern unsigned int page0[], page0_data[];
 		unsigned int *vectors = (int *) va;
 		unsigned int *vectors_data = vectors + (page0_data - page0);
 		int vec;
 		/*
 		 * Loop through the vectors we're taking over, and copy the
 		 * vector's insn and data word.
 		 */
 		for (vec = 0; vec < ARM_NVEC; vec++) {
 			if ((which & (1 << vec)) == 0) {
 				/* Don't want to take over this vector. */
 @@ -183,26 +188,27 @@ arm32_vector_init(vaddr_t va, int which)
 		 * cpu_setup()) because the vector page needs to be
 		 * accessible *before* cpu_startup() is called.
 		 * Think ddb(9) ...
+		 *
 		 * NOTE: If the CPU control register is not readable,
 		 * this will totally fail!  We'll just assume that
 		 * any system that has high vector support has a
 		 * readable CPU control register, for now.  If we
 		 * ever encounter one that does not, we'll have to
 		 * rethink this.
 		 */
 		cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC);
+	}
 #endif
+}
 /*
  * Debug function just to park the CPU
  */
 void
 halt(void)
+{
 	while (1)
 		cpu_sleep(0);
+}
 @@ -247,28 +253,30 @@ cpu_startup(void)
 	vaddr_t minaddr;
 	vaddr_t maxaddr;
 	u_int loop;
 	char pbuf[9];
 	/*
 	 * Until we better locking, we have to live under the kernel lock.
 	 */
 	//KERNEL_LOCK(1, NULL);
 	/* Set the CPU control register */
 	cpu_setup(boot_args);
 #ifndef ARM_HAS_VBAR
 	/* Lock down zero page */
 	vector_page_setprot(VM_PROT_READ);
 #endif
 	/*
 	 * Give pmap a chance to set up a few more things now the vm
 	 * is initialised
 	 */
 	pmap_postinit();
 	/*
 	 * Initialize error message buffer (at end of core).
 	 */
 	/* msgbufphys was setup during the secondary boot strap */
 	for (loop = 0; loop < btoc(MSGBUFSIZE); ++loop)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.256 2013/06/12 07:13:18 matt Exp $	*/
+/*	$NetBSD: pmap.c,v 1.257 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright 2003 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -202,27 +202,27 @@
 #include <sys/cdefs.h>
 #include <sys/cpu.h>
 #include <sys/sysctl.h>
 #include <uvm/uvm.h>
 #include <sys/bus.h>
 #include <machine/pmap.h>
 #include <machine/pcb.h>
 #include <machine/param.h>
 #include <arm/cpuconf.h>
 #include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.256 2013/06/12 07:13:18 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.257 2013/06/12 21:34:12 matt Exp $");
 #ifdef PMAP_DEBUG
 /* XXX need to get rid of all refs to this */
 int pmap_debug_level = 0;
 /*
  * for switching to potentially finer grained debugging
  */
 #define	PDB_FOLLOW	0x0001
 #define	PDB_INIT	0x0002
 #define	PDB_ENTER	0x0004
 #define	PDB_REMOVE	0x0008
 @@ -1544,43 +1544,45 @@ pmap_l2dtable_ctor(void *arg, void *v, i
+}
 static int
 pmap_pmap_ctor(void *arg, void *v, int flags)
+{
 	memset(v, 0, sizeof(struct pmap));
 	return (0);
+}
 static void
 pmap_pinit(pmap_t pm)
+{
 #ifndef ARM_HAS_VBAR
 	struct l2_bucket *l2b;
 	if (vector_page < KERNEL_BASE) {
 		/*
 		 * Map the vector page.
 		 */
 		pmap_enter(pm, vector_page, systempage.pv_pa,
 		    VM_PROT_READ, VM_PROT_READ | PMAP_WIRED);
 		pmap_update(pm);
 		pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
 		l2b = pmap_get_l2_bucket(pm, vector_page);
 		KDASSERT(l2b != NULL);
 		pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO |
 		    L1_C_DOM(pm->pm_domain);
 	} else
 		pm->pm_pl1vec = NULL;
 #endif
+}
 #ifdef PMAP_CACHE_VIVT
 /*
  * Since we have a virtually indexed cache, we may need to inhibit caching if
  * there is more than one mapping and at least one of them is writable.
  * Since we purge the cache on every context switch, we only need to check for
  * other mappings within the same pmap, or kernel_pmap.
  * This function is also called when a page is unmapped, to possibly reenable
  * caching on any remaining mappings.
+ *
  * The code implements the following logic, where:
+ *
 @@ -2813,26 +2815,31 @@ arm32_mmap_flags(paddr_t pa)
  *      NB:  This is the only routine which MAY NOT lazy-evaluate
  *      or lose information.  That is, this routine must actually
  *      insert this page into the given map NOW.
  */
 int
 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
+{
 	struct l2_bucket *l2b;
 	struct vm_page *pg, *opg;
 	struct pv_entry *pv;
 	pt_entry_t *ptep, npte, opte;
 	u_int nflags;
 	u_int oflags;
 #ifdef ARM_HAS_VBAR
 	const bool vector_page_p = false;
 #else
 	const bool vector_page_p = (va == vector_page);
 #endif
 	NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags));
 	KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0);
 	KDASSERT(((va | pa) & PGOFSET) == 0);
 	/*
 	 * Get a pointer to the page.  Later on in this function, we
 	 * test for a managed page by checking pg != NULL.
 	 */
 	pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL;
 	nflags = 0;
 @@ -3004,28 +3011,28 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
 	} else {
 		/*
 		 * We're mapping an unmanaged page.
 		 * These are always readable, and possibly writable, from
 		 * the get go as we don't need to track ref/mod status.
 		 */
 		npte |= l2pte_set_readonly(L2_S_PROTO);
 		if (prot & VM_PROT_WRITE)
 			npte = l2pte_set_writable(npte);
 		/*
 		 * Make sure the vector table is mapped cacheable
 		 */
-		if ((pm != pmap_kernel() && va == vector_page) ||
+		if ((vector_page_p && pm != pmap_kernel())
-		    (flags & ARM32_MMAP_CACHEABLE)) {
+		    || (flags & ARM32_MMAP_CACHEABLE)) {
 			npte |= pte_l2_s_cache_mode;
 		} else if (flags & ARM32_MMAP_WRITECOMBINE) {
 			npte |= pte_l2_s_wc_mode;
+		}
 		if (opg) {
 			/*
 			 * Looks like there's an existing 'managed' mapping
 			 * at this address.
 			 */
 			struct vm_page_md *omd = VM_PAGE_TO_MD(opg);
 			paddr_t opa = VM_PAGE_TO_PHYS(opg);
 #ifdef MULTIPROCESSOR
 @@ -3043,55 +3050,56 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
 				else
 				if (PV_BEEN_REFD(oflags))
 					pmap_dcache_wb_range(pm, va, PAGE_SIZE,
 					    true, (oflags & PVF_WRITE) == 0);
+			}
 #endif
 			pool_put(&pmap_pv_pool, pv);
+		}
+	}
 	/*
 	 * Make sure userland mappings get the right permissions
 	 */
-	if (pm != pmap_kernel() && va != vector_page)
+	if (!vector_page_p && pm != pmap_kernel()) {
 		npte |= L2_S_PROT_U;
+	}
 	/*
 	 * Keep the stats up to date
 	 */
 	if (opte == 0) {
 		l2b->l2b_occupancy++;
 		pm->pm_stats.resident_count++;
+	}
 	NPDEBUG(PDB_ENTER,
 	    printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte));
 	/*
 	 * If this is just a wiring change, the two PTEs will be
 	 * identical, so there's no need to update the page table.
 	 */
 	if (npte != opte) {
 		bool is_cached = pmap_is_cached(pm);
 		*ptep = npte;
 		PTE_SYNC(ptep);
 		if (is_cached) {
 			/*
 			 * We only need to frob the cache/tlb if this pmap
 			 * is current
 			 */
-			if (va != vector_page && l2pte_valid(npte)) {
+			if (!vector_page_p && l2pte_valid(npte)) {
 				/*
 				 * This mapping is likely to be accessed as
 				 * soon as we return to userland. Fix up the
 				 * L1 entry to avoid taking another
 				 * page/domain fault.
 				 */
 				pd_entry_t *pl1pd, l1pd;
 				pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)];
 				l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) |
 				    L1_C_PROTO;
 				if (*pl1pd != l1pd) {
 					*pl1pd = l1pd;
 @@ -4272,38 +4280,40 @@ pmap_activate(struct lwp *l)
 	if (rpm) {
 		rpm->pm_cstate.cs_cache = 0;
 		if (npm == pmap_kernel())
 			pmap_recent_user = NULL;
 #ifdef PMAP_CACHE_VIVT
 		cpu_idcache_wbinv_all();
 #endif
+	}
 #endif
 	/* No interrupts while we frob the TTB/DACR */
 	oldirqstate = disable_interrupts(IF32_bits);
 #ifndef ARM_HAS_VBAR
 	/*
 	 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1
 	 * entry corresponding to 'vector_page' in the incoming L1 table
 	 * before switching to it otherwise subsequent interrupts/exceptions
 	 * (including domain faults!) will jump into hyperspace.
 	 */
 	if (npm->pm_pl1vec != NULL) {
 		cpu_tlb_flushID_SE((u_int)vector_page);
 		cpu_cpwait();
 		*npm->pm_pl1vec = npm->pm_l1vec;
 		PTE_SYNC(npm->pm_pl1vec);
+	}
 #endif
 	cpu_domains(ndacr);
 	if (npm == pmap_kernel() || npm == rpm) {
 		/*
 		 * Switching to a kernel thread, or back to the
 		 * same user vmspace as before... Simply update
 		 * the TTB (no TLB flush required)
 		 */
 		cpu_setttb(npm->pm_l1->l1_physaddr, false);
 		cpu_cpwait();
 	} else {
 		/*
 @@ -4429,33 +4439,35 @@ pmap_destroy(pmap_t pm)
 	if (count > 0) {
 		if (pmap_is_current(pm)) {
 			if (pm != pmap_kernel())
 				pmap_use_l1(pm);
 			pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL;
+		}
 		return;
+	}
 	/*
 	 * reference count is zero, free pmap resources and then free pmap.
 	 */
 #ifndef ARM_HAS_VBAR
 	if (vector_page < KERNEL_BASE) {
 		KDASSERT(!pmap_is_current(pm));
 		/* Remove the vector page mapping */
 		pmap_remove(pm, vector_page, vector_page + PAGE_SIZE);
 		pmap_update(pm);
+	}
 #endif
 	LIST_REMOVE(pm, pm_list);
 	pmap_free_l1(pm);
 	if (pmap_recent_user == pm)
 		pmap_recent_user = NULL;
 	uvm_obj_destroy(&pm->pm_obj, false);
 	mutex_destroy(&pm->pm_obj_lock);
 	pool_cache_put(&pmap_cache, pm);
+}
 @@ -5114,26 +5126,27 @@ pmap_growkernel(vaddr_t maxkvaddr)
 	cpu_dcache_wbinv_all();
 	cpu_tlb_flushD();
 	cpu_cpwait();
 	mutex_exit(kpm->pm_lock);
 	splx(s);
 out:
 	return (pmap_curmaxkvaddr);
+}
 /************************ Utility routines ****************************/
 #ifndef ARM_HAS_VBAR
 /*
  * vector_page_setprot:
+ *
  *	Manipulate the protection of the vector page.
  */
 void
 vector_page_setprot(int prot)
+{
 	struct l2_bucket *l2b;
 	pt_entry_t *ptep;
 #if defined(CPU_ARMV7) || defined(CPU_ARM11)
 	/*
 @@ -5146,26 +5159,27 @@ vector_page_setprot(int prot)
+	}
 #endif
 	l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
 	KDASSERT(l2b != NULL);
 	ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
 	*ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
 	PTE_SYNC(ptep);
 	cpu_tlb_flushD_SE(vector_page);
 	cpu_cpwait();
+}
 #endif
 /*
  * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
  * Returns true if the mapping exists, else false.
+ *
  * NOTE: This function is only used by a couple of arm-specific modules.
  * It is not safe to take any pmap locks here, since we could be right
  * in the middle of debugging the pmap anyway...
+ *
  * It is possible for this routine to return false even though a valid
  * mapping does exist. This is because we don't lock, so the metadata
  * state may be inconsistent.
+ *
 @@ -5428,35 +5442,37 @@ pmap_bootstrap(vaddr_t vstart, vaddr_t v
 	/*
 	 * init the static-global locks and global pmap list.
 	 */
 	mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM);
 	/*
 	 * We can now initialise the first L1's metadata.
 	 */
 	SLIST_INIT(&l1_list);
 	TAILQ_INIT(&l1_lru_list);
 	pmap_init_l1(l1, l1pt);
 #ifndef ARM_HAS_VBAR
 	/* Set up vector page L1 details, if necessary */
 	if (vector_page < KERNEL_BASE) {
 		pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
 		l2b = pmap_get_l2_bucket(pm, vector_page);
 		KDASSERT(l2b != NULL);
 		pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO |
 		    L1_C_DOM(pm->pm_domain);
 	} else
 		pm->pm_pl1vec = NULL;
 #endif
 	/*
 	 * Initialize the pmap cache
 	 */
 	pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0,
 	    "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL);
 	LIST_INIT(&pmap_pmaps);
 	LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list);
 	/*
 	 * Initialize the pv pool.
 	 */
 	pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl",

 @@ -1,14 +1,14 @@
-#	$NetBSD: files.arm,v 1.118 2013/06/12 07:12:10 matt Exp $
+#	$NetBSD: files.arm,v 1.119 2013/06/12 21:34:12 matt Exp $
 # temporary define to allow easy moving to ../arch/arm/arm32
 defflag				ARM32
 # CPU types.  Make sure to update <arm/cpuconf.h> if you change this list.
 defflag	opt_cputypes.h		CPU_ARM2 CPU_ARM250 CPU_ARM3
 defflag	opt_cputypes.h		CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
 				CPU_ARM9 CPU_ARM9E CPU_ARM10 CPU_ARM11 CPU_ARMV7
 				CPU_SA110 CPU_SA1100 CPU_SA1110 CPU_IXP12X0
 				CPU_FA526 CPU_XSCALE_80200 CPU_XSCALE_80321
 				CPU_XSCALE_PXA250 CPU_XSCALE_PXA270
 				CPU_XSCALE_IXP425
 				CPU_SHEEVA
 @@ -26,26 +26,27 @@ defflag opt_cputypes.h		FPU_VFP
 defparam opt_cpuoptions.h	XSCALE_CCLKCFG
 defflag  opt_cpuoptions.h	XSCALE_CACHE_WRITE_THROUGH
 defflag  opt_cpuoptions.h	XSCALE_CACHE_WRITE_BACK
 defflag  opt_cpuoptions.h	XSCALE_NO_COALESCE_WRITES
 defflag  opt_cpuoptions.h	XSCALE_CACHE_READ_WRITE_ALLOCATE
 defflag  opt_cpuoptions.h	ARM32_DISABLE_ALIGNMENT_FAULTS
 defflag  opt_cpuoptions.h	ARM9_CACHE_WRITE_THROUGH
 defflag  opt_cpuoptions.h	TPIDRPRW_IS_CURLWP
 defflag  opt_cpuoptions.h	TPIDRPRW_IS_CURCPU
 defflag  opt_cpuoptions.h	ARM11_PMC CORTEX_PMC
 defflag  opt_cpuoptions.h	ARM11_CACHE_WRITE_THROUGH
 defflag	 opt_cpuoptions.h	ARM11MPCORE_COMPAT_MMU
 defflag	 opt_cpuoptions.h	ARM_USE_VBAR
 # use extended small page in compatible MMU mode for ARMv6
 defflag  opt_cpuoptions.h	ARMV6_EXTENDED_SMALL_PAGE
 # Interrupt implementation header definition.
 defparam opt_arm_intr_impl.h	ARM_INTR_IMPL
 # ARM-specific debug options
 defflag	opt_arm_debug.h		ARM_LOCK_CAS_DEBUG
 # Board-specific bus_space(9)/bus_dma(9) definitions
 defflag  opt_arm_bus_space.h	__BUS_SPACE_HAS_STREAM_METHODS
 				_ARM32_NEED_BUS_DMA_BOUNCE
 				BUSDMA_COUNTERS

 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.h,v 1.119 2012/12/12 15:09:37 matt Exp $	*/
+/*	$NetBSD: pmap.h,v 1.120 2013/06/12 21:34:12 matt Exp $	*/
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -176,27 +176,29 @@ struct pmap_devmap {
 	psize_t		pd_size;	/* size of region */
 	vm_prot_t	pd_prot;	/* protection code */
 	int		pd_cache;	/* cache attributes */
 };
 /*
  * The pmap structure itself
  */
 struct pmap {
 	uint8_t			pm_domain;
 	bool			pm_remove_all;
 	bool			pm_activated;
 	struct l1_ttable	*pm_l1;
 #ifndef ARM_HAS_VBAR
 	pd_entry_t		*pm_pl1vec;
 #endif
 	pd_entry_t		pm_l1vec;
 	union pmap_cache_state	pm_cstate;
 	struct uvm_object	pm_obj;
 	kmutex_t		pm_obj_lock;
 #define	pm_lock pm_obj.vmobjlock
 	struct l2_dtable	*pm_l2[L2_SIZE];
 	struct pmap_statistics	pm_stats;
 	LIST_ENTRY(pmap)	pm_list;
 };
 /*
  * Physical / virtual address structure. In a number of places (particularly
  * during bootstrapping) we need to keep track of the physical and virtual