Thu Jun 13 07:22:45 2013 UTC ()
Pull up following revision(s) (requested by martin in ticket #896):
	sys/dev/ic/iavc.c: revision 1.10
	sys/netisdn/i4b_capi_llif.c: revision 1.6
	sys/netisdn/i4b_capi.h: revision 1.6
Fix signature of capi_ll_control.
From Wolfgang Stukenbrock in PR kern/47863.


(msaitoh)
diff -r1.8 -r1.8.20.1 src/sys/dev/ic/iavc.c
diff -r1.5 -r1.5.94.1 src/sys/netisdn/i4b_capi.h
diff -r1.5 -r1.5.18.1 src/sys/netisdn/i4b_capi_llif.c
cvs diff -r1.8 -r1.8.20.1 src/sys/dev/ic/Attic/iavc.c (switch to unified diff)

--- src/sys/dev/ic/Attic/iavc.c 2009/01/23 19:49:16 1.8
+++ src/sys/dev/ic/Attic/iavc.c 2013/06/13 07:22:44 1.8.20.1
@@ -1,1092 +1,1092 @@ @@ -1,1092 +1,1092 @@
1/* $NetBSD: iavc.c,v 1.8 2009/01/23 19:49:16 christos Exp $ */ 1/* $NetBSD: iavc.c,v 1.8.20.1 2013/06/13 07:22:44 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved. 4 * Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE. 25 * SUCH DAMAGE.
26 * 26 *
27 * The AVM ISDN controllers' card specific support routines. 27 * The AVM ISDN controllers' card specific support routines.
28 * 28 *
29 * $FreeBSD: src/sys/i4b/capi/iavc/iavc_card.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $ 29 * $FreeBSD: src/sys/i4b/capi/iavc/iavc_card.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: iavc.c,v 1.8 2009/01/23 19:49:16 christos Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: iavc.c,v 1.8.20.1 2013/06/13 07:22:44 msaitoh Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/kernel.h> 36#include <sys/kernel.h>
37#include <sys/systm.h> 37#include <sys/systm.h>
38#include <sys/mbuf.h> 38#include <sys/mbuf.h>
39#include <sys/socket.h> 39#include <sys/socket.h>
40#include <sys/device.h> 40#include <sys/device.h>
41#include <sys/callout.h> 41#include <sys/callout.h>
42#include <sys/reboot.h> 42#include <sys/reboot.h>
43#include <net/if.h> 43#include <net/if.h>
44 44
45#include <sys/bus.h> 45#include <sys/bus.h>
46 46
47#include <netisdn/i4b_debug.h> 47#include <netisdn/i4b_debug.h>
48#include <netisdn/i4b_ioctl.h> 48#include <netisdn/i4b_ioctl.h>
49#include <netisdn/i4b_trace.h> 49#include <netisdn/i4b_trace.h>
50#include <netisdn/i4b_global.h> 50#include <netisdn/i4b_global.h>
51#include <netisdn/i4b_l3l4.h> 51#include <netisdn/i4b_l3l4.h>
52#include <netisdn/i4b_mbuf.h> 52#include <netisdn/i4b_mbuf.h>
53#include <netisdn/i4b_capi.h> 53#include <netisdn/i4b_capi.h>
54#include <netisdn/i4b_capi_msgs.h> 54#include <netisdn/i4b_capi_msgs.h>
55 55
56#include <dev/ic/iavcvar.h> 56#include <dev/ic/iavcvar.h>
57#include <dev/ic/iavcreg.h> 57#include <dev/ic/iavcreg.h>
58 58
59/* 59/*
60// AVM B1 (active BRI, PIO mode) 60// AVM B1 (active BRI, PIO mode)
61*/ 61*/
62 62
63int 63int
64iavc_b1_detect(iavc_softc_t *sc) 64iavc_b1_detect(iavc_softc_t *sc)
65{ 65{
66 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) || 66 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
67 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc)) 67 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
68 return (1); 68 return (1);
69 69
70 b1io_outp(sc, B1_INSTAT, 0x02); 70 b1io_outp(sc, B1_INSTAT, 0x02);
71 b1io_outp(sc, B1_OUTSTAT, 0x02); 71 b1io_outp(sc, B1_OUTSTAT, 0x02);
72 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 || 72 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
73 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2) 73 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
74 return (2); 74 return (2);
75 75
76 b1io_outp(sc, B1_INSTAT, 0x00); 76 b1io_outp(sc, B1_INSTAT, 0x00);
77 b1io_outp(sc, B1_OUTSTAT, 0x00); 77 b1io_outp(sc, B1_OUTSTAT, 0x00);
78 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) || 78 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
79 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe)) 79 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
80 return (3); 80 return (3);
81 81
82 return (0); /* found */ 82 return (0); /* found */
83} 83}
84 84
85void 85void
86iavc_b1_disable_irq(iavc_softc_t *sc) 86iavc_b1_disable_irq(iavc_softc_t *sc)
87{ 87{
88 b1io_outp(sc, B1_INSTAT, 0x00); 88 b1io_outp(sc, B1_INSTAT, 0x00);
89} 89}
90 90
91void 91void
92iavc_b1_reset(iavc_softc_t *sc) 92iavc_b1_reset(iavc_softc_t *sc)
93{ 93{
94 b1io_outp(sc, B1_RESET, 0); 94 b1io_outp(sc, B1_RESET, 0);
95 DELAY(55*2*1000); 95 DELAY(55*2*1000);
96 96
97 b1io_outp(sc, B1_RESET, 1); 97 b1io_outp(sc, B1_RESET, 1);
98 DELAY(55*2*1000); 98 DELAY(55*2*1000);
99 99
100 b1io_outp(sc, B1_RESET, 0); 100 b1io_outp(sc, B1_RESET, 0);
101 DELAY(55*2*1000); 101 DELAY(55*2*1000);
102} 102}
103 103
104/* 104/*
105// Newer PCI-based B1's, and T1's, supports DMA 105// Newer PCI-based B1's, and T1's, supports DMA
106*/ 106*/
107 107
108int 108int
109iavc_b1dma_detect(iavc_softc_t *sc) 109iavc_b1dma_detect(iavc_softc_t *sc)
110{ 110{
111 AMCC_WRITE(sc, AMCC_MCSR, 0); 111 AMCC_WRITE(sc, AMCC_MCSR, 0);
112 DELAY(10*1000); 112 DELAY(10*1000);
113 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000); 113 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
114 DELAY(10*1000); 114 DELAY(10*1000);
115 AMCC_WRITE(sc, AMCC_MCSR, 0); 115 AMCC_WRITE(sc, AMCC_MCSR, 0);
116 DELAY(42*1000); 116 DELAY(42*1000);
117 117
118 AMCC_WRITE(sc, AMCC_RXLEN, 0); 118 AMCC_WRITE(sc, AMCC_RXLEN, 0);
119 AMCC_WRITE(sc, AMCC_TXLEN, 0); 119 AMCC_WRITE(sc, AMCC_TXLEN, 0);
120 sc->sc_csr = 0; 120 sc->sc_csr = 0;
121 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 121 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
122 122
123 if (AMCC_READ(sc, AMCC_INTCSR) != 0) 123 if (AMCC_READ(sc, AMCC_INTCSR) != 0)
124 return 1; 124 return 1;
125 125
126 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff); 126 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
127 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff); 127 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
128 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) || 128 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
129 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc)) 129 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
130 return 2; 130 return 2;
131 131
132 AMCC_WRITE(sc, AMCC_RXPTR, 0); 132 AMCC_WRITE(sc, AMCC_RXPTR, 0);
133 AMCC_WRITE(sc, AMCC_TXPTR, 0); 133 AMCC_WRITE(sc, AMCC_TXPTR, 0);
134 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) || 134 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
135 (AMCC_READ(sc, AMCC_TXPTR) != 0)) 135 (AMCC_READ(sc, AMCC_TXPTR) != 0))
136 return 3; 136 return 3;
137 137
138 iavc_write_port(sc, 0x10, 0x00); 138 iavc_write_port(sc, 0x10, 0x00);
139 iavc_write_port(sc, 0x07, 0x00); 139 iavc_write_port(sc, 0x07, 0x00);
140 140
141 iavc_write_port(sc, 0x02, 0x02); 141 iavc_write_port(sc, 0x02, 0x02);
142 iavc_write_port(sc, 0x03, 0x02); 142 iavc_write_port(sc, 0x03, 0x02);
143 143
144 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) || 144 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
145 (iavc_read_port(sc, 0x03) != 0x03)) 145 (iavc_read_port(sc, 0x03) != 0x03))
146 return 4; 146 return 4;
147 147
148 iavc_write_port(sc, 0x02, 0x00); 148 iavc_write_port(sc, 0x02, 0x00);
149 iavc_write_port(sc, 0x03, 0x00); 149 iavc_write_port(sc, 0x03, 0x00);
150 150
151 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) || 151 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
152 (iavc_read_port(sc, 0x03) != 0x01)) 152 (iavc_read_port(sc, 0x03) != 0x01))
153 return 5; 153 return 5;
154 154
155 return (0); /* found */ 155 return (0); /* found */
156} 156}
157 157
158void 158void
159iavc_b1dma_reset(iavc_softc_t *sc) 159iavc_b1dma_reset(iavc_softc_t *sc)
160{ 160{
161 int s = splnet(); 161 int s = splnet();
162 162
163 sc->sc_csr = 0; 163 sc->sc_csr = 0;
164 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 164 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
165 AMCC_WRITE(sc, AMCC_MCSR, 0); 165 AMCC_WRITE(sc, AMCC_MCSR, 0);
166 AMCC_WRITE(sc, AMCC_RXLEN, 0); 166 AMCC_WRITE(sc, AMCC_RXLEN, 0);
167 AMCC_WRITE(sc, AMCC_TXLEN, 0); 167 AMCC_WRITE(sc, AMCC_TXLEN, 0);
168 168
169 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */ 169 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
170 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */ 170 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
171 171
172 splx(s); 172 splx(s);
173 173
174 AMCC_WRITE(sc, AMCC_MCSR, 0); 174 AMCC_WRITE(sc, AMCC_MCSR, 0);
175 DELAY(10 * 1000); 175 DELAY(10 * 1000);
176 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000); 176 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
177 DELAY(10 * 1000); 177 DELAY(10 * 1000);
178 AMCC_WRITE(sc, AMCC_MCSR, 0); 178 AMCC_WRITE(sc, AMCC_MCSR, 0);
179 DELAY(42 * 1000); 179 DELAY(42 * 1000);
180} 180}
181 181
182/* 182/*
183// AVM T1 (active PRI) 183// AVM T1 (active PRI)
184*/ 184*/
185 185
186#define b1dma_tx_empty(sc) (b1io_read_reg((sc), T1_OUTSTAT) & 1) 186#define b1dma_tx_empty(sc) (b1io_read_reg((sc), T1_OUTSTAT) & 1)
187#define b1dma_rx_full(sc) (b1io_read_reg((sc), T1_INSTAT) & 1) 187#define b1dma_rx_full(sc) (b1io_read_reg((sc), T1_INSTAT) & 1)
188 188
189static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len) 189static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
190{ 190{
191 volatile int spin; 191 volatile int spin;
192 char *s = (char*) buf; 192 char *s = (char*) buf;
193 while (len--) { 193 while (len--) {
194 spin = 0; 194 spin = 0;
195 while (!b1dma_tx_empty(sc) && spin < 100000) 195 while (!b1dma_tx_empty(sc) && spin < 100000)
196 spin++; 196 spin++;
197 if (!b1dma_tx_empty(sc)) 197 if (!b1dma_tx_empty(sc))
198 return -1; 198 return -1;
199 t1io_outp(sc, 1, *s++); 199 t1io_outp(sc, 1, *s++);
200 } 200 }
201 return 0; 201 return 0;
202} 202}
203 203
204static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len) 204static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
205{ 205{
206 volatile int spin; 206 volatile int spin;
207 char *s = (char*) buf; 207 char *s = (char*) buf;
208 while (len--) { 208 while (len--) {
209 spin = 0; 209 spin = 0;
210 while (!b1dma_rx_full(sc) && spin < 100000) 210 while (!b1dma_rx_full(sc) && spin < 100000)
211 spin++; 211 spin++;
212 if (!b1dma_rx_full(sc)) 212 if (!b1dma_rx_full(sc))
213 return -1; 213 return -1;
214 *s++ = t1io_inp(sc, 0); 214 *s++ = t1io_inp(sc, 0);
215 } 215 }
216 return 0; 216 return 0;
217} 217}
218 218
219static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val) 219static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
220{ 220{
221 u_int8_t cmd = 0; 221 u_int8_t cmd = 0;
222 if (b1dma_tolink(sc, &cmd, 1) == 0 && 222 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
223 b1dma_tolink(sc, &reg, 4) == 0) { 223 b1dma_tolink(sc, &reg, 4) == 0) {
224 u_int32_t tmp = val; 224 u_int32_t tmp = val;
225 return b1dma_tolink(sc, &tmp, 4); 225 return b1dma_tolink(sc, &tmp, 4);
226 } 226 }
227 return -1; 227 return -1;
228} 228}
229 229
230static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg) 230static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg)
231{ 231{
232 u_int8_t cmd = 1; 232 u_int8_t cmd = 1;
233 if (b1dma_tolink(sc, &cmd, 1) == 0 && 233 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
234 b1dma_tolink(sc, &reg, 4) == 0) { 234 b1dma_tolink(sc, &reg, 4) == 0) {
235 u_int32_t tmp; 235 u_int32_t tmp;
236 if (b1dma_fromlink(sc, &tmp, 4) == 0) 236 if (b1dma_fromlink(sc, &tmp, 4) == 0)
237 return (u_int8_t) tmp; 237 return (u_int8_t) tmp;
238 } 238 }
239 return 0xff; 239 return 0xff;
240} 240}
241 241
242int 242int
243iavc_t1_detect(iavc_softc_t *sc) 243iavc_t1_detect(iavc_softc_t *sc)
244{ 244{
245 int ret = iavc_b1dma_detect(sc); 245 int ret = iavc_b1dma_detect(sc);
246 if (ret) return ret; 246 if (ret) return ret;
247 247
248 if ((WriteReg(sc, 0x80001000, 0x11) != 0) || 248 if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
249 (WriteReg(sc, 0x80101000, 0x22) != 0) || 249 (WriteReg(sc, 0x80101000, 0x22) != 0) ||
250 (WriteReg(sc, 0x80201000, 0x33) != 0) || 250 (WriteReg(sc, 0x80201000, 0x33) != 0) ||
251 (WriteReg(sc, 0x80301000, 0x44) != 0)) 251 (WriteReg(sc, 0x80301000, 0x44) != 0))
252 return 6; 252 return 6;
253 253
254 if ((ReadReg(sc, 0x80001000) != 0x11) || 254 if ((ReadReg(sc, 0x80001000) != 0x11) ||
255 (ReadReg(sc, 0x80101000) != 0x22) || 255 (ReadReg(sc, 0x80101000) != 0x22) ||
256 (ReadReg(sc, 0x80201000) != 0x33) || 256 (ReadReg(sc, 0x80201000) != 0x33) ||
257 (ReadReg(sc, 0x80301000) != 0x44)) 257 (ReadReg(sc, 0x80301000) != 0x44))
258 return 7; 258 return 7;
259 259
260 if ((WriteReg(sc, 0x80001000, 0x55) != 0) || 260 if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
261 (WriteReg(sc, 0x80101000, 0x66) != 0) || 261 (WriteReg(sc, 0x80101000, 0x66) != 0) ||
262 (WriteReg(sc, 0x80201000, 0x77) != 0) || 262 (WriteReg(sc, 0x80201000, 0x77) != 0) ||
263 (WriteReg(sc, 0x80301000, 0x88) != 0)) 263 (WriteReg(sc, 0x80301000, 0x88) != 0))
264 return 8; 264 return 8;
265 265
266 if ((ReadReg(sc, 0x80001000) != 0x55) || 266 if ((ReadReg(sc, 0x80001000) != 0x55) ||
267 (ReadReg(sc, 0x80101000) != 0x66) || 267 (ReadReg(sc, 0x80101000) != 0x66) ||
268 (ReadReg(sc, 0x80201000) != 0x77) || 268 (ReadReg(sc, 0x80201000) != 0x77) ||
269 (ReadReg(sc, 0x80301000) != 0x88)) 269 (ReadReg(sc, 0x80301000) != 0x88))
270 return 9; 270 return 9;
271 271
272 return 0; /* found */ 272 return 0; /* found */
273} 273}
274 274
275void 275void
276iavc_t1_disable_irq(iavc_softc_t *sc) 276iavc_t1_disable_irq(iavc_softc_t *sc)
277{ 277{
278 iavc_write_port(sc, T1_IRQMASTER, 0x00); 278 iavc_write_port(sc, T1_IRQMASTER, 0x00);
279} 279}
280 280
281void 281void
282iavc_t1_reset(iavc_softc_t *sc) 282iavc_t1_reset(iavc_softc_t *sc)
283{ 283{
284 iavc_b1_reset(sc); 284 iavc_b1_reset(sc);
285 iavc_write_port(sc, B1_INSTAT, 0x00); 285 iavc_write_port(sc, B1_INSTAT, 0x00);
286 iavc_write_port(sc, B1_OUTSTAT, 0x00); 286 iavc_write_port(sc, B1_OUTSTAT, 0x00);
287 iavc_write_port(sc, T1_IRQMASTER, 0x00); 287 iavc_write_port(sc, T1_IRQMASTER, 0x00);
288 iavc_write_port(sc, T1_RESETBOARD, 0x0f); 288 iavc_write_port(sc, T1_RESETBOARD, 0x0f);
289} 289}
290 290
291/* Forward declarations of local subroutines... */ 291/* Forward declarations of local subroutines... */
292 292
293static int iavc_send_init(iavc_softc_t *); 293static int iavc_send_init(iavc_softc_t *);
294 294
295static void iavc_handle_rx(iavc_softc_t *); 295static void iavc_handle_rx(iavc_softc_t *);
296static void iavc_start_tx(iavc_softc_t *); 296static void iavc_start_tx(iavc_softc_t *);
297 297
298static uint32_t iavc_tx_capimsg(iavc_softc_t *, struct mbuf *); 298static uint32_t iavc_tx_capimsg(iavc_softc_t *, struct mbuf *);
299static uint32_t iavc_tx_ctrlmsg(iavc_softc_t *, struct mbuf *); 299static uint32_t iavc_tx_ctrlmsg(iavc_softc_t *, struct mbuf *);
300 300
301/* 301/*
302// Callbacks from the upper (capi) layer: 302// Callbacks from the upper (capi) layer:
303// -------------------------------------- 303// --------------------------------------
304// 304//
305// iavc_load 305// iavc_load
306// Resets the board and loads the firmware, then initiates 306// Resets the board and loads the firmware, then initiates
307// board startup. 307// board startup.
308// 308//
309// iavc_register 309// iavc_register
310// Registers a CAPI application id. 310// Registers a CAPI application id.
311// 311//
312// iavc_release 312// iavc_release
313// Releases a CAPI application id. 313// Releases a CAPI application id.
314// 314//
315// iavc_send 315// iavc_send
316// Sends a capi message. 316// Sends a capi message.
317*/ 317*/
318 318
319int iavc_load(capi_softc_t *capi_sc, int len, u_int8_t *cp) 319int iavc_load(capi_softc_t *capi_sc, int len, u_int8_t *cp)
320{ 320{
321 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx; 321 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx;
322 u_int8_t val; 322 u_int8_t val;
323 323
324 aprint_debug_dev(&sc->sc_dev, "reset card ....\n"); 324 aprint_debug_dev(&sc->sc_dev, "reset card ....\n");
325 325
326 if (sc->sc_dma) 326 if (sc->sc_dma)
327 iavc_b1dma_reset(sc); /* PCI cards */ 327 iavc_b1dma_reset(sc); /* PCI cards */
328 else if (sc->sc_t1) 328 else if (sc->sc_t1)
329 iavc_t1_reset(sc); /* ISA attachment T1 */ 329 iavc_t1_reset(sc); /* ISA attachment T1 */
330 else 330 else
331 iavc_b1_reset(sc); /* ISA attachment B1 */ 331 iavc_b1_reset(sc); /* ISA attachment B1 */
332 332
333 DELAY(1000); 333 DELAY(1000);
334 334
335 aprint_debug_dev(&sc->sc_dev, "start loading %d bytes firmware\n", len); 335 aprint_debug_dev(&sc->sc_dev, "start loading %d bytes firmware\n", len);
336 336
337 while (len && b1io_save_put_byte(sc, *cp++) == 0) 337 while (len && b1io_save_put_byte(sc, *cp++) == 0)
338 len--; 338 len--;
339 339
340 if (len) { 340 if (len) {
341 aprint_error_dev(&sc->sc_dev, "loading failed, can't write to card, len = %d\n", len); 341 aprint_error_dev(&sc->sc_dev, "loading failed, can't write to card, len = %d\n", len);
342 return (EIO); 342 return (EIO);
343 } 343 }
344 344
345 aprint_debug_dev(&sc->sc_dev, "firmware loaded, wait for ACK\n"); 345 aprint_debug_dev(&sc->sc_dev, "firmware loaded, wait for ACK\n");
346 346
347 if(sc->sc_capi.card_type == CARD_TYPEC_AVM_B1_ISA) 347 if(sc->sc_capi.card_type == CARD_TYPEC_AVM_B1_ISA)
348 iavc_put_byte(sc, SEND_POLL); 348 iavc_put_byte(sc, SEND_POLL);
349 else 349 else
350 iavc_put_byte(sc, SEND_POLLACK); 350 iavc_put_byte(sc, SEND_POLLACK);
351 351
352 for (len = 0; len < 1000 && !iavc_rx_full(sc); len++) 352 for (len = 0; len < 1000 && !iavc_rx_full(sc); len++)
353 DELAY(100); 353 DELAY(100);
354 354
355 if (!iavc_rx_full(sc)) { 355 if (!iavc_rx_full(sc)) {
356 aprint_error_dev(&sc->sc_dev, "loading failed, no ack\n"); 356 aprint_error_dev(&sc->sc_dev, "loading failed, no ack\n");
357 return (EIO); 357 return (EIO);
358 } 358 }
359 359
360 val = iavc_get_byte(sc); 360 val = iavc_get_byte(sc);
361 361
362 if ((sc->sc_dma && val != RECEIVE_POLLDWORD) || 362 if ((sc->sc_dma && val != RECEIVE_POLLDWORD) ||
363 (!sc->sc_dma && val != RECEIVE_POLL)) { 363 (!sc->sc_dma && val != RECEIVE_POLL)) {
364 aprint_error_dev(&sc->sc_dev, "loading failed, bad ack = %02x\n", val); 364 aprint_error_dev(&sc->sc_dev, "loading failed, bad ack = %02x\n", val);
365 return (EIO); 365 return (EIO);
366 } 366 }
367 367
368 aprint_debug_dev(&sc->sc_dev, "got ACK = 0x%02x\n", val); 368 aprint_debug_dev(&sc->sc_dev, "got ACK = 0x%02x\n", val);
369 369
370 /* Start the DMA engine */ 370 /* Start the DMA engine */
371 if (sc->sc_dma) { 371 if (sc->sc_dma) {
372 int s; 372 int s;
373 373
374 s = splnet(); 374 s = splnet();
375 375
376 sc->sc_csr = AVM_FLAG; 376 sc->sc_csr = AVM_FLAG;
377 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 377 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
378 AMCC_WRITE(sc, AMCC_MCSR, (EN_A2P_TRANSFERS|EN_P2A_TRANSFERS| 378 AMCC_WRITE(sc, AMCC_MCSR, (EN_A2P_TRANSFERS|EN_P2A_TRANSFERS|
379 A2P_HI_PRIORITY|P2A_HI_PRIORITY| 379 A2P_HI_PRIORITY|P2A_HI_PRIORITY|
380 RESET_A2P_FLAGS|RESET_P2A_FLAGS)); 380 RESET_A2P_FLAGS|RESET_P2A_FLAGS));
381 381
382 iavc_write_port(sc, 0x07, 0x30); /* XXX magic numbers from */ 382 iavc_write_port(sc, 0x07, 0x30); /* XXX magic numbers from */
383 iavc_write_port(sc, 0x10, 0xf0); /* XXX the linux driver */ 383 iavc_write_port(sc, 0x10, 0xf0); /* XXX the linux driver */
384 384
385 bus_dmamap_sync(sc->dmat, sc->rx_map, 0, sc->rx_map->dm_mapsize, 385 bus_dmamap_sync(sc->dmat, sc->rx_map, 0, sc->rx_map->dm_mapsize,
386 BUS_DMASYNC_PREREAD); 386 BUS_DMASYNC_PREREAD);
387 387
388 sc->sc_recv1 = 0; 388 sc->sc_recv1 = 0;
389 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr); 389 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr);
390 AMCC_WRITE(sc, AMCC_RXLEN, 4); 390 AMCC_WRITE(sc, AMCC_RXLEN, 4);
391 sc->sc_csr |= EN_RX_TC_INT|EN_TX_TC_INT; 391 sc->sc_csr |= EN_RX_TC_INT|EN_TX_TC_INT;
392 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 392 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
393 393
394 splx(s); 394 splx(s);
395 } 395 }
396 396
397#ifdef notyet 397#ifdef notyet
398 /* good happy place */ 398 /* good happy place */
399 if(sc->sc_capi.card_type == CARD_TYPEC_AVM_B1_ISA) 399 if(sc->sc_capi.card_type == CARD_TYPEC_AVM_B1_ISA)
400 b1isa_setup_irq(sc); 400 b1isa_setup_irq(sc);
401#endif 401#endif
402 402
403 iavc_send_init(sc); 403 iavc_send_init(sc);
404 404
405 return 0; 405 return 0;
406} 406}
407 407
408int iavc_register(capi_softc_t *capi_sc, int applid, int nchan) 408int iavc_register(capi_softc_t *capi_sc, int applid, int nchan)
409{ 409{
410 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx; 410 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx;
411 struct mbuf *m = i4b_Dgetmbuf(23); 411 struct mbuf *m = i4b_Dgetmbuf(23);
412 u_int8_t *p; 412 u_int8_t *p;
413 413
414 if (!m) { 414 if (!m) {
415 aprint_error("iavc%d: can't get memory\n", sc->sc_unit); 415 aprint_error("iavc%d: can't get memory\n", sc->sc_unit);
416 return (ENOMEM); 416 return (ENOMEM);
417 } 417 }
418 418
419 /* 419 /*
420 * byte 0x12 = SEND_REGISTER 420 * byte 0x12 = SEND_REGISTER
421 * dword ApplId 421 * dword ApplId
422 * dword NumMessages 422 * dword NumMessages
423 * dword NumB3Connections 0..nbch 423 * dword NumB3Connections 0..nbch
424 * dword NumB3Blocks 424 * dword NumB3Blocks
425 * dword B3Size 425 * dword B3Size
426 */ 426 */
427 427
428 p = amcc_put_byte(mtod(m, u_int8_t*), 0); 428 p = amcc_put_byte(mtod(m, u_int8_t*), 0);
429 p = amcc_put_byte(p, 0); 429 p = amcc_put_byte(p, 0);
430 p = amcc_put_byte(p, SEND_REGISTER); 430 p = amcc_put_byte(p, SEND_REGISTER);
431 p = amcc_put_word(p, applid); 431 p = amcc_put_word(p, applid);
432#if 0 432#if 0
433 p = amcc_put_word(p, 1024 + (nchan + 1)); 433 p = amcc_put_word(p, 1024 + (nchan + 1));
434#else 434#else
435 p = amcc_put_word(p, 1024 * (nchan + 1)); 435 p = amcc_put_word(p, 1024 * (nchan + 1));
436#endif 436#endif
437 p = amcc_put_word(p, nchan); 437 p = amcc_put_word(p, nchan);
438 p = amcc_put_word(p, 8); 438 p = amcc_put_word(p, 8);
439 p = amcc_put_word(p, 2048); 439 p = amcc_put_word(p, 2048);
440 440
441 IF_ENQUEUE(&sc->sc_txq, m); 441 IF_ENQUEUE(&sc->sc_txq, m);
442 442
443 iavc_start_tx(sc); 443 iavc_start_tx(sc);
444 444
445 return 0; 445 return 0;
446} 446}
447 447
448int iavc_release(capi_softc_t *capi_sc, int applid) 448int iavc_release(capi_softc_t *capi_sc, int applid)
449{ 449{
450 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx; 450 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx;
451 struct mbuf *m = i4b_Dgetmbuf(7); 451 struct mbuf *m = i4b_Dgetmbuf(7);
452 u_int8_t *p; 452 u_int8_t *p;
453 453
454 if (!m) { 454 if (!m) {
455 aprint_error_dev(&sc->sc_dev, "can't get memory\n"); 455 aprint_error_dev(&sc->sc_dev, "can't get memory\n");
456 return (ENOMEM); 456 return (ENOMEM);
457 } 457 }
458 458
459 /* 459 /*
460 * byte 0x14 = SEND_RELEASE 460 * byte 0x14 = SEND_RELEASE
461 * dword ApplId 461 * dword ApplId
462 */ 462 */
463 463
464 p = amcc_put_byte(mtod(m, u_int8_t*), 0); 464 p = amcc_put_byte(mtod(m, u_int8_t*), 0);
465 p = amcc_put_byte(p, 0); 465 p = amcc_put_byte(p, 0);
466 p = amcc_put_byte(p, SEND_RELEASE); 466 p = amcc_put_byte(p, SEND_RELEASE);
467 p = amcc_put_word(p, applid); 467 p = amcc_put_word(p, applid);
468 468
469 IF_ENQUEUE(&sc->sc_txq, m); 469 IF_ENQUEUE(&sc->sc_txq, m);
470 470
471 iavc_start_tx(sc); 471 iavc_start_tx(sc);
472 return 0; 472 return 0;
473} 473}
474 474
475int iavc_send(capi_softc_t *capi_sc, struct mbuf *m) 475int iavc_send(capi_softc_t *capi_sc, struct mbuf *m)
476{ 476{
477 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx; 477 iavc_softc_t *sc = (iavc_softc_t*) capi_sc->ctx;
478 478
479 if (sc->sc_state != IAVC_UP) { 479 if (sc->sc_state != IAVC_UP) {
480 aprint_error_dev(&sc->sc_dev, "attempt to send before device up\n"); 480 aprint_error_dev(&sc->sc_dev, "attempt to send before device up\n");
481 481
482 if (m->m_next) i4b_Bfreembuf(m->m_next); 482 if (m->m_next) i4b_Bfreembuf(m->m_next);
483 i4b_Dfreembuf(m); 483 i4b_Dfreembuf(m);
484 484
485 return (ENXIO); 485 return (ENXIO);
486 } 486 }
487 487
488 if (IF_QFULL(&sc->sc_txq)) { 488 if (IF_QFULL(&sc->sc_txq)) {
489 IF_DROP(&sc->sc_txq); 489 IF_DROP(&sc->sc_txq);
490 490
491 aprint_error_dev(&sc->sc_dev, "tx overflow, message dropped\n"); 491 aprint_error_dev(&sc->sc_dev, "tx overflow, message dropped\n");
492 492
493 if (m->m_next) i4b_Bfreembuf(m->m_next); 493 if (m->m_next) i4b_Bfreembuf(m->m_next);
494 i4b_Dfreembuf(m); 494 i4b_Dfreembuf(m);
495 495
496 } else { 496 } else {
497 IF_ENQUEUE(&sc->sc_txq, m); 497 IF_ENQUEUE(&sc->sc_txq, m);
498 498
499 iavc_start_tx(sc); 499 iavc_start_tx(sc);
500 } 500 }
501 501
502 return 0; 502 return 0;
503} 503}
504 504
505/* 505/*
506// Functions called by ourself during the initialization sequence: 506// Functions called by ourself during the initialization sequence:
507// --------------------------------------------------------------- 507// ---------------------------------------------------------------
508// 508//
509// iavc_send_init 509// iavc_send_init
510// Sends the system initialization message to a newly loaded 510// Sends the system initialization message to a newly loaded
511// board, and sets state to INIT. 511// board, and sets state to INIT.
512*/ 512*/
513 513
514static int iavc_send_init(iavc_softc_t *sc) 514static int iavc_send_init(iavc_softc_t *sc)
515{ 515{
516 struct mbuf *m = i4b_Dgetmbuf(15); 516 struct mbuf *m = i4b_Dgetmbuf(15);
517 u_int8_t *p; 517 u_int8_t *p;
518 int s; 518 int s;
519 519
520 if (!m) { 520 if (!m) {
521 aprint_error_dev(&sc->sc_dev, "can't get memory\n"); 521 aprint_error_dev(&sc->sc_dev, "can't get memory\n");
522 return (ENOMEM); 522 return (ENOMEM);
523 } 523 }
524 524
525 /* 525 /*
526 * byte 0x11 = SEND_INIT 526 * byte 0x11 = SEND_INIT
527 * dword NumApplications 527 * dword NumApplications
528 * dword NumNCCIs 528 * dword NumNCCIs
529 * dword BoardNumber 529 * dword BoardNumber
530 */ 530 */
531 531
532 p = amcc_put_byte(mtod(m, u_int8_t*), 0); 532 p = amcc_put_byte(mtod(m, u_int8_t*), 0);
533 p = amcc_put_byte(p, 0); 533 p = amcc_put_byte(p, 0);
534 p = amcc_put_byte(p, SEND_INIT); 534 p = amcc_put_byte(p, SEND_INIT);
535 p = amcc_put_word(p, 1); /* XXX MaxAppl XXX */ 535 p = amcc_put_word(p, 1); /* XXX MaxAppl XXX */
536 p = amcc_put_word(p, sc->sc_capi.sc_nbch); 536 p = amcc_put_word(p, sc->sc_capi.sc_nbch);
537 p = amcc_put_word(p, sc->sc_unit); 537 p = amcc_put_word(p, sc->sc_unit);
538 538
539 s = splnet(); 539 s = splnet();
540 IF_ENQUEUE(&sc->sc_txq, m); 540 IF_ENQUEUE(&sc->sc_txq, m);
541 541
542 iavc_start_tx(sc); 542 iavc_start_tx(sc);
543 543
544 sc->sc_state = IAVC_INIT; 544 sc->sc_state = IAVC_INIT;
545 splx(s); 545 splx(s);
546 return 0; 546 return 0;
547} 547}
548 548
549/* 549/*
550// Functions called during normal operation: 550// Functions called during normal operation:
551// ----------------------------------------- 551// -----------------------------------------
552// 552//
553// iavc_receive_init 553// iavc_receive_init
554// Reads the initialization reply and calls capi_ll_control(). 554// Reads the initialization reply and calls capi_ll_control().
555// 555//
556// iavc_receive_new_ncci 556// iavc_receive_new_ncci
557// Reads a new NCCI notification and calls capi_ll_control(). 557// Reads a new NCCI notification and calls capi_ll_control().
558// 558//
559// iavc_receive_free_ncci 559// iavc_receive_free_ncci
560// Reads a freed NCCI notification and calls capi_ll_control(). 560// Reads a freed NCCI notification and calls capi_ll_control().
561// 561//
562// iavc_receive_task_ready 562// iavc_receive_task_ready
563// Reads a task ready message -- which should not occur XXX. 563// Reads a task ready message -- which should not occur XXX.
564// 564//
565// iavc_receive_debugmsg 565// iavc_receive_debugmsg
566// Reads a debug message -- which should not occur XXX. 566// Reads a debug message -- which should not occur XXX.
567// 567//
568// iavc_receive_start 568// iavc_receive_start
569// Reads a START TRANSMIT message and unblocks device. 569// Reads a START TRANSMIT message and unblocks device.
570// 570//
571// iavc_receive_stop 571// iavc_receive_stop
572// Reads a STOP TRANSMIT message and blocks device. 572// Reads a STOP TRANSMIT message and blocks device.
573// 573//
574// iavc_receive 574// iavc_receive
575// Reads an incoming message and calls capi_ll_receive(). 575// Reads an incoming message and calls capi_ll_receive().
576*/ 576*/
577 577
578static int iavc_receive_init(iavc_softc_t *sc, u_int8_t *dmabuf) 578static int iavc_receive_init(iavc_softc_t *sc, u_int8_t *dmabuf)
579{ 579{
580 u_int32_t Length; 580 u_int32_t Length;
581 u_int8_t *p; 581 u_int8_t *p;
582 u_int8_t *cardtype, *serial, *profile, *vers, *caps, *prot; 582 u_int8_t *cardtype, *serial, *profile, *vers, *caps, *prot;
583 583
584 if (sc->sc_dma) { 584 if (sc->sc_dma) {
585 p = amcc_get_word(dmabuf, &Length); 585 p = amcc_get_word(dmabuf, &Length);
586 } else { 586 } else {
587 Length = iavc_get_slice(sc, sc->sc_recvbuf); 587 Length = iavc_get_slice(sc, sc->sc_recvbuf);
588 p = sc->sc_recvbuf; 588 p = sc->sc_recvbuf;
589 } 589 }
590 590
591#if 0 591#if 0
592 { 592 {
593 int len = 0; 593 int len = 0;
594 printf("%s: rx_init: ", device_xname(&sc->sc_dev)); 594 printf("%s: rx_init: ", device_xname(&sc->sc_dev));
595 while (len < Length) { 595 while (len < Length) {
596 printf(" %02x", p[len]); 596 printf(" %02x", p[len]);
597 if (len && (len % 16) == 0) printf("\n"); 597 if (len && (len % 16) == 0) printf("\n");
598 len++; 598 len++;
599 } 599 }
600 if (len % 16) printf("\n"); 600 if (len % 16) printf("\n");
601 } 601 }
602#endif 602#endif
603 603
604 vers = (p + 1); 604 vers = (p + 1);
605 p += (*p + 1); /* driver version */ 605 p += (*p + 1); /* driver version */
606 cardtype = (p + 1); 606 cardtype = (p + 1);
607 p += (*p + 1); /* card type */ 607 p += (*p + 1); /* card type */
608 p += (*p + 1); /* hardware ID */ 608 p += (*p + 1); /* hardware ID */
609 serial = (p + 1); 609 serial = (p + 1);
610 p += (*p + 1); /* serial number */ 610 p += (*p + 1); /* serial number */
611 caps = (p + 1); 611 caps = (p + 1);
612 p += (*p + 1); /* supported options */ 612 p += (*p + 1); /* supported options */
613 prot = (p + 1); 613 prot = (p + 1);
614 p += (*p + 1); /* supported protocols */ 614 p += (*p + 1); /* supported protocols */
615 profile = (p + 1); 615 profile = (p + 1);
616 616
617 if (cardtype && serial && profile) { 617 if (cardtype && serial && profile) {
618 int nbch = ((profile[3]<<8) | profile[2]); 618 int nbch = ((profile[3]<<8) | profile[2]);
619 619
620 aprint_normal_dev(&sc->sc_dev, "AVM %s, s/n %s, %d chans, f/w rev %s, prot %s\n", 620 aprint_normal_dev(&sc->sc_dev, "AVM %s, s/n %s, %d chans, f/w rev %s, prot %s\n",
621 cardtype, serial, nbch, vers, prot); 621 cardtype, serial, nbch, vers, prot);
622 aprint_verbose_dev(&sc->sc_dev, "%s\n", caps); 622 aprint_verbose_dev(&sc->sc_dev, "%s\n", caps);
623 623
624 capi_ll_control(&sc->sc_capi, CAPI_CTRL_PROFILE, (int) profile); 624 capi_ll_control(&sc->sc_capi, CAPI_CTRL_PROFILE, (intptr_t) profile);
625 625
626 } else { 626 } else {
627 printf("%s: no profile data in info response?\n", device_xname(&sc->sc_dev)); 627 printf("%s: no profile data in info response?\n", device_xname(&sc->sc_dev));
628 } 628 }
629 629
630 sc->sc_blocked = 1; /* controller will send START when ready */ 630 sc->sc_blocked = 1; /* controller will send START when ready */
631 return 0; 631 return 0;
632} 632}
633 633
634static int iavc_receive_start(iavc_softc_t *sc) 634static int iavc_receive_start(iavc_softc_t *sc)
635{ 635{
636 struct mbuf *m = i4b_Dgetmbuf(3); 636 struct mbuf *m = i4b_Dgetmbuf(3);
637 u_int8_t *p; 637 u_int8_t *p;
638 638
639 if (sc->sc_blocked && sc->sc_state == IAVC_UP) 639 if (sc->sc_blocked && sc->sc_state == IAVC_UP)
640 printf("%s: receive_start\n", device_xname(&sc->sc_dev)); 640 printf("%s: receive_start\n", device_xname(&sc->sc_dev));
641 641
642 if (!m) { 642 if (!m) {
643 aprint_error_dev(&sc->sc_dev, "can't get memory\n"); 643 aprint_error_dev(&sc->sc_dev, "can't get memory\n");
644 return (ENOMEM); 644 return (ENOMEM);
645 } 645 }
646 646
647 /* 647 /*
648 * byte 0x73 = SEND_POLLACK 648 * byte 0x73 = SEND_POLLACK
649 */ 649 */
650 650
651 p = amcc_put_byte(mtod(m, u_int8_t*), 0); 651 p = amcc_put_byte(mtod(m, u_int8_t*), 0);
652 p = amcc_put_byte(p, 0); 652 p = amcc_put_byte(p, 0);
653 p = amcc_put_byte(p, SEND_POLLACK); 653 p = amcc_put_byte(p, SEND_POLLACK);
654 654
655 IF_PREPEND(&sc->sc_txq, m); 655 IF_PREPEND(&sc->sc_txq, m);
656 656
657 NDBGL4(L4_IAVCDBG, "%s: blocked = %d, state = %d", 657 NDBGL4(L4_IAVCDBG, "%s: blocked = %d, state = %d",
658 device_xname(&sc->sc_dev), sc->sc_blocked, sc->sc_state); 658 device_xname(&sc->sc_dev), sc->sc_blocked, sc->sc_state);
659 659
660 sc->sc_blocked = 0; 660 sc->sc_blocked = 0;
661 iavc_start_tx(sc); 661 iavc_start_tx(sc);
662 662
663 /* If this was our first START, register our readiness */ 663 /* If this was our first START, register our readiness */
664 if (sc->sc_state != IAVC_UP) { 664 if (sc->sc_state != IAVC_UP) {
665 sc->sc_state = IAVC_UP; 665 sc->sc_state = IAVC_UP;
666 capi_ll_control(&sc->sc_capi, CAPI_CTRL_READY, 1); 666 capi_ll_control(&sc->sc_capi, CAPI_CTRL_READY, 1);
667 } 667 }
668 668
669 return 0; 669 return 0;
670} 670}
671 671
672static int iavc_receive_stop(iavc_softc_t *sc) 672static int iavc_receive_stop(iavc_softc_t *sc)
673{ 673{
674 printf("%s: receive_stop\n", device_xname(&sc->sc_dev)); 674 printf("%s: receive_stop\n", device_xname(&sc->sc_dev));
675 sc->sc_blocked = 1; 675 sc->sc_blocked = 1;
676 return 0; 676 return 0;
677} 677}
678 678
679static int iavc_receive_new_ncci(iavc_softc_t *sc, u_int8_t *dmabuf) 679static int iavc_receive_new_ncci(iavc_softc_t *sc, u_int8_t *dmabuf)
680{ 680{
681 u_int32_t ApplId, NCCI, WindowSize; 681 u_int32_t ApplId, NCCI, WindowSize;
682 682
683 if (sc->sc_dma) { 683 if (sc->sc_dma) {
684 dmabuf = amcc_get_word(dmabuf, &ApplId); 684 dmabuf = amcc_get_word(dmabuf, &ApplId);
685 dmabuf = amcc_get_word(dmabuf, &NCCI); 685 dmabuf = amcc_get_word(dmabuf, &NCCI);
686 dmabuf = amcc_get_word(dmabuf, &WindowSize); 686 dmabuf = amcc_get_word(dmabuf, &WindowSize);
687 } else { 687 } else {
688 ApplId = iavc_get_word(sc); 688 ApplId = iavc_get_word(sc);
689 NCCI = iavc_get_word(sc); 689 NCCI = iavc_get_word(sc);
690 WindowSize = iavc_get_word(sc); 690 WindowSize = iavc_get_word(sc);
691 } 691 }
692 692
693 capi_ll_control(&sc->sc_capi, CAPI_CTRL_NEW_NCCI, NCCI); 693 capi_ll_control(&sc->sc_capi, CAPI_CTRL_NEW_NCCI, NCCI);
694 return 0; 694 return 0;
695} 695}
696 696
697static int iavc_receive_free_ncci(iavc_softc_t *sc, u_int8_t *dmabuf) 697static int iavc_receive_free_ncci(iavc_softc_t *sc, u_int8_t *dmabuf)
698{ 698{
699 u_int32_t ApplId, NCCI; 699 u_int32_t ApplId, NCCI;
700 700
701 if (sc->sc_dma) { 701 if (sc->sc_dma) {
702 dmabuf = amcc_get_word(dmabuf, &ApplId); 702 dmabuf = amcc_get_word(dmabuf, &ApplId);
703 dmabuf = amcc_get_word(dmabuf, &NCCI); 703 dmabuf = amcc_get_word(dmabuf, &NCCI);
704 } else { 704 } else {
705 ApplId = iavc_get_word(sc); 705 ApplId = iavc_get_word(sc);
706 NCCI = iavc_get_word(sc); 706 NCCI = iavc_get_word(sc);
707 } 707 }
708 708
709 capi_ll_control(&sc->sc_capi, CAPI_CTRL_FREE_NCCI, NCCI); 709 capi_ll_control(&sc->sc_capi, CAPI_CTRL_FREE_NCCI, NCCI);
710 return 0; 710 return 0;
711} 711}
712 712
713static int iavc_receive_task_ready(iavc_softc_t *sc, u_int8_t *dmabuf) 713static int iavc_receive_task_ready(iavc_softc_t *sc, u_int8_t *dmabuf)
714{ 714{
715 u_int32_t TaskId, Length; 715 u_int32_t TaskId, Length;
716 u_int8_t *p; 716 u_int8_t *p;
717 printf("%s: receive_task_ready\n", device_xname(&sc->sc_dev)); 717 printf("%s: receive_task_ready\n", device_xname(&sc->sc_dev));
718 718
719 if (sc->sc_dma) { 719 if (sc->sc_dma) {
720 p = amcc_get_word(dmabuf, &TaskId); 720 p = amcc_get_word(dmabuf, &TaskId);
721 p = amcc_get_word(p, &Length); 721 p = amcc_get_word(p, &Length);
722 } else { 722 } else {
723 TaskId = iavc_get_word(sc); 723 TaskId = iavc_get_word(sc);
724 Length = iavc_get_slice(sc, sc->sc_recvbuf); 724 Length = iavc_get_slice(sc, sc->sc_recvbuf);
725 p = sc->sc_recvbuf; 725 p = sc->sc_recvbuf;
726 } 726 }
727 727
728 /* XXX could show the message if trace enabled? XXX */ 728 /* XXX could show the message if trace enabled? XXX */
729 return 0; 729 return 0;
730} 730}
731 731
732static int iavc_receive_debugmsg(iavc_softc_t *sc, u_int8_t *dmabuf) 732static int iavc_receive_debugmsg(iavc_softc_t *sc, u_int8_t *dmabuf)
733{ 733{
734 u_int32_t Length; 734 u_int32_t Length;
735 u_int8_t *p; 735 u_int8_t *p;
736 printf("%s: receive_debugmsg\n", device_xname(&sc->sc_dev)); 736 printf("%s: receive_debugmsg\n", device_xname(&sc->sc_dev));
737 737
738 if (sc->sc_dma) { 738 if (sc->sc_dma) {
739 p = amcc_get_word(dmabuf, &Length); 739 p = amcc_get_word(dmabuf, &Length);
740 } else { 740 } else {
741 Length = iavc_get_slice(sc, sc->sc_recvbuf); 741 Length = iavc_get_slice(sc, sc->sc_recvbuf);
742 p = sc->sc_recvbuf; 742 p = sc->sc_recvbuf;
743 } 743 }
744 744
745 /* XXX could show the message if trace enabled? XXX */ 745 /* XXX could show the message if trace enabled? XXX */
746 return 0; 746 return 0;
747} 747}
748 748
749static int iavc_receive(iavc_softc_t *sc, u_int8_t *dmabuf, int b3data) 749static int iavc_receive(iavc_softc_t *sc, u_int8_t *dmabuf, int b3data)
750{ 750{
751 struct mbuf *m; 751 struct mbuf *m;
752 u_int32_t ApplId, Length; 752 u_int32_t ApplId, Length;
753 753
754 /* 754 /*
755 * byte 0x21 = RECEIVE_MESSAGE 755 * byte 0x21 = RECEIVE_MESSAGE
756 * dword ApplId 756 * dword ApplId
757 * dword length 757 * dword length
758 * ... CAPI msg 758 * ... CAPI msg
759 * 759 *
760 * --or-- 760 * --or--
761 * 761 *
762 * byte 0x22 = RECEIVE_DATA_B3_IND 762 * byte 0x22 = RECEIVE_DATA_B3_IND
763 * dword ApplId 763 * dword ApplId
764 * dword length 764 * dword length
765 * ... CAPI msg 765 * ... CAPI msg
766 * dword datalen 766 * dword datalen
767 * ... B3 data 767 * ... B3 data
768 */ 768 */
769 769
770 if (sc->sc_dma) { 770 if (sc->sc_dma) {
771 dmabuf = amcc_get_word(dmabuf, &ApplId); 771 dmabuf = amcc_get_word(dmabuf, &ApplId);
772 dmabuf = amcc_get_word(dmabuf, &Length); 772 dmabuf = amcc_get_word(dmabuf, &Length);
773 } else { 773 } else {
774 ApplId = iavc_get_word(sc); 774 ApplId = iavc_get_word(sc);
775 Length = iavc_get_slice(sc, sc->sc_recvbuf); 775 Length = iavc_get_slice(sc, sc->sc_recvbuf);
776 dmabuf = sc->sc_recvbuf; 776 dmabuf = sc->sc_recvbuf;
777 } 777 }
778 778
779 m = i4b_Dgetmbuf(Length); 779 m = i4b_Dgetmbuf(Length);
780 if (!m) { 780 if (!m) {
781 aprint_error_dev(&sc->sc_dev, "can't get memory for receive\n"); 781 aprint_error_dev(&sc->sc_dev, "can't get memory for receive\n");
782 return (ENOMEM); 782 return (ENOMEM);
783 } 783 }
784 784
785 memcpy(mtod(m, u_int8_t*), dmabuf, Length); 785 memcpy(mtod(m, u_int8_t*), dmabuf, Length);
786 786
787#if 0 787#if 0
788 { 788 {
789 u_int8_t *p = mtod(m, u_int8_t*); 789 u_int8_t *p = mtod(m, u_int8_t*);
790 int len = 0; 790 int len = 0;
791 printf("%s: applid=%d, len=%d\n", device_xname(&sc->sc_dev), 791 printf("%s: applid=%d, len=%d\n", device_xname(&sc->sc_dev),
792 ApplId, Length); 792 ApplId, Length);
793 while (len < m->m_len) { 793 while (len < m->m_len) {
794 printf(" %02x", p[len]); 794 printf(" %02x", p[len]);
795 if (len && (len % 16) == 0) printf("\n"); 795 if (len && (len % 16) == 0) printf("\n");
796 len++; 796 len++;
797 } 797 }
798 if (len % 16) printf("\n"); 798 if (len % 16) printf("\n");
799 } 799 }
800#endif 800#endif
801 801
802 if (b3data) { 802 if (b3data) {
803 if (sc->sc_dma) { 803 if (sc->sc_dma) {
804 dmabuf = amcc_get_word(dmabuf + Length, &Length); 804 dmabuf = amcc_get_word(dmabuf + Length, &Length);
805 } else { 805 } else {
806 Length = iavc_get_slice(sc, sc->sc_recvbuf); 806 Length = iavc_get_slice(sc, sc->sc_recvbuf);
807 dmabuf = sc->sc_recvbuf; 807 dmabuf = sc->sc_recvbuf;
808 } 808 }
809 809
810 m->m_next = i4b_Bgetmbuf(Length); 810 m->m_next = i4b_Bgetmbuf(Length);
811 if (!m->m_next) { 811 if (!m->m_next) {
812 aprint_error_dev(&sc->sc_dev, "can't get memory for receive\n"); 812 aprint_error_dev(&sc->sc_dev, "can't get memory for receive\n");
813 i4b_Dfreembuf(m); 813 i4b_Dfreembuf(m);
814 return (ENOMEM); 814 return (ENOMEM);
815 } 815 }
816 816
817 memcpy(mtod(m->m_next, u_int8_t*), dmabuf, Length); 817 memcpy(mtod(m->m_next, u_int8_t*), dmabuf, Length);
818 } 818 }
819 819
820 capi_ll_receive(&sc->sc_capi, m); 820 capi_ll_receive(&sc->sc_capi, m);
821 return 0; 821 return 0;
822} 822}
823 823
824/* 824/*
825// iavc_handle_intr 825// iavc_handle_intr
826// Checks device interrupt status and calls iavc_handle_{rx,tx}() 826// Checks device interrupt status and calls iavc_handle_{rx,tx}()
827// as necessary. 827// as necessary.
828// 828//
829// iavc_handle_rx 829// iavc_handle_rx
830// Reads in the command byte and calls the subroutines above. 830// Reads in the command byte and calls the subroutines above.
831// 831//
832// iavc_start_tx 832// iavc_start_tx
833// Initiates DMA on the next queued message if possible. 833// Initiates DMA on the next queued message if possible.
834*/ 834*/
835 835
836int iavc_handle_intr(iavc_softc_t *sc) 836int iavc_handle_intr(iavc_softc_t *sc)
837{ 837{
838 u_int32_t status; 838 u_int32_t status;
839 u_int32_t newcsr; 839 u_int32_t newcsr;
840 840
841 if (!sc->sc_dma) { 841 if (!sc->sc_dma) {
842 while (iavc_rx_full(sc)) 842 while (iavc_rx_full(sc))
843 iavc_handle_rx(sc); 843 iavc_handle_rx(sc);
844 return 0; 844 return 0;
845 } 845 }
846 846
847 status = AMCC_READ(sc, AMCC_INTCSR); 847 status = AMCC_READ(sc, AMCC_INTCSR);
848 if ((status & ANY_S5933_INT) == 0) 848 if ((status & ANY_S5933_INT) == 0)
849 return 0; 849 return 0;
850 850
851 newcsr = sc->sc_csr | (status & ALL_INT); 851 newcsr = sc->sc_csr | (status & ALL_INT);
852 if (status & TX_TC_INT) newcsr &= ~EN_TX_TC_INT; 852 if (status & TX_TC_INT) newcsr &= ~EN_TX_TC_INT;
853 if (status & RX_TC_INT) newcsr &= ~EN_RX_TC_INT; 853 if (status & RX_TC_INT) newcsr &= ~EN_RX_TC_INT;
854 AMCC_WRITE(sc, AMCC_INTCSR, newcsr); 854 AMCC_WRITE(sc, AMCC_INTCSR, newcsr);
855 sc->sc_intr = 1; 855 sc->sc_intr = 1;
856 856
857 if (status & RX_TC_INT) { 857 if (status & RX_TC_INT) {
858 u_int32_t rxlen; 858 u_int32_t rxlen;
859 859
860 bus_dmamap_sync(sc->dmat, sc->rx_map, 0, sc->rx_map->dm_mapsize, 860 bus_dmamap_sync(sc->dmat, sc->rx_map, 0, sc->rx_map->dm_mapsize,
861 BUS_DMASYNC_POSTREAD); 861 BUS_DMASYNC_POSTREAD);
862 862
863 if (sc->sc_recv1 == 0) { 863 if (sc->sc_recv1 == 0) {
864 sc->sc_recv1 = *(u_int32_t*)(sc->sc_recvbuf); 864 sc->sc_recv1 = *(u_int32_t*)(sc->sc_recvbuf);
865 rxlen = (sc->sc_recv1 + 3) & ~3; 865 rxlen = (sc->sc_recv1 + 3) & ~3;
866 866
867 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr); 867 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr);
868 AMCC_WRITE(sc, AMCC_RXLEN, rxlen ? rxlen : 4); 868 AMCC_WRITE(sc, AMCC_RXLEN, rxlen ? rxlen : 4);
869 } else { 869 } else {
870 iavc_handle_rx(sc); 870 iavc_handle_rx(sc);
871 sc->sc_recv1 = 0; 871 sc->sc_recv1 = 0;
872 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr); 872 AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr);
873 AMCC_WRITE(sc, AMCC_RXLEN, 4); 873 AMCC_WRITE(sc, AMCC_RXLEN, 4);
874 } 874 }
875 } 875 }
876 876
877 if (status & TX_TC_INT) { 877 if (status & TX_TC_INT) {
878 bus_dmamap_sync(sc->dmat, sc->tx_map, 0, sc->tx_map->dm_mapsize, 878 bus_dmamap_sync(sc->dmat, sc->tx_map, 0, sc->tx_map->dm_mapsize,
879 BUS_DMASYNC_POSTWRITE); 879 BUS_DMASYNC_POSTWRITE);
880 sc->sc_csr &= ~EN_TX_TC_INT; 880 sc->sc_csr &= ~EN_TX_TC_INT;
881 iavc_start_tx(sc); 881 iavc_start_tx(sc);
882 } 882 }
883 883
884 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 884 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
885 sc->sc_intr = 0; 885 sc->sc_intr = 0;
886 886
887 return 0; 887 return 0;
888} 888}
889 889
890static void iavc_handle_rx(iavc_softc_t *sc) 890static void iavc_handle_rx(iavc_softc_t *sc)
891{ 891{
892 u_int8_t *dmabuf = 0, cmd; 892 u_int8_t *dmabuf = 0, cmd;
893 893
894 if (sc->sc_dma) { 894 if (sc->sc_dma) {
895 dmabuf = amcc_get_byte(sc->sc_recvbuf, &cmd); 895 dmabuf = amcc_get_byte(sc->sc_recvbuf, &cmd);
896 } else { 896 } else {
897 cmd = iavc_get_byte(sc); 897 cmd = iavc_get_byte(sc);
898 } 898 }
899 899
900 NDBGL4(L4_IAVCDBG, "iavc%d: command = 0x%02x", sc->sc_unit, cmd); 900 NDBGL4(L4_IAVCDBG, "iavc%d: command = 0x%02x", sc->sc_unit, cmd);
901 901
902 switch (cmd) { 902 switch (cmd) {
903 case RECEIVE_DATA_B3_IND: 903 case RECEIVE_DATA_B3_IND:
904 iavc_receive(sc, dmabuf, 1); 904 iavc_receive(sc, dmabuf, 1);
905 break; 905 break;
906 906
907 case RECEIVE_MESSAGE: 907 case RECEIVE_MESSAGE:
908 iavc_receive(sc, dmabuf, 0); 908 iavc_receive(sc, dmabuf, 0);
909 break; 909 break;
910 910
911 case RECEIVE_NEW_NCCI: 911 case RECEIVE_NEW_NCCI:
912 iavc_receive_new_ncci(sc, dmabuf); 912 iavc_receive_new_ncci(sc, dmabuf);
913 break; 913 break;
914 914
915 case RECEIVE_FREE_NCCI: 915 case RECEIVE_FREE_NCCI:
916 iavc_receive_free_ncci(sc, dmabuf); 916 iavc_receive_free_ncci(sc, dmabuf);
917 break; 917 break;
918 918
919 case RECEIVE_START: 919 case RECEIVE_START:
920 iavc_receive_start(sc); 920 iavc_receive_start(sc);
921 break; 921 break;
922 922
923 case RECEIVE_STOP: 923 case RECEIVE_STOP:
924 iavc_receive_stop(sc); 924 iavc_receive_stop(sc);
925 break; 925 break;
926 926
927 case RECEIVE_INIT: 927 case RECEIVE_INIT:
928 iavc_receive_init(sc, dmabuf); 928 iavc_receive_init(sc, dmabuf);
929 break; 929 break;
930 930
931 case RECEIVE_TASK_READY: 931 case RECEIVE_TASK_READY:
932 iavc_receive_task_ready(sc, dmabuf); 932 iavc_receive_task_ready(sc, dmabuf);
933 break; 933 break;
934 934
935 case RECEIVE_DEBUGMSG: 935 case RECEIVE_DEBUGMSG:
936 iavc_receive_debugmsg(sc, dmabuf); 936 iavc_receive_debugmsg(sc, dmabuf);
937 break; 937 break;
938 938
939 default: 939 default:
940 aprint_error_dev(&sc->sc_dev, "unknown msg %02x\n", cmd); 940 aprint_error_dev(&sc->sc_dev, "unknown msg %02x\n", cmd);
941 } 941 }
942} 942}
943 943
944static void iavc_start_tx(iavc_softc_t *sc) 944static void iavc_start_tx(iavc_softc_t *sc)
945{ 945{
946 struct mbuf *m; 946 struct mbuf *m;
947 u_int32_t txlen; 947 u_int32_t txlen;
948 948
949 /* If device has put us on hold, punt. */ 949 /* If device has put us on hold, punt. */
950 950
951 if (sc->sc_blocked) { 951 if (sc->sc_blocked) {
952 return; 952 return;
953 } 953 }
954 954
955 /* If using DMA and transmitter busy, punt. */ 955 /* If using DMA and transmitter busy, punt. */
956 if (sc->sc_dma && (sc->sc_csr & EN_TX_TC_INT)) { 956 if (sc->sc_dma && (sc->sc_csr & EN_TX_TC_INT)) {
957 return; 957 return;
958 } 958 }
959 959
960 /* Else, see if we have messages to send. */ 960 /* Else, see if we have messages to send. */
961 IF_DEQUEUE(&sc->sc_txq, m); 961 IF_DEQUEUE(&sc->sc_txq, m);
962 if (!m) { 962 if (!m) {
963 return; 963 return;
964 } 964 }
965 965
966 /* Have message, will send. */ 966 /* Have message, will send. */
967 if (CAPIMSG_LEN(m->m_data)) { 967 if (CAPIMSG_LEN(m->m_data)) {
968 /* A proper CAPI message, possibly with B3 data */ 968 /* A proper CAPI message, possibly with B3 data */
969 txlen = iavc_tx_capimsg(sc, m); 969 txlen = iavc_tx_capimsg(sc, m);
970 } else { 970 } else {
971 /* A board control message to be sent as is */ 971 /* A board control message to be sent as is */
972 txlen = iavc_tx_ctrlmsg(sc, m); 972 txlen = iavc_tx_ctrlmsg(sc, m);
973 } 973 }
974 974
975 if (m->m_next) { 975 if (m->m_next) {
976 i4b_Bfreembuf(m->m_next); 976 i4b_Bfreembuf(m->m_next);
977 m->m_next = NULL; 977 m->m_next = NULL;
978 } 978 }
979 i4b_Dfreembuf(m); 979 i4b_Dfreembuf(m);
980 980
981 /* Kick DMA into motion if applicable */ 981 /* Kick DMA into motion if applicable */
982 if (sc->sc_dma) { 982 if (sc->sc_dma) {
983 txlen = (txlen + 3) & ~3; 983 txlen = (txlen + 3) & ~3;
984 984
985 bus_dmamap_sync(sc->dmat, sc->tx_map, 0, txlen, 985 bus_dmamap_sync(sc->dmat, sc->tx_map, 0, txlen,
986 BUS_DMASYNC_PREWRITE); 986 BUS_DMASYNC_PREWRITE);
987 987
988 AMCC_WRITE(sc, AMCC_TXPTR, sc->tx_map->dm_segs[0].ds_addr); 988 AMCC_WRITE(sc, AMCC_TXPTR, sc->tx_map->dm_segs[0].ds_addr);
989 AMCC_WRITE(sc, AMCC_TXLEN, txlen); 989 AMCC_WRITE(sc, AMCC_TXLEN, txlen);
990 sc->sc_csr |= EN_TX_TC_INT; 990 sc->sc_csr |= EN_TX_TC_INT;
991 991
992 if (!sc->sc_intr) 992 if (!sc->sc_intr)
993 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr); 993 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
994 } 994 }
995} 995}
996 996
997static uint32_t 997static uint32_t
998iavc_tx_capimsg(iavc_softc_t *sc, struct mbuf *m) 998iavc_tx_capimsg(iavc_softc_t *sc, struct mbuf *m)
999{ 999{
1000 uint32_t txlen = 0; 1000 uint32_t txlen = 0;
1001 u_int8_t *dmabuf; 1001 u_int8_t *dmabuf;
1002 1002
1003 if (sc->sc_dma) { 1003 if (sc->sc_dma) {
1004 /* Copy message to DMA buffer. */ 1004 /* Copy message to DMA buffer. */
1005 1005
1006 if (m->m_next) 1006 if (m->m_next)
1007 dmabuf = amcc_put_byte(sc->sc_sendbuf, SEND_DATA_B3_REQ); 1007 dmabuf = amcc_put_byte(sc->sc_sendbuf, SEND_DATA_B3_REQ);
1008 else 1008 else
1009 dmabuf = amcc_put_byte(sc->sc_sendbuf, SEND_MESSAGE); 1009 dmabuf = amcc_put_byte(sc->sc_sendbuf, SEND_MESSAGE);
1010 1010
1011 dmabuf = amcc_put_word(dmabuf, m->m_len); 1011 dmabuf = amcc_put_word(dmabuf, m->m_len);
1012 memcpy(dmabuf, m->m_data, m->m_len); 1012 memcpy(dmabuf, m->m_data, m->m_len);
1013 dmabuf += m->m_len; 1013 dmabuf += m->m_len;
1014 txlen = 5 + m->m_len; 1014 txlen = 5 + m->m_len;
1015 1015
1016 if (m->m_next) { 1016 if (m->m_next) {
1017 dmabuf = amcc_put_word(dmabuf, m->m_next->m_len); 1017 dmabuf = amcc_put_word(dmabuf, m->m_next->m_len);
1018 memcpy(dmabuf, m->m_next->m_data, m->m_next->m_len); 1018 memcpy(dmabuf, m->m_next->m_data, m->m_next->m_len);
1019 txlen += 4 + m->m_next->m_len; 1019 txlen += 4 + m->m_next->m_len;
1020 } 1020 }
1021 1021
1022 } else { 1022 } else {
1023 /* Use PIO. */ 1023 /* Use PIO. */
1024 1024
1025 if (m->m_next) { 1025 if (m->m_next) {
1026 iavc_put_byte(sc, SEND_DATA_B3_REQ); 1026 iavc_put_byte(sc, SEND_DATA_B3_REQ);
1027 NDBGL4(L4_IAVCDBG, "iavc%d: tx SDB3R msg, len = %d", 1027 NDBGL4(L4_IAVCDBG, "iavc%d: tx SDB3R msg, len = %d",
1028 sc->sc_unit, m->m_len); 1028 sc->sc_unit, m->m_len);
1029 } else { 1029 } else {
1030 iavc_put_byte(sc, SEND_MESSAGE); 1030 iavc_put_byte(sc, SEND_MESSAGE);
1031 NDBGL4(L4_IAVCDBG, "iavc%d: tx SM msg, len = %d", 1031 NDBGL4(L4_IAVCDBG, "iavc%d: tx SM msg, len = %d",
1032 sc->sc_unit, m->m_len); 1032 sc->sc_unit, m->m_len);
1033 } 1033 }
1034#if 0 1034#if 0
1035 { 1035 {
1036 u_int8_t *p = mtod(m, u_int8_t*); 1036 u_int8_t *p = mtod(m, u_int8_t*);
1037 int len; 1037 int len;
1038 for (len = 0; len < m->m_len; len++) { 1038 for (len = 0; len < m->m_len; len++) {
1039 printf(" %02x", *p++); 1039 printf(" %02x", *p++);
1040 if (len && (len % 16) == 0) 1040 if (len && (len % 16) == 0)
1041 printf("\n"); 1041 printf("\n");
1042 } 1042 }
1043 if (len % 16) 1043 if (len % 16)
1044 printf("\n"); 1044 printf("\n");
1045 } 1045 }
1046#endif 1046#endif
1047 1047
1048 iavc_put_slice(sc, m->m_data, m->m_len); 1048 iavc_put_slice(sc, m->m_data, m->m_len);
1049 1049
1050 if (m->m_next) 1050 if (m->m_next)
1051 iavc_put_slice(sc, m->m_next->m_data, m->m_next->m_len); 1051 iavc_put_slice(sc, m->m_next->m_data, m->m_next->m_len);
1052 } 1052 }
1053 1053
1054 return txlen; 1054 return txlen;
1055} 1055}
1056 1056
1057static uint32_t 1057static uint32_t
1058iavc_tx_ctrlmsg(iavc_softc_t *sc, struct mbuf *m) 1058iavc_tx_ctrlmsg(iavc_softc_t *sc, struct mbuf *m)
1059{ 1059{
1060 uint32_t txlen = 0; 1060 uint32_t txlen = 0;
1061 uint8_t *dmabuf; 1061 uint8_t *dmabuf;
1062 1062
1063 if (sc->sc_dma) { 1063 if (sc->sc_dma) {
1064 memcpy(sc->sc_sendbuf, m->m_data + 2, m->m_len - 2); 1064 memcpy(sc->sc_sendbuf, m->m_data + 2, m->m_len - 2);
1065 txlen = m->m_len - 2; 1065 txlen = m->m_len - 2;
1066 } else { 1066 } else {
1067 1067
1068#if 0 1068#if 0
1069 { 1069 {
1070 u_int8_t *p = mtod(m, u_int8_t*) + 2; 1070 u_int8_t *p = mtod(m, u_int8_t*) + 2;
1071 int len; 1071 int len;
1072 1072
1073 printf("%s: tx BDC msg, len = %d, msg =", device_xname(&sc->sc_dev), 1073 printf("%s: tx BDC msg, len = %d, msg =", device_xname(&sc->sc_dev),
1074 m->m_len-2); 1074 m->m_len-2);
1075 for (len = 0; len < m->m_len-2; len++) { 1075 for (len = 0; len < m->m_len-2; len++) {
1076 printf(" %02x", *p++); 1076 printf(" %02x", *p++);
1077 if (len && (len % 16) == 0) printf("\n"); 1077 if (len && (len % 16) == 0) printf("\n");
1078 } 1078 }
1079 if (len % 16) 1079 if (len % 16)
1080 printf("\n"); 1080 printf("\n");
1081 } 1081 }
1082#endif 1082#endif
1083 1083
1084 /* no DMA */ 1084 /* no DMA */
1085 txlen = m->m_len - 2; 1085 txlen = m->m_len - 2;
1086 dmabuf = mtod(m, char*) + 2; 1086 dmabuf = mtod(m, char*) + 2;
1087 while(txlen--) 1087 while(txlen--)
1088 b1io_put_byte(sc, *dmabuf++); 1088 b1io_put_byte(sc, *dmabuf++);
1089 } 1089 }
1090 1090
1091 return txlen; 1091 return txlen;
1092} 1092}
cvs diff -r1.5 -r1.5.94.1 src/sys/netisdn/Attic/i4b_capi.h (switch to unified diff)

--- src/sys/netisdn/Attic/i4b_capi.h 2006/10/16 13:03:03 1.5
+++ src/sys/netisdn/Attic/i4b_capi.h 2013/06/13 07:22:44 1.5.94.1
@@ -1,134 +1,134 @@ @@ -1,134 +1,134 @@
1/* $NetBSD: i4b_capi.h,v 1.5 2006/10/16 13:03:03 pooka Exp $ */ 1/* $NetBSD: i4b_capi.h,v 1.5.94.1 2013/06/13 07:22:44 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved. 4 * Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE. 25 * SUCH DAMAGE.
26 * 26 *
27 * capi/capi.h The CAPI device interface. 27 * capi/capi.h The CAPI device interface.
28 * 28 *
29 * $FreeBSD: src/sys/i4b/capi/capi.h,v 1.1 2001/05/25 08:39:31 hm Exp $ 29 * $FreeBSD: src/sys/i4b/capi/capi.h,v 1.1 2001/05/25 08:39:31 hm Exp $
30 */ 30 */
31 31
32#ifndef _NETISDN_I4B_CAPI_H_ 32#ifndef _NETISDN_I4B_CAPI_H_
33#define _NETISDN_I4B_CAPI_H_ 33#define _NETISDN_I4B_CAPI_H_
34 34
35/* 35/*
36// CAPI driver context: B channels and controller softcs. 36// CAPI driver context: B channels and controller softcs.
37*/ 37*/
38 38
39#define INVALID -1 39#define INVALID -1
40 40
41enum capi_b_state { 41enum capi_b_state {
42 B_FREE, /* 0: channel free, ncci invalid */ 42 B_FREE, /* 0: channel free, ncci invalid */
43 B_CONNECT_CONF, /* 1: wait for CONNECT_CONF */ 43 B_CONNECT_CONF, /* 1: wait for CONNECT_CONF */
44 B_CONNECT_IND, /* 2: IND got, wait for appl RESP */ 44 B_CONNECT_IND, /* 2: IND got, wait for appl RESP */
45 B_CONNECT_ACTIVE_IND, /* 3: wait for CONNECT_ACTIVE_IND */ 45 B_CONNECT_ACTIVE_IND, /* 3: wait for CONNECT_ACTIVE_IND */
46 B_CONNECT_B3_CONF, /* 4: wait for CONNECT_B3_CONF */ 46 B_CONNECT_B3_CONF, /* 4: wait for CONNECT_B3_CONF */
47 B_CONNECT_B3_IND, /* 5: wait for CONNECT_B3_IND */ 47 B_CONNECT_B3_IND, /* 5: wait for CONNECT_B3_IND */
48 B_CONNECT_B3_ACTIVE_IND, /* 6: wait for CONNECT_B3_ACTIVE_IND */ 48 B_CONNECT_B3_ACTIVE_IND, /* 6: wait for CONNECT_B3_ACTIVE_IND */
49 B_CONNECTED, /* 7: channel connected & in use */ 49 B_CONNECTED, /* 7: channel connected & in use */
50 B_DISCONNECT_CONF, /* 8: wait for DISCONNECT_CONF */ 50 B_DISCONNECT_CONF, /* 8: wait for DISCONNECT_CONF */
51 B_DISCONNECT_B3_CONF, /* 9: wait for DISCONNECT_B3_CONF */ 51 B_DISCONNECT_B3_CONF, /* 9: wait for DISCONNECT_B3_CONF */
52 B_DISCONNECT_IND, /* 10: wait for DISCONNECT_IND */ 52 B_DISCONNECT_IND, /* 10: wait for DISCONNECT_IND */
53}; 53};
54 54
55typedef struct capi_bchan 55typedef struct capi_bchan
56{ 56{
57 /* Channel state */ 57 /* Channel state */
58 58
59 int ncci; 59 int ncci;
60#define CAPI_CTRL_MASK 0x000000ff 60#define CAPI_CTRL_MASK 0x000000ff
61#define CAPI_PLCI_MASK 0x0000ffff 61#define CAPI_PLCI_MASK 0x0000ffff
62#define CAPI_NCCI_MASK 0xffff0000 62#define CAPI_NCCI_MASK 0xffff0000
63 u_int16_t msgid; 63 u_int16_t msgid;
64 int busy; 64 int busy;
65 enum capi_b_state state; 65 enum capi_b_state state;
66 66
67 struct ifqueue tx_queue; 67 struct ifqueue tx_queue;
68 struct ifqueue rx_queue; 68 struct ifqueue rx_queue;
69 int rxcount; 69 int rxcount;
70 int txcount; 70 int txcount;
71 71
72 /* The rest is needed for i4b integration */ 72 /* The rest is needed for i4b integration */
73 int bprot; 73 int bprot;
74 int cdid; 74 int cdid;
75 75
76 struct mbuf *in_mbuf; 76 struct mbuf *in_mbuf;
77 isdn_link_t capi_isdn_linktab; 77 isdn_link_t capi_isdn_linktab;
78 78
79 const struct isdn_l4_driver_functions *l4_driver; 79 const struct isdn_l4_driver_functions *l4_driver;
80 void *l4_driver_softc; 80 void *l4_driver_softc;
81} capi_bchan_t; 81} capi_bchan_t;
82 82
83enum capi_c_state { 83enum capi_c_state {
84 C_DOWN, /* controller uninitialized */ 84 C_DOWN, /* controller uninitialized */
85 C_READY, /* controller initialized but not listening */ 85 C_READY, /* controller initialized but not listening */
86 C_UP, /* controller listening */ 86 C_UP, /* controller listening */
87}; 87};
88 88
89typedef struct capi_softc { 89typedef struct capi_softc {
90 int sc_unit; /* index in capi_sc[] */ 90 int sc_unit; /* index in capi_sc[] */
91 int card_type; /* CARD_TYPEC_xxx, filled by ll driver */ 91 int card_type; /* CARD_TYPEC_xxx, filled by ll driver */
92 int sc_nbch; /* number of b channels on this controller */ 92 int sc_nbch; /* number of b channels on this controller */
93 int sc_enabled; /* is daemon connected TRUE/FALSE */ 93 int sc_enabled; /* is daemon connected TRUE/FALSE */
94 int sc_msgid; /* next CAPI message id */ 94 int sc_msgid; /* next CAPI message id */
95 int capi_isdnif; /* isdnif identifier */ 95 int capi_isdnif; /* isdnif identifier */
96 char sc_profile[64];/* CAPI profile data */ 96 char sc_profile[64];/* CAPI profile data */
97 enum capi_c_state sc_state; 97 enum capi_c_state sc_state;
98 98
99 capi_bchan_t sc_bchan[MAX_BCHAN]; 99 capi_bchan_t sc_bchan[MAX_BCHAN];
100 100
101 /* Link layer driver context holder and methods */ 101 /* Link layer driver context holder and methods */
102 void *ctx; 102 void *ctx;
103 103
104 int (*load)(struct capi_softc *, int, u_int8_t *); 104 int (*load)(struct capi_softc *, int, u_int8_t *);
105 int (*reg_appl)(struct capi_softc *, int, int); 105 int (*reg_appl)(struct capi_softc *, int, int);
106 int (*rel_appl)(struct capi_softc *, int); 106 int (*rel_appl)(struct capi_softc *, int);
107 int (*send)(struct capi_softc *, struct mbuf *); 107 int (*send)(struct capi_softc *, struct mbuf *);
108} capi_softc_t; 108} capi_softc_t;
109 109
110#define CARD_TYPEC_CAPI_UNK 0 110#define CARD_TYPEC_CAPI_UNK 0
111#define CARD_TYPEC_AVM_T1_PCI 1 111#define CARD_TYPEC_AVM_T1_PCI 1
112#define CARD_TYPEC_AVM_B1_PCI 2 112#define CARD_TYPEC_AVM_B1_PCI 2
113#define CARD_TYPEC_AVM_B1_ISA 3 113#define CARD_TYPEC_AVM_B1_ISA 3
114 114
115/* 115/*
116// CAPI upcalls for the link layer. 116// CAPI upcalls for the link layer.
117*/ 117*/
118 118
119#define I4BCAPI_APPLID 1 119#define I4BCAPI_APPLID 1
120 120
121extern int capi_ll_attach(capi_softc_t *, const char *, const char *); 121extern int capi_ll_attach(capi_softc_t *, const char *, const char *);
122extern int capi_ll_control(capi_softc_t *, int op, int arg); 122extern int capi_ll_control(capi_softc_t *, int op, intptr_t arg);
123extern int capi_ll_detach(capi_softc_t *); 123extern int capi_ll_detach(capi_softc_t *);
124 124
125#define CAPI_CTRL_READY 0 /* ctrl ready, value=TRUE/FALSE */ 125#define CAPI_CTRL_READY 0 /* ctrl ready, value=TRUE/FALSE */
126#define CAPI_CTRL_PROFILE 1 /* set CAPI profile */ 126#define CAPI_CTRL_PROFILE 1 /* set CAPI profile */
127#define CAPI_CTRL_NEW_NCCI 2 /* new ncci value, assign bchan */ 127#define CAPI_CTRL_NEW_NCCI 2 /* new ncci value, assign bchan */
128#define CAPI_CTRL_FREE_NCCI 3 /* free ncci value, clear bchan */ 128#define CAPI_CTRL_FREE_NCCI 3 /* free ncci value, clear bchan */
129 129
130extern int capi_ll_receive(capi_softc_t *, struct mbuf *); 130extern int capi_ll_receive(capi_softc_t *, struct mbuf *);
131 131
132extern int capi_start_tx(void *, int bchan); 132extern int capi_start_tx(void *, int bchan);
133 133
134#endif /* !_NETISDN_I4B_CAPI_H_ */ 134#endif /* !_NETISDN_I4B_CAPI_H_ */
cvs diff -r1.5 -r1.5.18.1 src/sys/netisdn/Attic/i4b_capi_llif.c (switch to unified diff)

--- src/sys/netisdn/Attic/i4b_capi_llif.c 2009/04/18 14:58:06 1.5
+++ src/sys/netisdn/Attic/i4b_capi_llif.c 2013/06/13 07:22:44 1.5.18.1
@@ -1,164 +1,164 @@ @@ -1,164 +1,164 @@
1/* $NetBSD: i4b_capi_llif.c,v 1.5 2009/04/18 14:58:06 tsutsui Exp $ */ 1/* $NetBSD: i4b_capi_llif.c,v 1.5.18.1 2013/06/13 07:22:44 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved. 4 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE. 25 * SUCH DAMAGE.
26 * 26 *
27 * capi/capi_llif.c The i4b CAPI link layer interface. 27 * capi/capi_llif.c The i4b CAPI link layer interface.
28 * 28 *
29 * $FreeBSD: src/sys/i4b/capi/capi_llif.c,v 1.1 2001/05/25 08:39:31 hm Exp $ 29 * $FreeBSD: src/sys/i4b/capi/capi_llif.c,v 1.1 2001/05/25 08:39:31 hm Exp $
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: i4b_capi_llif.c,v 1.5 2009/04/18 14:58:06 tsutsui Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: i4b_capi_llif.c,v 1.5.18.1 2013/06/13 07:22:44 msaitoh Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/kernel.h> 36#include <sys/kernel.h>
37#include <sys/systm.h> 37#include <sys/systm.h>
38#include <sys/mbuf.h> 38#include <sys/mbuf.h>
39#include <sys/socket.h> 39#include <sys/socket.h>
40#include <sys/callout.h> 40#include <sys/callout.h>
41#include <net/if.h> 41#include <net/if.h>
42 42
43#include <netisdn/i4b_debug.h> 43#include <netisdn/i4b_debug.h>
44#include <netisdn/i4b_ioctl.h> 44#include <netisdn/i4b_ioctl.h>
45#include <netisdn/i4b_cause.h> 45#include <netisdn/i4b_cause.h>
46#include <netisdn/i4b_l3l4.h> 46#include <netisdn/i4b_l3l4.h>
47#include <netisdn/i4b_mbuf.h> 47#include <netisdn/i4b_mbuf.h>
48#include <netisdn/i4b_global.h> 48#include <netisdn/i4b_global.h>
49#include <netisdn/i4b_l4.h> 49#include <netisdn/i4b_l4.h>
50#include <netisdn/i4b_capi.h> 50#include <netisdn/i4b_capi.h>
51#include <netisdn/i4b_capi_msgs.h> 51#include <netisdn/i4b_capi_msgs.h>
52 52
53/* 53/*
54// capi_ll_control 54// capi_ll_control
55// CAPI link layer control routine. Called by a link layer 55// CAPI link layer control routine. Called by a link layer
56// driver when its state changes. 56// driver when its state changes.
57*/ 57*/
58 58
59int 59int
60capi_ll_control(capi_softc_t *sc, int op, int arg) 60capi_ll_control(capi_softc_t *sc, int op, intptr_t arg)
61{ 61{
62 switch (op) { 62 switch (op) {
63 case CAPI_CTRL_READY: 63 case CAPI_CTRL_READY:
64 if (arg) { 64 if (arg) {
65 sc->sc_state = C_READY; 65 sc->sc_state = C_READY;
66 66
67 /* 67 /*
68 * Register our CAPI ApplId and send CAPI_LISTEN_REQ 68 * Register our CAPI ApplId and send CAPI_LISTEN_REQ
69 * with CIP Mask value 1 (match all). 69 * with CIP Mask value 1 (match all).
70 */ 70 */
71 71
72 sc->reg_appl(sc, I4BCAPI_APPLID, sc->sc_nbch); 72 sc->reg_appl(sc, I4BCAPI_APPLID, sc->sc_nbch);
73 capi_listen_req(sc, 0x10007); 73 capi_listen_req(sc, 0x10007);
74 74
75 } else { 75 } else {
76 sc->sc_state = C_DOWN; 76 sc->sc_state = C_DOWN;
77 /* XXX go through cds and notify L4 of pdeact? XXX */ 77 /* XXX go through cds and notify L4 of pdeact? XXX */
78 } 78 }
79 break; 79 break;
80 80
81 case CAPI_CTRL_PROFILE: 81 case CAPI_CTRL_PROFILE:
82 memcpy(&sc->sc_profile, (char*) arg, sizeof(sc->sc_profile)); 82 memcpy(&sc->sc_profile, (char*) arg, sizeof(sc->sc_profile));
83 break; 83 break;
84 84
85 case CAPI_CTRL_NEW_NCCI: 85 case CAPI_CTRL_NEW_NCCI:
86 case CAPI_CTRL_FREE_NCCI: 86 case CAPI_CTRL_FREE_NCCI:
87 /* We ignore the controller's NCCI notifications. */ 87 /* We ignore the controller's NCCI notifications. */
88 break; 88 break;
89 89
90 default: 90 default:
91 printf("capi%d: unknown control %d\n", sc->sc_unit, op); 91 printf("capi%d: unknown control %d\n", sc->sc_unit, op);
92 } 92 }
93 93
94 return 0; 94 return 0;
95} 95}
96 96
97/* 97/*
98// i4b_capi_handlers 98// i4b_capi_handlers
99// Array of message-handler pairs used to dispatch CAPI 99// Array of message-handler pairs used to dispatch CAPI
100// messages sent to I4BCAPI_APPLID. 100// messages sent to I4BCAPI_APPLID.
101*/ 101*/
102 102
103static struct capi_cmdtab { 103static struct capi_cmdtab {
104 u_int16_t cmd; 104 u_int16_t cmd;
105 void (*handler)(capi_softc_t *, struct mbuf *); 105 void (*handler)(capi_softc_t *, struct mbuf *);
106} i4b_capi_handlers[] = { 106} i4b_capi_handlers[] = {
107 { CAPI_LISTEN_CONF, capi_listen_conf }, 107 { CAPI_LISTEN_CONF, capi_listen_conf },
108 { CAPI_INFO_IND, capi_info_ind }, 108 { CAPI_INFO_IND, capi_info_ind },
109 { CAPI_ALERT_CONF, capi_alert_conf }, 109 { CAPI_ALERT_CONF, capi_alert_conf },
110 { CAPI_CONNECT_CONF, capi_connect_conf }, 110 { CAPI_CONNECT_CONF, capi_connect_conf },
111 { CAPI_CONNECT_IND, capi_connect_ind }, 111 { CAPI_CONNECT_IND, capi_connect_ind },
112 { CAPI_CONNECT_ACTIVE_IND, capi_connect_active_ind }, 112 { CAPI_CONNECT_ACTIVE_IND, capi_connect_active_ind },
113 { CAPI_CONNECT_B3_CONF, capi_connect_b3_conf }, 113 { CAPI_CONNECT_B3_CONF, capi_connect_b3_conf },
114 { CAPI_CONNECT_B3_IND, capi_connect_b3_ind }, 114 { CAPI_CONNECT_B3_IND, capi_connect_b3_ind },
115 { CAPI_CONNECT_B3_ACTIVE_IND, capi_connect_b3_active_ind }, 115 { CAPI_CONNECT_B3_ACTIVE_IND, capi_connect_b3_active_ind },
116 { CAPI_DATA_B3_CONF, capi_data_b3_conf }, 116 { CAPI_DATA_B3_CONF, capi_data_b3_conf },
117 { CAPI_DATA_B3_IND, capi_data_b3_ind }, 117 { CAPI_DATA_B3_IND, capi_data_b3_ind },
118 { CAPI_DISCONNECT_B3_IND, capi_disconnect_b3_ind }, 118 { CAPI_DISCONNECT_B3_IND, capi_disconnect_b3_ind },
119 { CAPI_DISCONNECT_CONF, capi_disconnect_conf }, 119 { CAPI_DISCONNECT_CONF, capi_disconnect_conf },
120 { CAPI_DISCONNECT_IND, capi_disconnect_ind }, 120 { CAPI_DISCONNECT_IND, capi_disconnect_ind },
121 { 0, 0 } 121 { 0, 0 }
122}; 122};
123 123
124/* 124/*
125// capi_ll_receive 125// capi_ll_receive
126// CAPI link layer receive upcall. Called by a link layer 126// CAPI link layer receive upcall. Called by a link layer
127// driver to dispatch incoming CAPI messages. 127// driver to dispatch incoming CAPI messages.
128*/ 128*/
129 129
130int 130int
131capi_ll_receive(capi_softc_t *sc, struct mbuf *m) 131capi_ll_receive(capi_softc_t *sc, struct mbuf *m)
132{ 132{
133 u_int8_t *p = mtod(m, u_int8_t*); 133 u_int8_t *p = mtod(m, u_int8_t*);
134 u_int16_t len, applid, msgid, cmd; 134 u_int16_t len, applid, msgid, cmd;
135 135
136 capimsg_getu16(p + 0, &len); 136 capimsg_getu16(p + 0, &len);
137 capimsg_getu16(p + 2, &applid); 137 capimsg_getu16(p + 2, &applid);
138 capimsg_getu16(p + 4, &cmd); 138 capimsg_getu16(p + 4, &cmd);
139 capimsg_getu16(p + 6, &msgid); 139 capimsg_getu16(p + 6, &msgid);
140 140
141#if 0 141#if 0
142 printf("capi%d: ll_receive hdr %04x %04x %04x %04x\n", sc->sc_unit, 142 printf("capi%d: ll_receive hdr %04x %04x %04x %04x\n", sc->sc_unit,
143 len, applid, cmd, msgid); 143 len, applid, cmd, msgid);
144#endif 144#endif
145 145
146 if (applid == I4BCAPI_APPLID) { 146 if (applid == I4BCAPI_APPLID) {
147 struct capi_cmdtab *e; 147 struct capi_cmdtab *e;
148 for (e = i4b_capi_handlers; e->cmd && e->cmd != cmd; e++); 148 for (e = i4b_capi_handlers; e->cmd && e->cmd != cmd; e++);
149 if (e->cmd) (*e->handler)(sc, m); 149 if (e->cmd) (*e->handler)(sc, m);
150 else printf("capi%d: unknown message %04x\n", sc->sc_unit, cmd); 150 else printf("capi%d: unknown message %04x\n", sc->sc_unit, cmd);
151 151
152 } else { 152 } else {
153 /* XXX we could handle arbitrary ApplIds here XXX */ 153 /* XXX we could handle arbitrary ApplIds here XXX */
154 printf("capi%d: message %04x for unknown applid %d\n", sc->sc_unit, 154 printf("capi%d: message %04x for unknown applid %d\n", sc->sc_unit,
155 cmd, applid); 155 cmd, applid);
156 } 156 }
157 157
158 if (m->m_next) { 158 if (m->m_next) {
159 i4b_Bfreembuf(m->m_next); 159 i4b_Bfreembuf(m->m_next);
160 m->m_next = NULL; 160 m->m_next = NULL;
161 } 161 }
162 i4b_Dfreembuf(m); 162 i4b_Dfreembuf(m);
163 return(0); 163 return(0);
164} 164}