Beginnings of OMAP5 support.


(matt)

/*	$NetBSD: omap5430_intr.h,v 1.1 2013/06/15 21:55:09 matt Exp $	*/
/*-
 * Copyright (c) 2012 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Matt Thomas of 3am Software Foundry.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _ARM_OMAP_OMAP5430_INTR_H_
#define _ARM_OMAP_OMAP5430_INTR_H_

/*
 *  0-15 are used for SGIs (software generated interrupts).
 * 16-31 are used for PPIs (private peripheral interrupts).
 * 32... are used for SPIs (shared peripheral interrupts).
 *
 * To make things easier, SPIs will start at 0 and SGIs/PPIs
 * will at the end of SPIs (these are internal and shouldn't
 * be used by real devices).
 */
#define	PIC_MAXSOURCES		(32+160)
#define	PIC_MAXMAXSOURCES	(PIC_MAXSOURCES+8*32)

/*
 * The BCM53xx uses a generic interrupt controller so pull that stuff.
 */
#include <arm/cortex/gic_intr.h>
#include <arm/cortex/gtmr_intr.h>      /* A9 Timer PPIs */

#ifndef _LOCORE

#define IRQ_MPU_CLUSTER		(32+0)	// Illegal writes to interrupt controller memory map region
#define IRQ_CTI_0		(32+1)	// Cross-trigger module 0 (CTI0) interrupt
#define IRQ_CTI_1		(32+2)	// Cross-trigger module 1 (CTI1) interrupt
#define IRQ_ELM			(32+4)	// Error location process completion
#define IRQ_WD_TIMER_C0		(32+5)	// WD_TIMER_MPU_C0 warning interrupt
#define IRQ_WD_TIMER_C1		(32+6)	// WD_TIMER_MPU_C1 warning interrupt
#define IRQ_SYS_NIRQ1		(32+7)	// External interrupt 1 (active low)
#define IRQ_L3_DBG		(32+9)	// L3 interconnect debug error
#define IRQ_L3_APP		(32+10)	// L3 interconnect application error
#define IRQ_PRCM_MPU		(32+11)	// PRCM interrupt
#define IRQ_SDMA_0		(32+12)	// sDMA interrupt 0
#define IRQ_SDMA_1		(32+13)	// sDMA interrupt 1
#define IRQ_SDMA_2		(32+14)	// sDMA interrupt 2
#define IRQ_SDMA_3		(32+15)	// sDMA interrupt 3
#define IRQ_L3_MAIN_STAT_ALARM	(32+16)	// L3 N0C statistic collector alarm
#define IRQ_MCBSP1		(32+17)	// MCBSP1 interrupt
#define IRQ_SR_MPU		(32+18)	// SmartReflex MPU interrupt
#define IRQ_SR_CORE		(32+19)	// SmartReflex Core interrupt
#define IRQ_GPMC		(32+20)	// GPMC interrupt
#define IRQ_GPU			(32+21)	// 2D/3D graphics module interrupt
#define IRQ_MCBSP2		(32+22)	// MCBSP2 interrupt
#define IRQ_MCBSP3		(32+23)	// MCBSP3 interrupt
#define IRQ_ISS5		(32+24)	// Imaging subsystem interrupt 5
#define IRQ_DSS_DISPC		(32+25)	// Display controller interrupt
#define IRQ_MAIL_U0_MPU		(32+26)	// Mailbox user 0 interrupt
#define IRQ_27			(32+27)	// Reserved
#define IRQ_DSP_MMU		(32+28)	// DSP MMU interrupt
#define IRQ_GPIO1_MPU		(32+29)	// GPIO1 MPU interrupt
#define IRQ_GPIO2_MPU		(32+30)	// GPIO2 MPU interrupt
#define IRQ_GPIO3_MPU		(32+31)	// GPIO3 MPU interrupt
#define IRQ_GPIO4_MPU		(32+32)	// GPIO4 MPU interrupt
#define IRQ_GPIO5_MPU		(32+33)	// GPIO5 MPU interrupt
#define IRQ_GPIO6_MPU		(32+34)	// GPIO6 MPU interrupt
#define IRQ_GPIO7_MPU		(32+35)	// GPIO7 MPU interrupt
#define IRQ_WDT3		(32+36)	// WDTIMER3 overflow
#define IRQ_GPT1		(32+37)	// GPTIMER1 interrupt
#define IRQ_GPT2		(32+38)	// GPTIMER2 interrupt
#define IRQ_GPT3		(32+39)	// GPTIMER3 interrupt
#define IRQ_GPT4		(32+40)	// GPTIMER4 interrupt
#define IRQ_GPT5		(32+41)	// GPTIMER5 interrupt
#define IRQ_GPT6		(32+42)	// GPTIMER6 interrupt
#define IRQ_GPT7		(32+43)	// GPTIMER7 interrupt
#define IRQ_GPT8		(32+44)	// GPTIMER8 interrupt
#define IRQ_GPT9		(32+45)	// GPTIMER9 interrupt
#define IRQ_GPT10		(32+46)	// GPTIMER10 interrupt
#define IRQ_GPT11		(32+47)	// GPTIMER11 interrupt
#define IRQ_MCSPI4		(32+48)	// MCSPI4 interrupt
#define IRQ_DSS_DSI1_A		(32+53)	// Display Subsystem DSI1_A interrupt
#define IRQ_SATA		(32+54)	// SATA interrupt
#define IRQ_DSS_DSI1_C		(32+55)	// Display Subsystem DSI1_C interrupt
#define IRQ_I2C1		(32+56)	// I2C1 interrupt
#define IRQ_I2C2		(32+57)	// I2C2 interrupt
#define IRQ_HDQ			(32+58)	// HDQ/1wire interrupt
#define IRQ_MMC5		(32+59)	// MMC5 interrupt
#define IRQ_I2C3		(32+61)	// I2C3 interrupt
#define IRQ_I2C4		(32+62)	// I2C4 interrupt
#define IRQ_MCSPI1		(32+65)	// MCSPI1 interrupt
#define IRQ_MCSPI2		(32+66)	// MCSPI2 interrupt
#define IRQ_HSI_P1_MPU		(32+67)	// HSI Port 1 interrupt
#define IRQ_HSI_P2_MPU		(32+68)	// HSI Port 2 interrupt
#define IRQ_FDIF_3		(32+69)	// Face detect interrupt 3
#define IRQ_UART4		(32+70)	// UART module 4 interrupt
#define IRQ_HSI_DMA_MPU		(32+71)	// HSI DMA engine IRQ_MPU request
#define IRQ_UART1		(32+72)	// UART1 interrupt
#define IRQ_UART2		(32+73)	// UART2 interrupt
#define IRQ_UART3		(32+74)	// UART3 interrupt
#define IRQ_PBIAS		(32+75)	// Merged interrupt for PBIASlite1 and 2
#define IRQ_HSUSB_OHCI		(32+76)	// HSUSB MP host interrupt OHCI controller
#define IRQ_HSUSB_EHCI		(32+77)	// HSUSB MP host interrupt EHCI controller
#define IRQ_HSUSB_TLL		(32+78)	// HSUSB MP TLL interrupt
#define IRQ_WDT2		(32+80)	// WDTIMER2 interrupt
#define IRQ_MMC1		(32+83)	// MMC1 interrupt
#define IRQ_MMC2		(32+86)	// MMC2 interrupt
#define IRQ_DEBUGSS_CT_UART	(32+90)	// CT_UART interrupt generated when data ready on RX or when TX empty
#define IRQ_MCSPI3		(32+91)	// MCSPI3 interrupt
#define IRQ_HSUSB_OTG		(32+92)	// HSUSB OTG controller interrupt
#define IRQ_HSUSB_OTG_DMA	(32+93)	// HSUSB OTG DMA interrupt
#define IRQ_MMC3		(32+94)	// MMC3 interrupt
#define IRQ_MMC4		(32+96)	// MMC4 interrupt
#define IRQ_ABE_MPU		(32+99)	// Audio back-end interrupt
#define IRQ_IPU_MMU		(32+100) // Cortex-M4 MMU interrupt
#define IRQ_HDMI		(32+101) // Display subsystem HDMI interrupt
#define IRQ_SR_IVA		(32+102)	// SmartReflex IVA interrupt
#define IRQ_IVAHD2		(32+103)	// Sync interrupt from ICONT2 (vDMA)
#define IRQ_IVAHD1		(32+104)	// Sync interrupt from ICONT1
#define IRQ_UART5		(32+105)	// UART5 interrupt
#define IRQ_UART6		(32+106)	// UART6 interrupt
#define IRQ_IVAHD_MAILBOX_0	(32+107)	// IVAHD mailbox interrupt 0
#define IRQ_MCASP1_AXINT	(32+109)	// McASP1 transmit interrupt
#define IRQ_EMIF1		(32+110)	// EMIF1 interrupt
#define IRQ_EMIF2		(32+111)	// EMIF2 interrupt
#define IRQ_MCPDM		(32+112)	// MCPDM interrupt
#define IRQ_DMM			(32+113)	// DMM interrupt
#define IRQ_DMIC		(32+114)	// DMIC interupt
#define IRQ_SYS_NIRQ2		(32+119)	// External interrupt 2 (active low)
#define	IRQ_KBD_CTL		(32+120)	// Keyboard controller interrupt
#define IRQ_GPIO8		(32+121)	// GPIO8 interupt
#define IRQ_BB2D		(32+125)	// BB2D interupt

#endif /* _LOCORE */

#endif /* _ARM_OMAP_OMAP5430_INTR_H_ */

/* $NetBSD: omap5_ahcisata.c,v 1.1 2013/06/15 21:55:09 matt Exp $ */

/*-
 * Copyright (c) 2013 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Matt Thomas of 3am Software Foundry.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: omap5_ahcisata.c,v 1.1 2013/06/15 21:55:09 matt Exp $");

#include "locators.h"

#include "opt_omap.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/intr.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/bus.h>
#include <sys/gpio.h>

#include <dev/ata/atavar.h>

#include <dev/ic/ahcisatavar.h>

#include <arm/omap/omap2_obioreg.h>
#include <arm/omap/omap2_obiovar.h>
#include <arm/omap/omap2_reg.h>

struct omap5_ahci_softc {
	struct ahci_softc	psc_sc;
	void		*psc_ih;
};

static int
omap5_ahcisata_match(device_t parent, cfdata_t match, void *aux)
{
#if defined(OMAP5)
	struct obio_attach_args *obio = aux;

	if (obio->obio_addr == AHCI1_BASE_OMAP5)
		return 1;
#endif

	return 0;
}

static void
omap5_ahcisata_attach(device_t parent, device_t self, void *aux)
{
	struct omap5_ahci_softc *psc = device_private(self);
	struct ahci_softc * const sc = &psc->psc_sc;
	struct obio_attach_args * const obio = aux;
	int rv;

	sc->sc_atac.atac_dev = self;

	aprint_naive("\n");
	aprint_normal(": OMAP AHCI controller\n");

	sc->sc_dmat = obio->obio_dmat;
	sc->sc_ahcit = obio->obio_iot;
	sc->sc_ahcis = obio->obio_size;
	rv = bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
	    0, &sc->sc_ahcih);
	if (rv) {
		aprint_error_dev(self, "couldn't map memory space\n");
		return;
	}

	psc->psc_ih = intr_establish(obio->obio_intr, IPL_BIO, IST_LEVEL,
	    ahci_intr, sc);

	ahci_attach(sc);
}

static int
omap5_ahcisata_detach(device_t self, int flags)
{
	struct omap5_ahci_softc * const psc = device_private(self);
	struct ahci_softc * const sc = &psc->psc_sc;
	int rv;

	rv = ahci_detach(sc, flags);
	if (rv)
		return rv;

	if (psc->psc_ih) {
		intr_disestablish(psc->psc_ih);
		psc->psc_ih = NULL;
	}

	if (sc->sc_ahcis) {
		bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
		sc->sc_ahcit = 0;
		sc->sc_ahcih = 0;
		sc->sc_ahcis = 0;
	}

	return 0;
}

CFATTACH_DECL_NEW(omap5_ahcisata, sizeof(struct omap5_ahci_softc),
    omap5_ahcisata_match,
    omap5_ahcisata_attach,
    omap5_ahcisata_detach,
    0
);