Sun Jun 16 16:42:13 2013 UTC ()
OMAP4 EHCI enhancements


(matt)
diff -r1.18 -r1.19 src/sys/arch/arm/omap/omap2_reg.h
diff -r1.6 -r1.7 src/sys/arch/arm/omap/omap3_ehci.c
cvs diff -r1.18 -r1.19 src/sys/arch/arm/omap/Attic/omap2_reg.h (expand / switch to unified diff)

--- src/sys/arch/arm/omap/Attic/omap2_reg.h 2013/04/30 05:37:51 1.18
+++ src/sys/arch/arm/omap/Attic/omap2_reg.h 2013/06/16 16:42:13 1.19
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: omap2_reg.h,v 1.18 2013/04/30 05:37:51 matt Exp $ */ 1/* $NetBSD: omap2_reg.h,v 1.19 2013/06/16 16:42:13 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007 Microsoft 4 * Copyright (c) 2007 Microsoft
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -77,39 +77,65 @@ @@ -77,39 +77,65 @@
77 77
78#define OMAP4430_L4_CORE_BASE 0x4A000000 78#define OMAP4430_L4_CORE_BASE 0x4A000000
79#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */ 79#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
80 80
81#define OMAP4430_L4_WAKEUP_BASE 0x4A300000 81#define OMAP4430_L4_WAKEUP_BASE 0x4A300000
82#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */ 82#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
83 83
84#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000 84#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000
85#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */ 85#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
86 86
87#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */ 87#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
88#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */ 88#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
89 89
 90#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
 91#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
 92
 93#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
 94#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
 95
 96/* OMAP5 processors */
 97
 98#define OMAP5430_L4_CORE_BASE 0x4A000000
 99#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
 100
 101#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
 102#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
 103
 104#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
 105#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
 106
 107#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
 108#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
 109
 110#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
 111#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
 112
 113#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
 114#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
 115
90/* TI Sitara AM335x (OMAP like) */ 116/* TI Sitara AM335x (OMAP like) */
91 117
92#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000 118#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
93#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */ 119#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */
94 120
95#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000 121#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000
96#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */ 122#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
97 123
98#define TI_AM335X_L4_FAST_BASE 0x4A000000 124#define TI_AM335X_L4_FAST_BASE 0x4A000000
99#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */ 125#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
100 126
101#define TI_AM335X_L4_EMIF_BASE 0x4C000000 127#define TI_AM335X_EMIF1_BASE 0x4C000000
102#define TI_AM335X_L4_EMIF_SIZE 0x01000000 /* 16MB */ 128#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
103 129
104/* TI Sitara DM37xx (OMAP like) */ 130/* TI Sitara DM37xx (OMAP like) */
105 131
106#define TI_DM37XX_L4_CORE_BASE 0x48000000 132#define TI_DM37XX_L4_CORE_BASE 0x48000000
107#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */ 133#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */
108 134
109#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000 135#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000
110#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */ 136#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */
111 137
112#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000 138#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000
113#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */ 139#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
114 140
115#define TI_DM37XX_L4_EMULATION_BASE 0x54000000 141#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
@@ -123,26 +149,29 @@ @@ -123,26 +149,29 @@
123#endif 149#endif
124#ifdef OMAP_2420 150#ifdef OMAP_2420
125#define OMAP2_CM_BASE 0x48008000 151#define OMAP2_CM_BASE 0x48008000
126#endif 152#endif
127#ifdef OMAP_3430 153#ifdef OMAP_3430
128#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000) 154#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000)
129#endif 155#endif
130#ifdef OMAP_3530 156#ifdef OMAP_3530
131#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000) 157#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
132#endif 158#endif
133#ifdef OMAP_4430 159#ifdef OMAP_4430
134#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000) 160#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
135#endif 161#endif
 162#ifdef OMAP_5430
 163#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
 164#endif
136#ifdef TI_AM335X 165#ifdef TI_AM335X
137#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000) 166#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
138#endif 167#endif
139#ifdef TI_DM37XX 168#ifdef TI_DM37XX
140#define OMAP2_CM_BASE 0x48004000 169#define OMAP2_CM_BASE 0x48004000
141#endif 170#endif
142 171
143#define OMAP2_CM_CLKSEL_MPU 0x140 172#define OMAP2_CM_CLKSEL_MPU 0x140
144#define OMAP2_CM_FCLKEN1_CORE 0x200 173#define OMAP2_CM_FCLKEN1_CORE 0x200
145#define OMAP2_CM_FCLKEN2_CORE 0x204 174#define OMAP2_CM_FCLKEN2_CORE 0x204
146#define OMAP2_CM_ICLKEN1_CORE 0x210 175#define OMAP2_CM_ICLKEN1_CORE 0x210
147#define OMAP2_CM_ICLKEN2_CORE 0x214 176#define OMAP2_CM_ICLKEN2_CORE 0x214
148#define OMAP2_CM_CLKSEL2_CORE 0x244 177#define OMAP2_CM_CLKSEL2_CORE 0x244
@@ -336,26 +365,29 @@ @@ -336,26 +365,29 @@
336 365
337/* 366/*
338 * Power Management registers base, offsets, and size 367 * Power Management registers base, offsets, and size
339 */ 368 */
340#ifdef OMAP_3430 369#ifdef OMAP_3430
341#define OMAP2_PRM_BASE 0x48306000 370#define OMAP2_PRM_BASE 0x48306000
342#endif 371#endif
343#ifdef OMAP_3530 372#ifdef OMAP_3530
344#define OMAP2_PRM_BASE 0x48306000 373#define OMAP2_PRM_BASE 0x48306000
345#endif 374#endif
346#ifdef OMAP_4430 375#ifdef OMAP_4430
347#define OMAP2_PRM_BASE (OMAP4430_L4_WAKEUP_BASE + 0x6000) 376#define OMAP2_PRM_BASE (OMAP4430_L4_WAKEUP_BASE + 0x6000)
348#endif 377#endif
 378#ifdef OMAP_5430
 379#define OMAP2_PRM_BASE (OMAP5430_L4_WAKEUP_BASE + 0x6000)
 380#endif
349#ifdef TI_AM335X 381#ifdef TI_AM335X
350#define OMAP2_PRM_BASE 0x48306000 382#define OMAP2_PRM_BASE 0x48306000
351#endif 383#endif
352#ifdef TI_DM37XX 384#ifdef TI_DM37XX
353#define OMAP2_PRM_BASE 0x48306000 385#define OMAP2_PRM_BASE 0x48306000
354#endif 386#endif
355 387
356#define OMAP2_PRM_SIZE 0x00002000 /* 8k */ 388#define OMAP2_PRM_SIZE 0x00002000 /* 8k */
357 389
358/* module offsets */ 390/* module offsets */
359#define OCP_MOD 0x0800 391#define OCP_MOD 0x0800
360#define MPU_MOD 0x0900 392#define MPU_MOD 0x0900
361#define CORE_MOD 0x0a00 393#define CORE_MOD 0x0a00
@@ -660,26 +692,35 @@ @@ -660,26 +692,35 @@
660#define GPIO2_BASE_3530 0x49050000 692#define GPIO2_BASE_3530 0x49050000
661#define GPIO3_BASE_3530 0x49052000 693#define GPIO3_BASE_3530 0x49052000
662#define GPIO4_BASE_3530 0x49054000 694#define GPIO4_BASE_3530 0x49054000
663#define GPIO5_BASE_3530 0x49056000 695#define GPIO5_BASE_3530 0x49056000
664#define GPIO6_BASE_3530 0x49058000 696#define GPIO6_BASE_3530 0x49058000
665 697
666#define GPIO1_BASE_4430 0x4a310000 698#define GPIO1_BASE_4430 0x4a310000
667#define GPIO2_BASE_4430 0x48055000 699#define GPIO2_BASE_4430 0x48055000
668#define GPIO3_BASE_4430 0x48057000 700#define GPIO3_BASE_4430 0x48057000
669#define GPIO4_BASE_4430 0x48059000 701#define GPIO4_BASE_4430 0x48059000
670#define GPIO5_BASE_4430 0x4805b000 702#define GPIO5_BASE_4430 0x4805b000
671#define GPIO6_BASE_4430 0x4805d000 703#define GPIO6_BASE_4430 0x4805d000
672 704
 705#define GPIO1_BASE_5430 0x4ae10000
 706#define GPIO2_BASE_5430 0x48055000
 707#define GPIO3_BASE_5430 0x48057000
 708#define GPIO4_BASE_5430 0x48059000
 709#define GPIO5_BASE_5430 0x4805b000
 710#define GPIO6_BASE_5430 0x4805d000
 711#define GPIO7_BASE_5430 0x48051000
 712#define GPIO8_BASE_5430 0x48053000
 713
673#define GPIO0_BASE_TI_AM335X 0x44e07000 714#define GPIO0_BASE_TI_AM335X 0x44e07000
674#define GPIO1_BASE_TI_AM335X 0x4804c000 715#define GPIO1_BASE_TI_AM335X 0x4804c000
675#define GPIO2_BASE_TI_AM335X 0x481ac000 716#define GPIO2_BASE_TI_AM335X 0x481ac000
676#define GPIO3_BASE_TI_AM335X 0x481ae000 717#define GPIO3_BASE_TI_AM335X 0x481ae000
677 718
678#define GPIO1_BASE_TI_DM37XX 0x48310000 719#define GPIO1_BASE_TI_DM37XX 0x48310000
679#define GPIO2_BASE_TI_DM37XX 0x49050000 720#define GPIO2_BASE_TI_DM37XX 0x49050000
680#define GPIO3_BASE_TI_DM37XX 0x49052000 721#define GPIO3_BASE_TI_DM37XX 0x49052000
681#define GPIO4_BASE_TI_DM37XX 0x49054000 722#define GPIO4_BASE_TI_DM37XX 0x49054000
682#define GPIO5_BASE_TI_DM37XX 0x49056000 723#define GPIO5_BASE_TI_DM37XX 0x49056000
683#define GPIO6_BASE_TI_DM37XX 0x49058000 724#define GPIO6_BASE_TI_DM37XX 0x49058000
684 725
685#define GPIO_IRQSTATUS1 0x018 726#define GPIO_IRQSTATUS1 0x018
@@ -708,49 +749,46 @@ @@ -708,49 +749,46 @@
708 749
709/* 750/*
710 * I2C 751 * I2C
711 */ 752 */
712#define I2C1_BASE_3530 0x48070000 753#define I2C1_BASE_3530 0x48070000
713#define I2C2_BASE_3530 0x48072000 754#define I2C2_BASE_3530 0x48072000
714#define I2C3_BASE_3530 0x48060000 755#define I2C3_BASE_3530 0x48060000
715 756
716/* 757/*
717 * USB Host 758 * USB Host
718 */ 759 */
719#define OHCI1_BASE_2430 0x4805e000 760#define OHCI1_BASE_2430 0x4805e000
720 761
721#define OHCI1_BASE_3430 0x48064400 762#define OHCI1_BASE_OMAP3 0x48064400
722#define EHCI1_BASE_3430 0x48064800 763#define EHCI1_BASE_OMAP3 0x48064800
723 764
724#define OHCI1_BASE_3530 0x48064400 765#define OHCI1_BASE_OMAP4 0x4A064800
725#define EHCI1_BASE_3530 0x48064800 766#define EHCI1_BASE_OMAP4 0x4A064C00
726 
727#define OHCI1_BASE_4430 0x4A064800 
728#define EHCI1_BASE_4430 0x4A064C00 
729 767
730/* 768/*
731 * SDRC 769 * SDRC
732 */ 770 */
733#define OMAP3530_SDRC_BASE 0x6d000000 771#define OMAP3530_SDRC_BASE 0x6d000000
734#define OMAP3530_SDRC_SIZE 0x00010000 /* 16KB */ 772#define OMAP3530_SDRC_SIZE 0x00010000 /* 16KB */
735 773
736/* 774/*
737 * DMA 775 * DMA
738 */ 776 */
739#define OMAP3530_SDMA_BASE 0x48056000 777#define OMAP3530_SDMA_BASE 0x48056000
740#define OMAP3530_SDMA_SIZE 0x00001000 /* 4KB */ 778#define OMAP3530_SDMA_SIZE 0x00001000 /* 4KB */
741 779
742#ifdef TI_AM335X 780#ifdef TI_AM335X
743#define TI_AM335X_CTLMOD_BASE 0x44e10000 781#define TI_AM335X_CTLMOD_BASE 0x44e10000
744#define CTLMOD_CONTROL_STATUS 0x40 782#define CTLMOD_CONTROL_STATUS 0x40
745#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22) 783#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22)
746 784#endif
747#define TI_AM335X_EMIF0_BASE 0x4c000000 785#if defined(OMAP4) || defined(TI_AM335X)
748#define TI_AM335X_EMIF0_SIZE 0x00100000 
749#define EMIF_SDRAM_CONFIG 8 786#define EMIF_SDRAM_CONFIG 8
750#define SDRAM_CONFIG_WIDTH __BITS(15,14) 787#define SDRAM_CONFIG_WIDTH __BITS(15,14)
751#define SDRAM_CONFIG_RSIZE __BITS(9,7) 788#define SDRAM_CONFIG_RSIZE __BITS(9,7)
752#define SDRAM_CONFIG_IBANK __BITS(6,4) 789#define SDRAM_CONFIG_IBANK __BITS(6,4)
 790#define SDRAM_CONFIG_EBANK __BIT(3)
753#define SDRAM_CONFIG_PAGESIZE __BITS(2,0) 791#define SDRAM_CONFIG_PAGESIZE __BITS(2,0)
754#endif 792#endif
755  793
756#endif /* _ARM_OMAP_OMAP2_REG_H_ */ 794#endif /* _ARM_OMAP_OMAP2_REG_H_ */
cvs diff -r1.6 -r1.7 src/sys/arch/arm/omap/Attic/omap3_ehci.c (expand / switch to unified diff)

--- src/sys/arch/arm/omap/Attic/omap3_ehci.c 2012/12/24 06:41:02 1.6
+++ src/sys/arch/arm/omap/Attic/omap3_ehci.c 2013/06/16 16:42:13 1.7
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $ */ 1/* $NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products 12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission. 13 * derived from this software without specific prior written permission.
14 * 14 *
@@ -16,27 +16,27 @@ @@ -16,27 +16,27 @@
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE. 25 * SUCH DAMAGE.
26 */ 26 */
27 27
28#include <sys/cdefs.h> 28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $"); 29__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $");
30 30
31#include "locators.h" 31#include "locators.h"
32 32
33#include "opt_omap.h" 33#include "opt_omap.h"
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/systm.h> 36#include <sys/systm.h>
37#include <sys/kernel.h> 37#include <sys/kernel.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/bus.h> 39#include <sys/bus.h>
40#include <sys/gpio.h> 40#include <sys/gpio.h>
41 41
42#include <machine/intr.h> 42#include <machine/intr.h>
@@ -263,30 +263,38 @@ omap3_ehci_attach1(device_t self) @@ -263,30 +263,38 @@ omap3_ehci_attach1(device_t self)
263 263
264 err = ehci_init(&sc->sc); 264 err = ehci_init(&sc->sc);
265 if (err != USBD_NORMAL_COMPLETION) { 265 if (err != USBD_NORMAL_COMPLETION) {
266 aprint_error_dev(self, "init failed, error = %d\n", err); 266 aprint_error_dev(self, "init failed, error = %d\n", err);
267 return; 267 return;
268 } 268 }
269 269
270 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 270 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
271} 271}
272 272
273static int 273static int
274omap3_ehci_match(device_t parent, cfdata_t match, void *opaque) 274omap3_ehci_match(device_t parent, cfdata_t match, void *opaque)
275{ 275{
 276#ifdef OMAP3
276 struct obio_attach_args *obio = opaque; 277 struct obio_attach_args *obio = opaque;
 278#endif
277 279
278 if (obio->obio_addr == EHCI1_BASE_3530) 280#if defined(OMAP3) && !defined(OMAP4)
 281 if (obio->obio_addr == EHCI1_BASE_OMAP3)
 282 return 1;
 283#endif
 284#ifdef OMAP4
 285 if (obio->obio_addr == EHCI1_BASE_OMAP4)
279 return 1; 286 return 1;
 287#endif
280 288
281 return 0; 289 return 0;
282} 290}
283 291
284static enum omap3_ehci_port_mode 292static enum omap3_ehci_port_mode
285omap3_ehci_get_port_mode(prop_dictionary_t prop, const char *key) 293omap3_ehci_get_port_mode(prop_dictionary_t prop, const char *key)
286{ 294{
287 const char *s = NULL; 295 const char *s = NULL;
288 enum omap3_ehci_port_mode mode = OMAP3_EHCI_PORT_MODE_NONE; 296 enum omap3_ehci_port_mode mode = OMAP3_EHCI_PORT_MODE_NONE;
289 297
290 if (prop_dictionary_get_cstring_nocopy(prop, key, &s) && s != NULL) { 298 if (prop_dictionary_get_cstring_nocopy(prop, key, &s) && s != NULL) {
291 if (strcmp(s, "phy") == 0) { 299 if (strcmp(s, "phy") == 0) {
292 mode = OMAP3_EHCI_PORT_MODE_PHY; 300 mode = OMAP3_EHCI_PORT_MODE_PHY;
@@ -419,58 +427,68 @@ omap3_ehci_detach(device_t self, int fla @@ -419,58 +427,68 @@ omap3_ehci_detach(device_t self, int fla
419 if (sc->sc.sc_size) { 427 if (sc->sc.sc_size) {
420 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 428 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
421 sc->sc.sc_size = 0; 429 sc->sc.sc_size = 0;
422 } 430 }
423 431
424 return 0; 432 return 0;
425} 433}
426 434
427static void 435static void
428dpll5_init(struct omap3_ehci_softc *sc) 436dpll5_init(struct omap3_ehci_softc *sc)
429{ 437{
430 bus_space_tag_t iot = sc->sc.iot; 438 bus_space_tag_t iot = sc->sc.iot;
431 bus_space_handle_t ioh; 439 bus_space_handle_t ioh;
432 uint32_t m, n, m2; 
433 int err; 440 int err;
434 441
435 if (sc->sc_dpll5.m == 0 || sc->sc_dpll5.n == 0 || sc->sc_dpll5.m2 == 0) 442 if (sc->sc_dpll5.m == 0 || sc->sc_dpll5.n == 0 || sc->sc_dpll5.m2 == 0)
436 return; 443 return;
437 444
438 err = bus_space_map(iot, CCR_CM_BASE, CCR_CM_SIZE, 0, &ioh); 445 err = bus_space_map(iot, CCR_CM_BASE, CCR_CM_SIZE, 0, &ioh);
439 if (err) 446 if (err)
440 panic("%s: cannot map CCR_CM_BASE at %#x, error %d\n", 447 panic("%s: cannot map CCR_CM_BASE at %#x, error %d\n",
441 __func__, CCR_CM_BASE, err); 448 __func__, CCR_CM_BASE, err);
442 449
443#if OMAP_MPU_TIMER_CLOCK_FREQ != 12000000 
444#error FIXME 
445#endif 
446 450
 451#if defined(OMAP_3530) || defined(OMAP_3540)
447 /* set the multiplier and divider values for the desired CLKOUT freq */ 452 /* set the multiplier and divider values for the desired CLKOUT freq */
448 m = sc->sc_dpll5.m; 453 uint32_t m = sc->sc_dpll5.m;
449 n = sc->sc_dpll5.n; 454 uint32_t n = sc->sc_dpll5.n;
450 /* set the corresponding output dividers */ 455 /* set the corresponding output dividers */
451 m2 = sc->sc_dpll5.m2; 456 uint32_t m2 = sc->sc_dpll5.m2;
452 457
453 /* 4.7.6.2 In the DPLL programming sequence, the DPLL_FREQSEL must be programmed 458 KASSERTMSG(479900000 <= 2 * m * (omap_sys_clk / ((n + 1) * m2)),
454 * before the new Multiplier factor M and the Divider factor N are programmed so 459 "m=%u n=%u m2=%u freq=%u",
455 * that the new value is taken into account during current DPLL relock. 460 m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
 461 KASSERTMSG(2 * m * (omap_sys_clk / ((n + 1) * m2)) <= 480100000,
 462 "m=%u n=%u m2=%u freq=%u",
 463 m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
 464
 465 /* 4.7.6.2
 466 * In the DPLL programming sequence, the DPLL_FREQSEL must be
 467 * programmed before the new Multiplier factor M and the Divider
 468 * factor N are programmed so that the new value is taken into
 469 * account during current DPLL relock.
456 */ 470 */
457 bus_space_write_4(iot, ioh, CM_CLKEN2_PLL, (0x4 << 4) | 0x7); 471 bus_space_write_4(iot, ioh, CM_CLKEN2_PLL, (0x4 << 4) | 0x7);
458 472
459 bus_space_write_4(iot, ioh, CM_CLKSEL4_PLL, (m << 8) | n); 473 bus_space_write_4(iot, ioh, CM_CLKSEL4_PLL, (m << 8) | n);
460 bus_space_write_4(iot, ioh, CM_CLKSEL5_PLL, m2); 474 bus_space_write_4(iot, ioh, CM_CLKSEL5_PLL, m2);
461 475
462 /* Put DPLL5 into low power stop mode when the 120MHz clock is not required (restarted automatically) */ 476 /*
 477 * Put DPLL5 into low power stop mode when the 120MHz clock
 478 * is not required (restarted automatically)
 479 */
463 bus_space_write_4(iot, ioh, CM_AUTOIDLE2_PLL, AUTO_PERIPH2_DPLL); 480 bus_space_write_4(iot, ioh, CM_AUTOIDLE2_PLL, AUTO_PERIPH2_DPLL);
 481#endif /* OMAP_3540 || OMAP_3530 */
464 482
465 bus_space_unmap(iot, ioh, CCR_CM_SIZE); 483 bus_space_unmap(iot, ioh, CCR_CM_SIZE);
466} 484}
467 485
468static void 486static void
469usbhost_init(struct omap3_ehci_softc *sc, int enable) 487usbhost_init(struct omap3_ehci_softc *sc, int enable)
470{ 488{
471 bus_space_tag_t iot = sc->sc.iot; 489 bus_space_tag_t iot = sc->sc.iot;
472 bus_space_handle_t ioh; 490 bus_space_handle_t ioh;
473 uint32_t r; 491 uint32_t r;
474 int err; 492 int err;
475 493
476 /* 494 /*