Sun Jun 16 17:57:21 2013 UTC ()
Fix pasto.


(matt)
diff -r1.14 -r1.15 src/sys/arch/evbarm/beagle/beagle_start.S
cvs diff -r1.14 -r1.15 src/sys/arch/evbarm/beagle/Attic/beagle_start.S (expand / switch to unified diff)

--- src/sys/arch/evbarm/beagle/Attic/beagle_start.S 2013/06/16 16:48:23 1.14
+++ src/sys/arch/evbarm/beagle/Attic/beagle_start.S 2013/06/16 17:57:21 1.15
@@ -88,27 +88,27 @@ @@ -88,27 +88,27 @@
88#include <machine/asm.h> 88#include <machine/asm.h>
89#include <arm/armreg.h> 89#include <arm/armreg.h>
90#include "assym.h" 90#include "assym.h"
91 91
92#include <arm/omap/omap2_obioreg.h> 92#include <arm/omap/omap2_obioreg.h>
93#include <evbarm/beagle/beagle.h>  93#include <evbarm/beagle/beagle.h>
94 94
95#ifdef MEMSIZE 95#ifdef MEMSIZE
96#define INIT_MEMSIZE MEMSIZE 96#define INIT_MEMSIZE MEMSIZE
97#else 97#else
98#define INIT_MEMSIZE 128 98#define INIT_MEMSIZE 128
99#endif 99#endif
100 100
101RCSID("$NetBSD: beagle_start.S,v 1.14 2013/06/16 16:48:23 matt Exp $") 101RCSID("$NetBSD: beagle_start.S,v 1.15 2013/06/16 17:57:21 matt Exp $")
102 102
103#define Invalidate_I_cache(reg) \ 103#define Invalidate_I_cache(reg) \
104 mcr p15, 0, reg, c7, c5, 0 /* Invalidate Entire I cache */ 104 mcr p15, 0, reg, c7, c5, 0 /* Invalidate Entire I cache */
105 105
106/* 106/*
107 * Kernel start routine for BEAGLEBOARD boards. 107 * Kernel start routine for BEAGLEBOARD boards.
108 * At this point, this code has been loaded into SDRAM 108 * At this point, this code has been loaded into SDRAM
109 * and the MMU is off 109 * and the MMU is off
110 */ 110 */
111 .section .start,"ax",%progbits 111 .section .start,"ax",%progbits
112 112
113 .global _C_LABEL(beagle_start) 113 .global _C_LABEL(beagle_start)
114_C_LABEL(beagle_start): 114_C_LABEL(beagle_start):
@@ -275,28 +275,28 @@ Lauxctl_CZ_restrict: @@ -275,28 +275,28 @@ Lauxctl_CZ_restrict:
275 275
276mmu_init_table: 276mmu_init_table:
277 /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */ 277 /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */
278 MMU_INIT(KERNEL_BASE, KERNEL_BASE, 278 MMU_INIT(KERNEL_BASE, KERNEL_BASE,
279 (INIT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 279 (INIT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
280 L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C) 280 L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
281 281
282 /* Map first 1MB of L4 CORE (so console will work) */ 282 /* Map first 1MB of L4 CORE (so console will work) */
283 MMU_INIT(OMAP_L4_CORE_VBASE, OMAP_L4_CORE_BASE, 283 MMU_INIT(OMAP_L4_CORE_VBASE, OMAP_L4_CORE_BASE,
284 (OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 284 (OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
285 L1_S_PROTO | L1_S_APv7_KRW) 285 L1_S_PROTO | L1_S_APv7_KRW)
286 286
287#if OMAP_L4_CORE_BASE <= CONSADDR \ 287#if OMAP_L4_CORE_BASE <= CONSADDR \
288 /* Map first 1MB of L4 CORE 1:1 (so console will work) */ 
289 && CONSADDR < OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE 288 && CONSADDR < OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE
 289 /* Map first 1MB of L4 CORE 1:1 (so console will work) */
290 MMU_INIT(OMAP_L4_CORE_BASE, OMAP_L4_CORE_BASE, 290 MMU_INIT(OMAP_L4_CORE_BASE, OMAP_L4_CORE_BASE,
291 (OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 291 (OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
292 L1_S_PROTO | L1_S_APv7_KRW) 292 L1_S_PROTO | L1_S_APv7_KRW)
293#endif 293#endif
294 294
295 /* Map first 4MB of L4 PERIPHERAL (so console will work) */ 295 /* Map first 4MB of L4 PERIPHERAL (so console will work) */
296 MMU_INIT(OMAP_L4_PERIPHERAL_VBASE, OMAP_L4_PERIPHERAL_BASE, 296 MMU_INIT(OMAP_L4_PERIPHERAL_VBASE, OMAP_L4_PERIPHERAL_BASE,
297 (OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 297 (OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
298 L1_S_PROTO | L1_S_APv7_KRW) 298 L1_S_PROTO | L1_S_APv7_KRW)
299 299
300#if OMAP_L4_PERIPHERAL_BASE <= CONSADDR \ 300#if OMAP_L4_PERIPHERAL_BASE <= CONSADDR \
301 && CONSADDR < OMAP_L4_PERIPHERAL_BASE + OMAP_L4_PERIPHERAL_SIZE 301 && CONSADDR < OMAP_L4_PERIPHERAL_BASE + OMAP_L4_PERIPHERAL_SIZE
302 /* Map first 1MB of L4 PERIPHERAL 1:1 (so console will work) */ 302 /* Map first 1MB of L4 PERIPHERAL 1:1 (so console will work) */