 @@ -74,220 +74,120 @@
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_omap.h"
 #include "opt_com.h"
 #include "opt_cpuoptions.h"
 #include "opt_cputypes.h"
 #include "opt_multiprocessor.h"
-#include <machine/asm.h>
+#include <arm/asm.h>
 #include <arm/armreg.h>
 #include "assym.h"
 #include <arm/omap/omap2_obioreg.h>
 #include <evbarm/beagle/beagle.h>
-#ifdef MEMSIZE
+#ifdef CPU_CORTEXA9
-#define INIT_MEMSIZE	MEMSIZE
+#include <arm/cortex/a9tmr_reg.h>
 #else
 #define INIT_MEMSIZE	128
 #endif
-RCSID("$NetBSD: beagle_start.S,v 1.15 2013/06/16 17:57:21 matt Exp $")
+RCSID("$NetBSD: beagle_start.S,v 1.16 2013/06/17 04:39:48 matt Exp $")
 #undef VERBOSE_INIT_ARM
 #define VERBOSE_INIT_ARM
 #if defined(VERBOSE_INIT_ARM)
 #define	XPUTC(n)	mov r0, n; bl xputc
 #define COM_MULT	4
 #define XPUTC_COM	1
 #else
 #define	XPUTC(n)
 #endif
-#define Invalidate_I_cache(reg) \
+#define INIT_MEMSIZE	128
-	mcr	p15, 0, reg, c7, c5, 0	/* Invalidate Entire I cache */
+#define	TEMP_L1_TABLE	(0x80000000 + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
 /*
  * Kernel start routine for BEAGLEBOARD boards.
  * At this point, this code has been loaded into SDRAM
  * and the MMU is off
  */
 	.section .start,"ax",%progbits
 	.global	_C_LABEL(beagle_start)
 _C_LABEL(beagle_start):
 	/* Move into supervisor mode and disable IRQs/FIQs. */
 	cpsid	if, #PSR_SVC32_MODE
 	ldr	r4, .Luboot_args
 	stmia	r4, {r0-r3}
 	/*
-	 * Set up a preliminary mapping in the MMU to allow us to run
+	 * Save any arguments passed to us.
 	 * at KERNEL_BASE with caches on.
 	 */
-	/* Build page table from scratch */
+	movw	r4, #:lower16:uboot_args
-	ldr	r0, Ltemp_l1_table
+	movt	r4, #:upper16:uboot_args
-	mov	r1, r0			/* Save the page table address. */
+	stmia	r4, {r0-r3}
 	/* Zero the entire table so all virtual addresses are invalid. */
 	mov	r2, #L1_TABLE_SIZE	/* in bytes */
 	mov	r3, #0
 	mov	r4, r3
 	mov	r5, r3
 	mov	r6, r3
 	mov	r7, r3
 	mov	r8, r3
 	mov	r10, r3
 	mov	r11, r3
 :	stmia	r1!, {r3-r8,r10-r11}
 	stmia	r1!, {r3-r8,r10-r11}
 	stmia	r1!, {r3-r8,r10-r11}
 	stmia	r1!, {r3-r8,r10-r11}
 	subs	r2, r2, #(4 * 4 * 8)	/* bytes per loop */
 	bne	1b
 	/* Now create our entries per the mmu_init_table. */
 	l1table	.req r0
 	va	.req r1
 	pa	.req r2
 	n_sec	.req r3
 	attr	.req r4
 	itable	.req r5
 	l1sfrm	.req r6
 	adr	itable, mmu_init_table
 	ldr	l1sfrm, Ll1_s_frame
 	b	3f
 :	str	pa, [l1table, va, lsl #2]
 	add	va, va, #1
 	add	pa, pa, #(L1_S_SIZE)
 	adds	n_sec, n_sec, #-1
 	bhi	2b
 :	ldmia	itable!, {va,pa,n_sec,attr}
 	/* Convert va to l1 offset:	va = 4 * (va >> L1_S_SHIFT)	*/
 	lsr	va, va, #L1_S_SHIFT
 	/* Convert pa to l1 entry:	pa = (pa & L1_S_FRAME) | attr	*/
 	and	pa, pa, l1sfrm
 	orr	pa, pa, attr
 	cmp	n_sec, #0
 	bne	2b
 	.unreq	va
 	.unreq	pa
 	.unreq	n_sec
 	.unreq	attr
 	.unreq	itable
 	.unreq	l1table
 	.unreq	l1sfrm
 #ifdef CPU_CORTEXA9
 	/*
-	 * In theory, because the MMU is off, we shouldn't need all of this,
+	 * Turn on the SCU if we are on a Cortex-A9
 	 * but let's not take any chances and do a typical sequence to set
 	 * the Translation Table Base.
 	 */
 	bl	a9_start
-	Invalidate_I_cache(r0)
+	XPUTC(#67)
 #endif
         ldr     r2, Lctl_ID_dis		/* Disable I+D caches */
 	mrc	p15, 0, r1, c1, c0, 0	/*  "       "   "     */
 	and	r1, r1, r2		/*  "       "   "     */
 	mcr	p15, 0, r1, c1, c0, 0	/*  "       "   "     */
 	mcr	p15, 0, r0, c7, c10, 4	/* Drain the write buffers. */
 	mcr	p15, 0, r0, c2, c0, 0	/* Set Translation Table Base */
 	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate TLBs */
 	/* Set the Domain Access register.  Very important! */
         mov     r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
 	mcr	p15, 0, r0, c3, c0, 0
 	/*
-	 * Enable the MMU, etc.
+	 * Set up a preliminary mapping in the MMU to allow us to run
 	 * at KERNEL_BASE with caches on.
 	 */
-	mrc     p15, 0, r0, c1, c0, 0
+	movw	r0, #:lower16:TEMP_L1_TABLE
-	ldr     r1, Lcontrol_wax
+	movt	r0, #:upper16:TEMP_L1_TABLE
-	and	r0, r0, r1
+	adr	r1, .Lmmu_init_table
-	ldr     r1, Lcontrol_clr
+	bl	arm_boot_l1pt_init
 	mvn	r1, r1
-	and	r0, r0, r1
+	XPUTC(#68)
 	ldr     r1, Lcontrol_set
 	orr	r0, r0, r1
 	mcr     p15, 0, r0, c1, c0, 0
 	/*
-	 * Ensure that the coprocessor has finished turning on the MMU.
+	 * Turn on the MMU, Caches, etc.
 	 */
-	mrc	p15, 0, r0, c2, c0, 0	/* Read an arbitrary value. */
+	movw	r0, #:lower16:TEMP_L1_TABLE
-	mov	r0, r0			/* Stall until read completes. */
+	movt	r0, #:upper16:TEMP_L1_TABLE
 	bl	arm_cpuinit
 	XPUTC(#90)
 	/*
 	 * Jump to start in locore.S, which in turn will call initarm and main.
 	 */
 	b	start		/* Jump to start (flushes pipeline). */
 	nop
 	nop
 	nop
 	nop
 	/* NOTREACHED */
-.Luboot_args:
+#include <arm/cortex/a9_mpsubr.S>
 	.word	uboot_args
 Ll1_s_frame:
 	.word	L1_S_FRAME
 Ltemp_l1_table:
 	/* Put the temporary L1 translation table at the end of SDRAM. */
 	.word	0x80000000 + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE
 /*
  * Coprocessor register initialization values
  */
 # define CPU_AUXCTL_CZ	(1 << 6)		/* Restrict Cache Size */
 	/* bits to set in the Control Register */
 Lcontrol_set:
 	.word CPU_CONTROL_MMU_ENABLE  | \
 	      CPU_CONTROL_AFLT_ENABLE | \
 	      CPU_CONTROL_DC_ENABLE   | \
 	      CPU_CONTROL_IC_ENABLE   | \
 	      CPU_CONTROL_BPRD_ENABLE
 	/* bits to clear in the Control Register */
 Lcontrol_clr:
 	.word	0
 	/* bits to "write as existing" in the Control Register */
 Lcontrol_wax:
 	.word	(1 << 31) | \
 		(1 << 26) | \
 		(0x7ff << 14) | \
 		(0xff << 3)
 	/* bits to disable the caches */
 Lctl_ID_dis:
 	.word	~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
 	/* bit to restrict cache size */
 Lauxctl_CZ_restrict:
 	.word	CPU_AUXCTL_CZ
 /* We'll modify va and pa at run time so we can use relocatable addresses. */
 #define MMU_INIT(va,pa,n_sec,attr) \
 	.word	va					    ; \
 	.word	pa					    ; \
 	.word	n_sec					    ; \
 	.word	attr					    ;
-mmu_init_table:
+.Lmmu_init_table:
-	/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */
+	/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
 	MMU_INIT(KERNEL_BASE, KERNEL_BASE,
 		(INIT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
-		L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
+		L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C | L1_S_V6_S)
 	/* Map first 1MB of L4 CORE (so console will work) */
 	MMU_INIT(OMAP_L4_CORE_VBASE, OMAP_L4_CORE_BASE,
 		(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
 		L1_S_PROTO | L1_S_APv7_KRW)
 #if OMAP_L4_CORE_BASE <= CONSADDR \
 	&& CONSADDR < OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE
 	/* Map first 1MB of L4 CORE 1:1 (so console will work) */
 	MMU_INIT(OMAP_L4_CORE_BASE, OMAP_L4_CORE_BASE,
 		(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
 		L1_S_PROTO | L1_S_APv7_KRW)
 #endif