Mon Jun 17 05:13:07 2013 UTC ()
KASSERT -> KASSERTMSG


(matt)
diff -r1.11 -r1.12 src/sys/arch/arm/cortex/pl310.c
cvs diff -r1.11 -r1.12 src/sys/arch/arm/cortex/pl310.c (expand / switch to unified diff)

--- src/sys/arch/arm/cortex/pl310.c 2013/02/13 23:10:58 1.11
+++ src/sys/arch/arm/cortex/pl310.c 2013/06/17 05:13:07 1.12
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pl310.c,v 1.11 2013/02/13 23:10:58 matt Exp $ */ 1/* $NetBSD: pl310.c,v 1.12 2013/06/17 05:13:07 matt Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas 8 * by Matt Thomas
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.11 2013/02/13 23:10:58 matt Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.12 2013/06/17 05:13:07 matt Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/cpu.h> 37#include <sys/cpu.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/atomic.h> 39#include <sys/atomic.h>
40 40
41#include <arm/cortex/mpcore_var.h> 41#include <arm/cortex/mpcore_var.h>
42#include <arm/cortex/pl310_reg.h> 42#include <arm/cortex/pl310_reg.h>
43#include <arm/cortex/pl310_var.h> 43#include <arm/cortex/pl310_var.h>
44 44
45static int arml2cc_match(device_t, cfdata_t, void *); 45static int arml2cc_match(device_t, cfdata_t, void *);
46static void arml2cc_attach(device_t, device_t, void *); 46static void arml2cc_attach(device_t, device_t, void *);
@@ -181,27 +181,29 @@ arml2cc_attach(device_t parent, device_t @@ -181,27 +181,29 @@ arml2cc_attach(device_t parent, device_t
181 } 181 }
182 } else if ((device_cfdata(self)->cf_flags & 1) == 0) { 182 } else if ((device_cfdata(self)->cf_flags & 1) == 0) {
183 if (!enabled_p) { 183 if (!enabled_p) {
184 arml2cc_enable(sc); 184 arml2cc_enable(sc);
185 aprint_normal_dev(self, "cache %s\n", 185 aprint_normal_dev(self, "cache %s\n",
186 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 186 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled");
187 } 187 }
188 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 188 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range;
189 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 189 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range;
190 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 190 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range;
191 sc->sc_enabled = true; 191 sc->sc_enabled = true;
192 } 192 }
193 193
194 KASSERT(arm_pcache.dcache_line_size == arm_scache.dcache_line_size); 194 KASSERTMSG(arm_pcache.dcache_line_size == arm_scache.dcache_line_size,
 195 "pcache %u scache %u",
 196 arm_pcache.dcache_line_size, arm_scache.dcache_line_size);
195} 197}
196 198
197static inline void 199static inline void
198arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val, 200arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val,
199 bool wait) 201 bool wait)
200{ 202{
201 arml2cc_write_4(sc, off, val); 203 arml2cc_write_4(sc, off, val);
202 if (wait) { 204 if (wait) {
203 while (arml2cc_read_4(sc, off) & 1) { 205 while (arml2cc_read_4(sc, off) & 1) {
204 /* spin */ 206 /* spin */
205 } 207 }
206 } 208 }
207} 209}