Tue Jun 18 15:01:49 2013 UTC ()
Omap4 changes


(matt)
diff -r1.1 -r1.2 src/sys/arch/arm/omap/omap3_uhhreg.h
cvs diff -r1.1 -r1.2 src/sys/arch/arm/omap/Attic/omap3_uhhreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/omap/Attic/omap3_uhhreg.h 2012/12/12 00:33:45 1.1
+++ src/sys/arch/arm/omap/Attic/omap3_uhhreg.h 2013/06/18 15:01:49 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: omap3_uhhreg.h,v 1.1 2012/12/12 00:33:45 matt Exp $ */ 1/* $NetBSD: omap3_uhhreg.h,v 1.2 2013/06/18 15:01:49 matt Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products 12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission. 13 * derived from this software without specific prior written permission.
14 * 14 *
@@ -43,36 +43,38 @@ @@ -43,36 +43,38 @@
43#define UHH_SYSCONFIG_SOFTRESET 0x00000002 43#define UHH_SYSCONFIG_SOFTRESET 0x00000002
44#define UHH_SYSCONFIG_AUTOIDLE 0x00000001 44#define UHH_SYSCONFIG_AUTOIDLE 0x00000001
45 45
46#define UHH_SYSSTATUS 0x14 46#define UHH_SYSSTATUS 0x14
47#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004 47#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
48#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002 48#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
49#define UHH_SYSSTATUS_RESETDONE 0x00000001 49#define UHH_SYSSTATUS_RESETDONE 0x00000001
50#define UHH_SYSSTATUS_RESETDONE_ALL \ 50#define UHH_SYSSTATUS_RESETDONE_ALL \
51 (UHH_SYSSTATUS_EHCI_RESETDONE | \ 51 (UHH_SYSSTATUS_EHCI_RESETDONE | \
52 UHH_SYSSTATUS_OHCI_RESETDONE | \ 52 UHH_SYSSTATUS_OHCI_RESETDONE | \
53 UHH_SYSSTATUS_RESETDONE) 53 UHH_SYSSTATUS_RESETDONE)
54 54
55#define UHH_HOSTCONFIG 0x40 55#define UHH_HOSTCONFIG 0x40
56#define UHH_HOSTCONFIG_APP_START_CLK 0x80000000 56#define UHH_HOSTCONFIG_APP_START_CLK __BIT(31)
57#define UHH_HOSTCONFIG_P3_ULPI_BYPASS 0x00001000 57#define UHH_HOSTCONFIG_P2_MODE __BITS(19,18)
58#define UHH_HOSTCONFIG_P2_ULPI_BYPASS 0x00000800 58#define UHH_HOSTCONFIG_P1_MODE __BITS(17,16)
59#define UHH_HOSTCONFIG_P3_CONNECT_STATUS 0x00000400 59#define UHH_HOSTCONFIG_P3_ULPI_BYPASS __BIT(12)
60#define UHH_HOSTCONFIG_P2_CONNECT_STATUS 0x00000200 60#define UHH_HOSTCONFIG_P2_ULPI_BYPASS __BIT(11)
61#define UHH_HOSTCONFIG_P1_CONNECT_STATUS 0x00000100 61#define UHH_HOSTCONFIG_P3_CONNECT_STATUS __BIT(10)
62#define UHH_HOSTCONFIG_ENA_INCR_ALIGN 0x00000020 62#define UHH_HOSTCONFIG_P2_CONNECT_STATUS __BIT(9)
63#define UHH_HOSTCONFIG_ENA_INCR16 0x00000010 63#define UHH_HOSTCONFIG_P1_CONNECT_STATUS __BIT(8)
64#define UHH_HOSTCONFIG_ENA_INCR8 0x00000008 64#define UHH_HOSTCONFIG_ENA_INCR_ALIGN __BIT(5)
65#define UHH_HOSTCONFIG_ENA_INCR4 0x00000004 65#define UHH_HOSTCONFIG_ENA_INCR16 __BIT(4)
66#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN 0x00000002 66#define UHH_HOSTCONFIG_ENA_INCR8 __BIT(3)
67#define UHH_HOSTCONFIG_P1_ULPI_BYPASS 0x00000001 67#define UHH_HOSTCONFIG_ENA_INCR4 __BIT(2)
 68#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN __BIT(1)
 69#define UHH_HOSTCONFIG_P1_ULPI_BYPASS __BIT(0)
68 70
69#define UHH_DEBUG_CSR 0x44 71#define UHH_DEBUG_CSR 0x44
70#define UHH_DEBUG_CSR_OHCI_CCS_3 0x00080000 72#define UHH_DEBUG_CSR_OHCI_CCS_3 0x00080000
71#define UHH_DEBUG_CSR_OHCI_CCS_2 0x00040000 73#define UHH_DEBUG_CSR_OHCI_CCS_2 0x00040000
72#define UHH_DEBUG_CSR_OHCI_CCS_1 0x00020000 74#define UHH_DEBUG_CSR_OHCI_CCS_1 0x00020000
73#define UHH_DEBUG_CSR_OHCI_GLOBALSUSPEND 0x00010000 75#define UHH_DEBUG_CSR_OHCI_GLOBALSUSPEND 0x00010000
74#define UHH_DEBUG_CSR_OHCI_CNTSEL 0x00000080 76#define UHH_DEBUG_CSR_OHCI_CNTSEL 0x00000080
75#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE 0x00000040 77#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE 0x00000040
76#define UHH_DEBUG_CSR_EHCI_FLADJ 0x0000003f 78#define UHH_DEBUG_CSR_EHCI_FLADJ 0x0000003f
77 79
78#endif /* !_OMAP3_UHHREG_H */ 80#endif /* !_OMAP3_UHHREG_H */