 @@ -1,14 +1,14 @@
-/* $NetBSD: omap3_ehci.c,v 1.8 2013/06/16 17:47:54 matt Exp $ */
+/* $NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $ */
 /*-
  * Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
 @@ -16,27 +16,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.8 2013/06/16 17:47:54 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
 #include "locators.h"
 #include "opt_omap.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <sys/gpio.h>
 #include <machine/intr.h>
 @@ -98,61 +98,73 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c
 /*  USBHOST_CM registers */
 #define CM_FCLKEN_USBHOST	0x00
 #define  EN_USBHOST1		 1	/* USB HOST 48 MHz clock enable */
 #define  EN_USBHOST2		 2	/* USB HOST 120 MHz clock enable */
 #define CM_ICLKEN_USBHOST	0x10
 #define  EN_USBHOST		 1	/* USB HOST clock enable */
 #define CM_IDLEST_USBHOST	0x20
 #define CM_AUTOIDLE_USBHOST	0x30
 #define CM_SLEEPDEP_USBHOST	0x44
 #define CM_CLKSTCTRL_USBHOST	0x48
 #define CM_CLKSTST_USBHOST	0x4c
 /* USBTLL module */
 #ifdef OMAP_3XXX
 #define	USBTLL_BASE		0x48062000
 #elif defined(OMAP4)
 #define	USBTLL_BASE		0x4a062000
 #endif
 #define	USBTLL_SIZE		0x1000
 /* HS USB HOST module */
 #ifdef OMAP_3XXX
 #define	UHH_BASE		0x48064000
 #elif defined(OMAP4)
 #define	UHH_BASE		0x4a064000
 #endif
 #define	UHH_SIZE		0x1000
 enum omap3_ehci_port_mode {
 	OMAP3_EHCI_PORT_MODE_NONE,
 	OMAP3_EHCI_PORT_MODE_PHY,
 	OMAP3_EHCI_PORT_MODE_TLL,
 };
 struct omap3_ehci_softc {
 	ehci_softc_t	sc;
 	void		*sc_ih;
 	bus_space_handle_t sc_ioh_usbtll;
 	bus_size_t	sc_usbtll_size;
 	bus_space_handle_t sc_ioh_uhh;
 	bus_size_t	sc_uhh_size;
 	uint16_t	sc_nports;
 	bool		sc_phy_reset;
 	struct {
 		enum omap3_ehci_port_mode mode;
 		int gpio;
 		bool value;
 	} sc_portconfig[3];
 	struct {
 		uint16_t m, n, m2;
 	} sc_dpll5;
 };
-static void	dpll5_init(struct omap3_ehci_softc *);
+#ifdef OMAP_3XXX
-static void	usbhost_init(struct omap3_ehci_softc *, int);
+static void	omap3_dpll5_init(struct omap3_ehci_softc *);
 static void	omap3_usbhost_init(struct omap3_ehci_softc *, int);
 #endif
 static void	usbtll_reset(struct omap3_ehci_softc *);
 static void	usbtll_power(struct omap3_ehci_softc *, bool);
 static void	usbtll_init(struct omap3_ehci_softc *, int);
 static void	uhh_power(struct omap3_ehci_softc *, bool);
 static void	uhh_portconfig(struct omap3_ehci_softc *);
 #define	USBTLL_READ4(sc, reg)		bus_space_read_4((sc)->sc.iot, (sc)->sc_ioh_usbtll, (reg))
 #define	USBTLL_WRITE4(sc, reg, v)	bus_space_write_4((sc)->sc.iot, (sc)->sc_ioh_usbtll, (reg), (v))
 #define	UHH_READ4(sc, reg)	bus_space_read_4((sc)->sc.iot, (sc)->sc_ioh_uhh, (reg))
 #define	UHH_WRITE4(sc, reg, v)	bus_space_write_4((sc)->sc.iot, (sc)->sc_ioh_uhh, (reg), (v))
 /* Table 23-55 "EHCI Registers Mapping Summary" */
 #define EHCI_INSNREG00		0x90
 @@ -198,158 +210,175 @@ omap3_ehci_phy_reset(struct omap3_ehci_s
 static void
 omap3_ehci_find_companions(struct omap3_ehci_softc *sc)
+{
 	device_t dv;
 	deviter_t di;
 	sc->sc.sc_ncomp = 0;
 	for (dv = deviter_first(&di, DEVITER_F_ROOT_FIRST);
 	     dv != NULL;
 	     dv = deviter_next(&di)) {
 		if (device_is_a(dv, "ohci") &&
 		    device_parent(dv) == device_parent(sc->sc.sc_dev)) {
-			printf("  adding companion '%s'\n", device_xname(dv));
+#ifdef OMAP3_EHCI_DEBUG
 			aprint_normal("  adding companion '%s'\n", device_xname(dv));
 #endif
 			sc->sc.sc_comps[sc->sc.sc_ncomp++] = dv;
+		}
+	}
 	deviter_release(&di);
+}
 static void
 omap3_ehci_attach1(device_t self)
+{
 	struct omap3_ehci_softc *sc = device_private(self);
 	usbd_status err;
 	int i;
-	for (i = 0; sc->sc_phy_reset && i < 3; i++) {
+	for (u_int i = 0; sc->sc_phy_reset && i < sc->sc_nports; i++) {
 		if (sc->sc_portconfig[i].gpio != -1) {
 			if (!omap2_gpio_has_pin(sc->sc_portconfig[i].gpio)) {
 				aprint_error_dev(self, "WARNING: "
 				    "gpio pin %d not available\n",
 				    sc->sc_portconfig[i].gpio);
 				continue;
+			}
 			omap2_gpio_ctl(sc->sc_portconfig[i].gpio, GPIO_PIN_OUTPUT);
-			omap2_gpio_write(sc->sc_portconfig[i].gpio, 0);
+			omap2_gpio_write(sc->sc_portconfig[i].gpio,
 			    !sc->sc_portconfig[i].value); // off
 			delay(10);
+		}
+	}
 	usbtll_power(sc, true);
 	usbtll_init(sc, 3);
 	uhh_power(sc, true);
 	uhh_portconfig(sc);
-	for (i = 0; i < 3; i++) {
+	for (u_int i = 0; i < sc->sc_nports; i++) {
 		if (sc->sc_portconfig[i].mode == OMAP3_EHCI_PORT_MODE_PHY) {
 			omap3_ehci_phy_reset(sc, i);
+		}
+	}
 	delay(10);
-	for (i = 0; sc->sc_phy_reset && i < 3; i++) {
+	for (u_int i = 0; sc->sc_phy_reset && i < sc->sc_nports; i++) {
 		if (sc->sc_portconfig[i].gpio != -1) {
 			if (!omap2_gpio_has_pin(sc->sc_portconfig[i].gpio))
 				continue;
 			omap2_gpio_ctl(sc->sc_portconfig[i].gpio, GPIO_PIN_OUTPUT);
-			omap2_gpio_write(sc->sc_portconfig[i].gpio, 1);
+			omap2_gpio_write(sc->sc_portconfig[i].gpio,
 			    sc->sc_portconfig[i].value);
 			delay(10);
+		}
+	}
 	omap3_ehci_find_companions(sc);
 	err = ehci_init(&sc->sc);
 	if (err != USBD_NORMAL_COMPLETION) {
 		aprint_error_dev(self, "init failed, error = %d\n", err);
 		return;
+	}
 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
+}
 static int
 omap3_ehci_match(device_t parent, cfdata_t match, void *opaque)
+{
 #ifdef OMAP3
 	struct obio_attach_args *obio = opaque;
 #endif
-#if defined(OMAP3) && !defined(OMAP4)
+#ifdef OMAP_3XXX
 	if (obio->obio_addr == EHCI1_BASE_OMAP3)
 		return 1;
 #endif
 #ifdef OMAP4
 	if (obio->obio_addr == EHCI1_BASE_OMAP4)
 		return 1;
 #endif
 	return 0;
+}
 static enum omap3_ehci_port_mode
 omap3_ehci_get_port_mode(prop_dictionary_t prop, const char *key)
+{
 	const char *s = NULL;
 	enum omap3_ehci_port_mode mode = OMAP3_EHCI_PORT_MODE_NONE;
 	if (prop_dictionary_get_cstring_nocopy(prop, key, &s) && s != NULL) {
 		if (strcmp(s, "phy") == 0) {
 			mode = OMAP3_EHCI_PORT_MODE_PHY;
 #ifdef OMAP_3XXX
 		} else if (strcmp(s, "tll") == 0) {
 			mode = OMAP3_EHCI_PORT_MODE_TLL;
 #endif
+		}
+	}
 	return mode;
+}
 static int
 omap3_ehci_get_port_gpio(prop_dictionary_t prop, const char *key)
+{
 	int16_t gpio;
 	if (prop_dictionary_get_int16(prop, key, &gpio) == false)
 		gpio = -1;
 	return gpio;
+}
 static void
 omap3_ehci_parse_properties(struct omap3_ehci_softc *sc, prop_dictionary_t prop)
+{
 	prop_dictionary_get_uint16(prop, "nports", &sc->sc_nports);
 	prop_dictionary_get_bool(prop, "phy-reset", &sc->sc_phy_reset);
 	sc->sc_portconfig[0].mode = omap3_ehci_get_port_mode(prop, "port0-mode");
 	sc->sc_portconfig[0].gpio = omap3_ehci_get_port_gpio(prop, "port0-gpio");
-	sc->sc_portconfig[1].mode = omap3_ehci_get_port_mode(prop, "port1-mode");
+	prop_dictionary_get_bool(prop, "port0-gpioval", &sc->sc_portconfig[0].value);
-	sc->sc_portconfig[1].gpio = omap3_ehci_get_port_gpio(prop, "port1-gpio");
+	if (sc->sc_nports > 1) {
-	sc->sc_portconfig[2].mode = omap3_ehci_get_port_mode(prop, "port2-mode");
+		sc->sc_portconfig[1].mode = omap3_ehci_get_port_mode(prop, "port1-mode");
-	sc->sc_portconfig[2].gpio = omap3_ehci_get_port_gpio(prop, "port2-gpio");
+		sc->sc_portconfig[1].gpio = omap3_ehci_get_port_gpio(prop, "port1-gpio");
 		prop_dictionary_get_bool(prop, "port1-gpioval", &sc->sc_portconfig[1].value);
+	}
 	if (sc->sc_nports > 2) {
 		sc->sc_portconfig[2].mode = omap3_ehci_get_port_mode(prop, "port2-mode");
 		sc->sc_portconfig[2].gpio = omap3_ehci_get_port_gpio(prop, "port2-gpio");
 		prop_dictionary_get_bool(prop, "port2-gpioval", &sc->sc_portconfig[2].value);
+	}
 #ifdef OMAP_3XXX
 	prop_dictionary_get_uint16(prop, "dpll5-m", &sc->sc_dpll5.m);
 	prop_dictionary_get_uint16(prop, "dpll5-n", &sc->sc_dpll5.n);
 	prop_dictionary_get_uint16(prop, "dpll5-m2", &sc->sc_dpll5.m2);
 #endif
 #ifdef OMAP3_EHCI_DEBUG
 	printf("  GPIO PHY reset: %d\n", sc->sc_phy_reset);
 	printf("  Port #0: mode %d, gpio %d\n", sc->sc_portconfig[0].mode, sc->sc_portconfig[0].gpio);
 	printf("  Port #1: mode %d, gpio %d\n", sc->sc_portconfig[1].mode, sc->sc_portconfig[1].gpio);
 	printf("  Port #2: mode %d, gpio %d\n", sc->sc_portconfig[2].mode, sc->sc_portconfig[2].gpio);
 #ifdef OMAP_3XXX
 	printf("  DPLL5: m=%d n=%d m2=%d\n", sc->sc_dpll5.m, sc->sc_dpll5.n, sc->sc_dpll5.m2);
 #endif
 #endif
+}
 static void
 omap3_ehci_attach(device_t parent, device_t self, void *opaque)
+{
 	struct omap3_ehci_softc *sc = device_private(self);
 	struct obio_attach_args *obio = opaque;
 	int rv;
 	sc->sc.sc_dev = self;
 	sc->sc.sc_bus.hci_private = sc;
 	aprint_naive("\n");
 @@ -371,29 +400,31 @@ omap3_ehci_attach(device_t parent, devic
+	}
 	sc->sc_usbtll_size = USBTLL_SIZE;
 	rv = bus_space_map(obio->obio_iot, UHH_BASE, UHH_SIZE, 0, &sc->sc_ioh_uhh);
 	if (rv) {
 		aprint_error_dev(self, "couldn't map uhh memory space\n");
 		return;
+	}
 	sc->sc_uhh_size = UHH_SIZE;
 	sc->sc.sc_bus.dmatag = obio->obio_dmat;
 	sc->sc.sc_bus.usbrev = USBREV_2_0;
 	sc->sc.sc_id_vendor = PCI_VENDOR_TI;
 	strlcpy(sc->sc.sc_vendor, "OMAP3", sizeof(sc->sc.sc_vendor));
-	dpll5_init(sc);
+#ifdef OMAP_3XXX
 	omap3_dpll5_init(sc);
-	usbhost_init(sc, 1);
+	omap3_usbhost_init(sc, 1);
 #endif /* OMAP_3XXX */
 	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
 	//EOWRITE4(&sc->sc, EHCI_INSNREG04, 1 << 5);
 	sc->sc_ih = intr_establish(obio->obio_intr, IPL_USB, IST_LEVEL, ehci_intr, &sc->sc);
 	//config_interrupts(self, omap3_ehci_attach1);
 	omap3_ehci_attach1(self);
+}
 static int
 omap3_ehci_detach(device_t self, int flags)
 @@ -423,43 +454,42 @@ omap3_ehci_detach(device_t self, int fla
 	if (sc->sc_uhh_size) {
 		bus_space_unmap(sc->sc.iot, sc->sc_ioh_uhh, sc->sc_uhh_size);
 		sc->sc_uhh_size = 0;
+	}
 	if (sc->sc.sc_size) {
 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
 		sc->sc.sc_size = 0;
+	}
 	return 0;
+}
 #ifdef OMAP_3XXX
 static void
-dpll5_init(struct omap3_ehci_softc *sc)
+omap3_dpll5_init(struct omap3_ehci_softc *sc)
+{
 	bus_space_tag_t iot = sc->sc.iot;
 	bus_space_handle_t ioh;
 	int err;
 	if (sc->sc_dpll5.m == 0 || sc->sc_dpll5.n == 0 || sc->sc_dpll5.m2 == 0)
 		return;
 	err = bus_space_map(iot, CCR_CM_BASE, CCR_CM_SIZE, 0, &ioh);
 	if (err)
                 panic("%s: cannot map CCR_CM_BASE at %#x, error %d\n",
                         __func__, CCR_CM_BASE, err);
 #if defined(OMAP_3530) || defined(OMAP_3540)
 	/* set the multiplier and divider values for the desired CLKOUT freq */
 	uint32_t m = sc->sc_dpll5.m;
 	uint32_t n = sc->sc_dpll5.n;
 	/* set the corresponding output dividers */
 	uint32_t m2 = sc->sc_dpll5.m2;
 	KASSERTMSG(479900000 <= 2 * m * (omap_sys_clk / ((n + 1) * m2)),
 	    "m=%u n=%u m2=%u freq=%u",
 	    m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
 	KASSERTMSG(2 * m * (omap_sys_clk / ((n + 1) * m2)) <= 480100000,
 	    "m=%u n=%u m2=%u freq=%u",
 	    m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
 @@ -469,33 +499,32 @@ dpll5_init(struct omap3_ehci_softc *sc)
 	 * factor N are programmed so that the new value is taken into
 	 * account during current DPLL relock.
 	 */
 	bus_space_write_4(iot, ioh, CM_CLKEN2_PLL, (0x4 << 4) | 0x7);
 	bus_space_write_4(iot, ioh, CM_CLKSEL4_PLL, (m << 8) | n);
 	bus_space_write_4(iot, ioh, CM_CLKSEL5_PLL, m2);
 	/*
 	 * Put DPLL5 into low power stop mode when the 120MHz clock
 	 * is not required (restarted automatically)
 	 */
 	bus_space_write_4(iot, ioh, CM_AUTOIDLE2_PLL, AUTO_PERIPH2_DPLL);
 #endif /* OMAP_3540 || OMAP_3530 */
 	bus_space_unmap(iot, ioh, CCR_CM_SIZE);
+}
 static void
-usbhost_init(struct omap3_ehci_softc *sc, int enable)
+omap3_usbhost_init(struct omap3_ehci_softc *sc, int enable)
+{
 	bus_space_tag_t iot = sc->sc.iot;
         bus_space_handle_t ioh;
         uint32_t r;
         int err;
 	/*
 	 * USBHOST
 	 */
         err = bus_space_map(iot, USBHOST_CM_BASE, USBHOST_CM_SIZE, 0, &ioh);
         if (err)
                 panic("%s: cannot map USBHOST_CM_BASE at %#x, error %d\n",
                         __func__, USBHOST_CM_BASE, err);
 @@ -546,26 +575,27 @@ usbhost_init(struct omap3_ehci_softc *sc
 	else
 		r |= AUTO_USBTLL;
 	bus_space_write_4(iot, ioh, CM_AUTOIDLE3_CORE, r);
 	bus_space_unmap(iot, ioh, CORE_CM_SIZE);
 	delay(10000);
 #undef USBHOST_CM_SIZE
 #undef USBHOST_CM_BASE
 #undef CORE_CM_SIZE
 #undef CORE_CM_BASE
+}
 #endif /* OMAP_3XXX */
 static void
 usbtll_reset(struct omap3_ehci_softc *sc)
+{
 	uint32_t v;
 	int retry = 5000;
 	USBTLL_WRITE4(sc, USBTLL_SYSCONFIG, USBTLL_SYSCONFIG_SOFTRESET);
 	do {
 		v = USBTLL_READ4(sc, USBTLL_SYSSTATUS);
 		if (v & USBTLL_SYSSTATUS_RESETDONE)
 			break;
 		delay(10);
 @@ -584,36 +614,35 @@ usbtll_power(struct omap3_ehci_softc *sc
 	if (on) {
 		v = USBTLL_SYSCONFIG_ENAWAKEUP |
 		    USBTLL_SYSCONFIG_AUTOIDLE |
 		    USBTLL_SYSCONFIG_SIDLEMODE |
 		    USBTLL_SYSCONFIG_CLOCKACTIVITY;
 		USBTLL_WRITE4(sc, USBTLL_SYSCONFIG, v);
+	}
+}
 static void
 usbtll_init(struct omap3_ehci_softc *sc, int chmask)
+{
 	int i;
 	uint32_t v;
 	v = USBTLL_READ4(sc, USBTLL_SHARED_CONF);
 	v |= (USBTLL_SHARED_CONF_FCLK_IS_ON | (1 << 2)/*divration*/);
 	v &= ~USBTLL_SHARED_CONF_USB_90D_DDR_EN;
 	v &= ~USBTLL_SHARED_CONF_USB_180D_SDR_EN;
 	USBTLL_WRITE4(sc, USBTLL_SHARED_CONF, v);
-	for (i = 0; i < 3; i++) {
+	for (u_int i = 0; i < sc->sc_nports; i++) {
 		if (sc->sc_portconfig[i].mode == OMAP3_EHCI_PORT_MODE_NONE)
 			continue;
 		v = USBTLL_READ4(sc, USBTLL_CHANNEL_CONF(i));
 		v &= ~(USBTLL_CHANNEL_CONF_ULPINOBITSTUFF|
 		       USBTLL_CHANNEL_CONF_ULPIAUTOIDLE|
 		       USBTLL_CHANNEL_CONF_ULPIDDRMODE);
 		//v |= USBTLL_CHANNEL_CONF_FSLSMODE;
 		v |= USBTLL_CHANNEL_CONF_CHANEN;
 		USBTLL_WRITE4(sc, USBTLL_CHANNEL_CONF(i), v);
+	}
+}
 static void
 @@ -653,44 +682,44 @@ static void
 uhh_portconfig(struct omap3_ehci_softc *sc)
+{
 	uint32_t v;
 	v = UHH_READ4(sc, UHH_HOSTCONFIG);
 	v |= UHH_HOSTCONFIG_ENA_INCR16;
 	v |= UHH_HOSTCONFIG_ENA_INCR8;
 	v |= UHH_HOSTCONFIG_ENA_INCR4;
 	v |= UHH_HOSTCONFIG_APP_START_CLK;
 	v &= ~UHH_HOSTCONFIG_ENA_INCR_ALIGN;
 	if (sc->sc_portconfig[0].mode == OMAP3_EHCI_PORT_MODE_NONE)
 		v &= ~UHH_HOSTCONFIG_P1_CONNECT_STATUS;
-	if (sc->sc_portconfig[1].mode == OMAP3_EHCI_PORT_MODE_NONE)
+	if (sc->sc_nports > 1
 	    && sc->sc_portconfig[1].mode == OMAP3_EHCI_PORT_MODE_NONE)
 		v &= ~UHH_HOSTCONFIG_P2_CONNECT_STATUS;
-	if (sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_NONE)
+	if (sc->sc_nports > 2
 	    && sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_NONE)
 		v &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
-	if (sc->sc_portconfig[0].mode == OMAP3_EHCI_PORT_MODE_PHY)
+	v &= ~(UHH_HOSTCONFIG_P1_ULPI_BYPASS |UHH_HOSTCONFIG_P2_ULPI_BYPASS
-		v &= ~UHH_HOSTCONFIG_P1_ULPI_BYPASS;
+	    |UHH_HOSTCONFIG_P2_ULPI_BYPASS);
-	else
+	if (sc->sc_portconfig[0].mode != OMAP3_EHCI_PORT_MODE_PHY)
 		v |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
-	if (sc->sc_portconfig[1].mode == OMAP3_EHCI_PORT_MODE_PHY)
+	if (sc->sc_nports > 1
-		v &= ~UHH_HOSTCONFIG_P2_ULPI_BYPASS;
+	    && sc->sc_portconfig[1].mode != OMAP3_EHCI_PORT_MODE_PHY)
 	else
 		v |= UHH_HOSTCONFIG_P2_ULPI_BYPASS;
-	if (sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_PHY)
+	if (sc->sc_nports > 2
-		v &= ~UHH_HOSTCONFIG_P3_ULPI_BYPASS;
+	    && sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_PHY)
 	else
 		v |= UHH_HOSTCONFIG_P3_ULPI_BYPASS;
 	UHH_WRITE4(sc, UHH_HOSTCONFIG, v);
+}
 CFATTACH_DECL2_NEW(omap3_ehci, sizeof(struct omap3_ehci_softc),
     omap3_ehci_match,
     omap3_ehci_attach,
     omap3_ehci_detach,
     ehci_activate,
     NULL,
     ehci_childdet
 );