Tue Jun 18 15:27:05 2013 UTC ()
Only set CPU_CONTROL_VECRELOC if ARM_HAS_VBAR is not defined.


(matt)
diff -r1.122 -r1.123 src/sys/arch/arm/arm/cpufunc.c
cvs diff -r1.122 -r1.123 src/sys/arch/arm/arm/cpufunc.c (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc.c 2013/06/12 01:16:48 1.122
+++ src/sys/arch/arm/arm/cpufunc.c 2013/06/18 15:27:05 1.123
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc.c,v 1.122 2013/06/12 01:16:48 matt Exp $ */ 1/* $NetBSD: cpufunc.c,v 1.123 2013/06/18 15:27:05 matt Exp $ */
2 2
3/* 3/*
4 * arm7tdmi support code Copyright (c) 2001 John Fremlin 4 * arm7tdmi support code Copyright (c) 2001 John Fremlin
5 * arm8 support code Copyright (c) 1997 ARM Limited 5 * arm8 support code Copyright (c) 1997 ARM Limited
6 * arm8 support code Copyright (c) 1997 Causality Limited 6 * arm8 support code Copyright (c) 1997 Causality Limited
7 * arm9 support code Copyright (C) 2001 ARM Ltd 7 * arm9 support code Copyright (C) 2001 ARM Ltd
8 * arm11 support code Copyright (c) 2007 Microsoft 8 * arm11 support code Copyright (c) 2007 Microsoft
9 * cortexa8 support code Copyright (c) 2008 3am Software Foundry 9 * cortexa8 support code Copyright (c) 2008 3am Software Foundry
10 * cortexa8 improvements Copyright (c) Goeran Weinholt 10 * cortexa8 improvements Copyright (c) Goeran Weinholt
11 * Copyright (c) 1997 Mark Brinicombe. 11 * Copyright (c) 1997 Mark Brinicombe.
12 * Copyright (c) 1997 Causality Limited 12 * Copyright (c) 1997 Causality Limited
13 * All rights reserved. 13 * All rights reserved.
14 * 14 *
@@ -39,27 +39,27 @@ @@ -39,27 +39,27 @@
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE. 40 * SUCH DAMAGE.
41 * 41 *
42 * RiscBSD kernel project 42 * RiscBSD kernel project
43 * 43 *
44 * cpufuncs.c 44 * cpufuncs.c
45 * 45 *
46 * C functions for supporting CPU / MMU / TLB specific operations. 46 * C functions for supporting CPU / MMU / TLB specific operations.
47 * 47 *
48 * Created : 30/01/97 48 * Created : 30/01/97
49 */ 49 */
50 50
51#include <sys/cdefs.h> 51#include <sys/cdefs.h>
52__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.122 2013/06/12 01:16:48 matt Exp $"); 52__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.123 2013/06/18 15:27:05 matt Exp $");
53 53
54#include "opt_compat_netbsd.h" 54#include "opt_compat_netbsd.h"
55#include "opt_cpuoptions.h" 55#include "opt_cpuoptions.h"
56#include "opt_perfctrs.h" 56#include "opt_perfctrs.h"
57 57
58#include <sys/types.h> 58#include <sys/types.h>
59#include <sys/param.h> 59#include <sys/param.h>
60#include <sys/pmc.h> 60#include <sys/pmc.h>
61#include <sys/systm.h> 61#include <sys/systm.h>
62#include <machine/cpu.h> 62#include <machine/cpu.h>
63#include <machine/bootconfig.h> 63#include <machine/bootconfig.h>
64#include <arch/arm/arm/disassem.h> 64#include <arch/arm/arm/disassem.h>
65 65
@@ -2784,28 +2784,30 @@ arm9_setup(char *args) @@ -2784,28 +2784,30 @@ arm9_setup(char *args)
2784 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC 2784 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC
2785 | CPU_CONTROL_ROUNDROBIN; 2785 | CPU_CONTROL_ROUNDROBIN;
2786 2786
2787#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 2787#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
2788 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 2788 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
2789#endif 2789#endif
2790 2790
2791 cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl); 2791 cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl);
2792 2792
2793#ifdef __ARMEB__ 2793#ifdef __ARMEB__
2794 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 2794 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
2795#endif 2795#endif
2796 2796
 2797#ifndef ARM_HAS_VBAR
2797 if (vector_page == ARM_VECTORS_HIGH) 2798 if (vector_page == ARM_VECTORS_HIGH)
2798 cpuctrl |= CPU_CONTROL_VECRELOC; 2799 cpuctrl |= CPU_CONTROL_VECRELOC;
 2800#endif
2799 2801
2800 /* Clear out the cache */ 2802 /* Clear out the cache */
2801 cpu_idcache_wbinv_all(); 2803 cpu_idcache_wbinv_all();
2802 2804
2803 /* Set the control register */ 2805 /* Set the control register */
2804 curcpu()->ci_ctrl = cpuctrl; 2806 curcpu()->ci_ctrl = cpuctrl;
2805 cpu_control(cpuctrlmask, cpuctrl); 2807 cpu_control(cpuctrlmask, cpuctrl);
2806 2808
2807} 2809}
2808#endif /* CPU_ARM9 */ 2810#endif /* CPU_ARM9 */
2809 2811
2810#if defined(CPU_ARM9E) || defined(CPU_ARM10) 2812#if defined(CPU_ARM9E) || defined(CPU_ARM10)
2811struct cpu_option arm10_options[] = { 2813struct cpu_option arm10_options[] = {
@@ -2835,28 +2837,30 @@ arm10_setup(char *args) @@ -2835,28 +2837,30 @@ arm10_setup(char *args)
2835 | CPU_CONTROL_BPRD_ENABLE 2837 | CPU_CONTROL_BPRD_ENABLE
2836 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; 2838 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
2837 2839
2838#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 2840#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
2839 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 2841 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
2840#endif 2842#endif
2841 2843
2842 cpuctrl = parse_cpu_options(args, arm10_options, cpuctrl); 2844 cpuctrl = parse_cpu_options(args, arm10_options, cpuctrl);
2843 2845
2844#ifdef __ARMEB__ 2846#ifdef __ARMEB__
2845 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 2847 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
2846#endif 2848#endif
2847 2849
 2850#ifndef ARM_HAS_VBAR
2848 if (vector_page == ARM_VECTORS_HIGH) 2851 if (vector_page == ARM_VECTORS_HIGH)
2849 cpuctrl |= CPU_CONTROL_VECRELOC; 2852 cpuctrl |= CPU_CONTROL_VECRELOC;
 2853#endif
2850 2854
2851 /* Clear out the cache */ 2855 /* Clear out the cache */
2852 cpu_idcache_wbinv_all(); 2856 cpu_idcache_wbinv_all();
2853 2857
2854 /* Now really make sure they are clean. */ 2858 /* Now really make sure they are clean. */
2855 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); 2859 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
2856 2860
2857 /* Set the control register */ 2861 /* Set the control register */
2858 curcpu()->ci_ctrl = cpuctrl; 2862 curcpu()->ci_ctrl = cpuctrl;
2859 cpu_control(0xffffffff, cpuctrl); 2863 cpu_control(0xffffffff, cpuctrl);
2860 2864
2861 /* And again. */ 2865 /* And again. */
2862 cpu_idcache_wbinv_all(); 2866 cpu_idcache_wbinv_all();
@@ -2889,28 +2893,30 @@ arm11_setup(char *args) @@ -2889,28 +2893,30 @@ arm11_setup(char *args)
2889 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE 2893 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
2890 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; 2894 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
2891 2895
2892#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 2896#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
2893 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 2897 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
2894#endif 2898#endif
2895 2899
2896 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); 2900 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
2897 2901
2898#ifdef __ARMEB__ 2902#ifdef __ARMEB__
2899 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 2903 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
2900#endif 2904#endif
2901 2905
 2906#ifndef ARM_HAS_VBAR
2902 if (vector_page == ARM_VECTORS_HIGH) 2907 if (vector_page == ARM_VECTORS_HIGH)
2903 cpuctrl |= CPU_CONTROL_VECRELOC; 2908 cpuctrl |= CPU_CONTROL_VECRELOC;
 2909#endif
2904 2910
2905 /* Clear out the cache */ 2911 /* Clear out the cache */
2906 cpu_idcache_wbinv_all(); 2912 cpu_idcache_wbinv_all();
2907 2913
2908 /* Now really make sure they are clean. */ 2914 /* Now really make sure they are clean. */
2909 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); 2915 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
2910 2916
2911 /* Allow detection code to find the VFP if it's fitted. */ 2917 /* Allow detection code to find the VFP if it's fitted. */
2912 __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff)); 2918 __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
2913 2919
2914 /* Set the control register */ 2920 /* Set the control register */
2915 curcpu()->ci_ctrl = cpuctrl; 2921 curcpu()->ci_ctrl = cpuctrl;
2916 cpu_control(0xffffffff, cpuctrl); 2922 cpu_control(0xffffffff, cpuctrl);
@@ -2936,28 +2942,30 @@ arm11mpcore_setup(char *args) @@ -2936,28 +2942,30 @@ arm11mpcore_setup(char *args)
2936 | CPU_CONTROL_AFLT_ENABLE 2942 | CPU_CONTROL_AFLT_ENABLE
2937 | CPU_CONTROL_VECRELOC; 2943 | CPU_CONTROL_VECRELOC;
2938 2944
2939#ifdef ARM11MPCORE_MMU_COMPAT 2945#ifdef ARM11MPCORE_MMU_COMPAT
2940 /* XXX: S and R? */ 2946 /* XXX: S and R? */
2941#endif 2947#endif
2942 2948
2943#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 2949#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
2944 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 2950 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
2945#endif 2951#endif
2946 2952
2947 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); 2953 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
2948 2954
 2955#ifndef ARM_HAS_VBAR
2949 if (vector_page == ARM_VECTORS_HIGH) 2956 if (vector_page == ARM_VECTORS_HIGH)
2950 cpuctrl |= CPU_CONTROL_VECRELOC; 2957 cpuctrl |= CPU_CONTROL_VECRELOC;
 2958#endif
2951 2959
2952 /* Clear out the cache */ 2960 /* Clear out the cache */
2953 cpu_idcache_wbinv_all(); 2961 cpu_idcache_wbinv_all();
2954 2962
2955 /* Now really make sure they are clean. */ 2963 /* Now really make sure they are clean. */
2956 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); 2964 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
2957 2965
2958 /* Allow detection code to find the VFP if it's fitted. */ 2966 /* Allow detection code to find the VFP if it's fitted. */
2959 __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff)); 2967 __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
2960 2968
2961 /* Set the control register */ 2969 /* Set the control register */
2962 curcpu()->ci_ctrl = cpu_control(cpuctrlmask, cpuctrl); 2970 curcpu()->ci_ctrl = cpu_control(cpuctrlmask, cpuctrl);
2963 2971
@@ -2975,28 +2983,30 @@ pj4bv7_setup(char *args) @@ -2975,28 +2983,30 @@ pj4bv7_setup(char *args)
2975 pj4b_config(); 2983 pj4b_config();
2976 2984
2977 cpuctrl = CPU_CONTROL_MMU_ENABLE; 2985 cpuctrl = CPU_CONTROL_MMU_ENABLE;
2978#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 2986#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
2979 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 2987 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
2980#endif 2988#endif
2981 cpuctrl |= CPU_CONTROL_DC_ENABLE; 2989 cpuctrl |= CPU_CONTROL_DC_ENABLE;
2982 cpuctrl |= CPU_CONTROL_IC_ENABLE; 2990 cpuctrl |= CPU_CONTROL_IC_ENABLE;
2983 cpuctrl |= (0xf << 3); 2991 cpuctrl |= (0xf << 3);
2984 cpuctrl |= CPU_CONTROL_BPRD_ENABLE; 2992 cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
2985 cpuctrl |= (0x5 << 16) | (1 < 22); 2993 cpuctrl |= (0x5 << 16) | (1 < 22);
2986 cpuctrl |= CPU_CONTROL_XP_ENABLE; 2994 cpuctrl |= CPU_CONTROL_XP_ENABLE;
2987 2995
 2996#ifndef ARM_HAS_VBAR
2988 if (vector_page == ARM_VECTORS_HIGH) 2997 if (vector_page == ARM_VECTORS_HIGH)
2989 cpuctrl |= CPU_CONTROL_VECRELOC; 2998 cpuctrl |= CPU_CONTROL_VECRELOC;
 2999#endif
2990 3000
2991 /* Clear out the cache */ 3001 /* Clear out the cache */
2992 cpu_idcache_wbinv_all(); 3002 cpu_idcache_wbinv_all();
2993 3003
2994 /* Set the control register */ 3004 /* Set the control register */
2995 cpu_control(0xffffffff, cpuctrl); 3005 cpu_control(0xffffffff, cpuctrl);
2996 3006
2997 /* And again. */ 3007 /* And again. */
2998 cpu_idcache_wbinv_all(); 3008 cpu_idcache_wbinv_all();
2999 3009
3000 curcpu()->ci_ctrl = cpuctrl; 3010 curcpu()->ci_ctrl = cpuctrl;
3001} 3011}
3002#endif /* CPU_PJ4B */ 3012#endif /* CPU_PJ4B */
@@ -3024,28 +3034,30 @@ armv7_setup(char *args) @@ -3024,28 +3034,30 @@ armv7_setup(char *args)
3024 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE 3034 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
3025 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; 3035 | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
3026 3036
3027#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3037#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3028 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3038 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3029#endif 3039#endif
3030 3040
3031 cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl); 3041 cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl);
3032 3042
3033#ifdef __ARMEB__ 3043#ifdef __ARMEB__
3034 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3044 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3035#endif 3045#endif
3036 3046
 3047#ifndef ARM_HAS_VBAR
3037 if (vector_page == ARM_VECTORS_HIGH) 3048 if (vector_page == ARM_VECTORS_HIGH)
3038 cpuctrl |= CPU_CONTROL_VECRELOC; 3049 cpuctrl |= CPU_CONTROL_VECRELOC;
 3050#endif
3039 3051
3040 /* Clear out the cache */ 3052 /* Clear out the cache */
3041 cpu_idcache_wbinv_all(); 3053 cpu_idcache_wbinv_all();
3042 3054
3043 /* Set the control register */ 3055 /* Set the control register */
3044 curcpu()->ci_ctrl = cpuctrl; 3056 curcpu()->ci_ctrl = cpuctrl;
3045 cpu_control(0xffffffff, cpuctrl); 3057 cpu_control(0xffffffff, cpuctrl);
3046} 3058}
3047#endif /* CPU_CORTEX */ 3059#endif /* CPU_CORTEX */
3048 3060
3049 3061
3050#if defined(CPU_ARM1136) || defined(CPU_ARM1176)  3062#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
3051void 3063void
@@ -3081,28 +3093,30 @@ arm11x6_setup(char *args) @@ -3081,28 +3093,30 @@ arm11x6_setup(char *args)
3081 (3 << 19) | 3093 (3 << 19) |
3082 (1 << 17); 3094 (1 << 17);
3083 3095
3084#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3096#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3085 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3097 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3086#endif 3098#endif
3087 3099
3088 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); 3100 cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
3089 3101
3090#ifdef __ARMEB__ 3102#ifdef __ARMEB__
3091 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3103 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3092#endif 3104#endif
3093 3105
 3106#ifndef ARM_HAS_VBAR
3094 if (vector_page == ARM_VECTORS_HIGH) 3107 if (vector_page == ARM_VECTORS_HIGH)
3095 cpuctrl |= CPU_CONTROL_VECRELOC; 3108 cpuctrl |= CPU_CONTROL_VECRELOC;
 3109#endif
3096 3110
3097 auxctrl = 0; 3111 auxctrl = 0;
3098 auxctrl_wax = ~0; 3112 auxctrl_wax = ~0;
3099 /* 3113 /*
3100 * This options enables the workaround for the 364296 ARM1136 3114 * This options enables the workaround for the 364296 ARM1136
3101 * r0pX errata (possible cache data corruption with 3115 * r0pX errata (possible cache data corruption with
3102 * hit-under-miss enabled). It sets the undocumented bit 31 in 3116 * hit-under-miss enabled). It sets the undocumented bit 31 in
3103 * the auxiliary control register and the FI bit in the control 3117 * the auxiliary control register and the FI bit in the control
3104 * register, thus disabling hit-under-miss without putting the 3118 * register, thus disabling hit-under-miss without putting the
3105 * processor into full low interrupt latency mode. ARM11MPCore 3119 * processor into full low interrupt latency mode. ARM11MPCore
3106 * is not affected. 3120 * is not affected.
3107 */ 3121 */
3108 if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */ 3122 if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
@@ -3179,28 +3193,30 @@ sa110_setup(char *args) @@ -3179,28 +3193,30 @@ sa110_setup(char *args)
3179 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE 3193 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
3180 | CPU_CONTROL_CPCLK; 3194 | CPU_CONTROL_CPCLK;
3181 3195
3182#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3196#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3183 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3197 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3184#endif 3198#endif
3185 3199
3186 cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl); 3200 cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl);
3187 3201
3188#ifdef __ARMEB__ 3202#ifdef __ARMEB__
3189 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3203 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3190#endif 3204#endif
3191 3205
 3206#ifndef ARM_HAS_VBAR
3192 if (vector_page == ARM_VECTORS_HIGH) 3207 if (vector_page == ARM_VECTORS_HIGH)
3193 cpuctrl |= CPU_CONTROL_VECRELOC; 3208 cpuctrl |= CPU_CONTROL_VECRELOC;
 3209#endif
3194 3210
3195 /* Clear out the cache */ 3211 /* Clear out the cache */
3196 cpu_idcache_wbinv_all(); 3212 cpu_idcache_wbinv_all();
3197 3213
3198 /* Set the control register */ 3214 /* Set the control register */
3199 curcpu()->ci_ctrl = cpuctrl; 3215 curcpu()->ci_ctrl = cpuctrl;
3200/* cpu_control(cpuctrlmask, cpuctrl);*/ 3216/* cpu_control(cpuctrlmask, cpuctrl);*/
3201 cpu_control(0xffffffff, cpuctrl); 3217 cpu_control(0xffffffff, cpuctrl);
3202 3218
3203 /* 3219 /*
3204 * enable clockswitching, note that this doesn't read or write to r0, 3220 * enable clockswitching, note that this doesn't read or write to r0,
3205 * r0 is just to make it valid asm 3221 * r0 is just to make it valid asm
3206 */ 3222 */
@@ -3242,28 +3258,30 @@ sa11x0_setup(char *args) @@ -3242,28 +3258,30 @@ sa11x0_setup(char *args)
3242 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE 3258 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
3243 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; 3259 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
3244 3260
3245#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3261#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3246 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3262 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3247#endif 3263#endif
3248 3264
3249 cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl); 3265 cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl);
3250 3266
3251#ifdef __ARMEB__ 3267#ifdef __ARMEB__
3252 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3268 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3253#endif 3269#endif
3254 3270
 3271#ifndef ARM_HAS_VBAR
3255 if (vector_page == ARM_VECTORS_HIGH) 3272 if (vector_page == ARM_VECTORS_HIGH)
3256 cpuctrl |= CPU_CONTROL_VECRELOC; 3273 cpuctrl |= CPU_CONTROL_VECRELOC;
 3274#endif
3257 3275
3258 /* Clear out the cache */ 3276 /* Clear out the cache */
3259 cpu_idcache_wbinv_all(); 3277 cpu_idcache_wbinv_all();
3260 3278
3261 /* Set the control register */ 3279 /* Set the control register */
3262 curcpu()->ci_ctrl = cpuctrl; 3280 curcpu()->ci_ctrl = cpuctrl;
3263 cpu_control(0xffffffff, cpuctrl); 3281 cpu_control(0xffffffff, cpuctrl);
3264} 3282}
3265#endif /* CPU_SA1100 || CPU_SA1110 */ 3283#endif /* CPU_SA1100 || CPU_SA1110 */
3266 3284
3267#if defined(CPU_FA526) 3285#if defined(CPU_FA526)
3268struct cpu_option fa526_options[] = { 3286struct cpu_option fa526_options[] = {
3269#ifdef COMPAT_12 3287#ifdef COMPAT_12
@@ -3294,28 +3312,30 @@ fa526_setup(char *args) @@ -3294,28 +3312,30 @@ fa526_setup(char *args)
3294 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE 3312 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
3295 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; 3313 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
3296 3314
3297#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3315#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3298 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3316 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3299#endif 3317#endif
3300 3318
3301 cpuctrl = parse_cpu_options(args, fa526_options, cpuctrl); 3319 cpuctrl = parse_cpu_options(args, fa526_options, cpuctrl);
3302 3320
3303#ifdef __ARMEB__ 3321#ifdef __ARMEB__
3304 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3322 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3305#endif 3323#endif
3306 3324
 3325#ifndef ARM_HAS_VBAR
3307 if (vector_page == ARM_VECTORS_HIGH) 3326 if (vector_page == ARM_VECTORS_HIGH)
3308 cpuctrl |= CPU_CONTROL_VECRELOC; 3327 cpuctrl |= CPU_CONTROL_VECRELOC;
 3328#endif
3309 3329
3310 /* Clear out the cache */ 3330 /* Clear out the cache */
3311 cpu_idcache_wbinv_all(); 3331 cpu_idcache_wbinv_all();
3312 3332
3313 /* Set the control register */ 3333 /* Set the control register */
3314 curcpu()->ci_ctrl = cpuctrl; 3334 curcpu()->ci_ctrl = cpuctrl;
3315 cpu_control(0xffffffff, cpuctrl); 3335 cpu_control(0xffffffff, cpuctrl);
3316} 3336}
3317#endif /* CPU_FA526 */ 3337#endif /* CPU_FA526 */
3318 3338
3319#if defined(CPU_IXP12X0) 3339#if defined(CPU_IXP12X0)
3320struct cpu_option ixp12x0_options[] = { 3340struct cpu_option ixp12x0_options[] = {
3321 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, 3341 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@@ -3345,28 +3365,30 @@ ixp12x0_setup(char *args) @@ -3345,28 +3365,30 @@ ixp12x0_setup(char *args)
3345 | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE 3365 | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
3346 | CPU_CONTROL_VECRELOC; 3366 | CPU_CONTROL_VECRELOC;
3347 3367
3348#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3368#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3349 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3369 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3350#endif 3370#endif
3351 3371
3352 cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl); 3372 cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl);
3353 3373
3354#ifdef __ARMEB__ 3374#ifdef __ARMEB__
3355 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3375 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3356#endif 3376#endif
3357 3377
 3378#ifndef ARM_HAS_VBAR
3358 if (vector_page == ARM_VECTORS_HIGH) 3379 if (vector_page == ARM_VECTORS_HIGH)
3359 cpuctrl |= CPU_CONTROL_VECRELOC; 3380 cpuctrl |= CPU_CONTROL_VECRELOC;
 3381#endif
3360 3382
3361 /* Clear out the cache */ 3383 /* Clear out the cache */
3362 cpu_idcache_wbinv_all(); 3384 cpu_idcache_wbinv_all();
3363 3385
3364 /* Set the control register */ 3386 /* Set the control register */
3365 curcpu()->ci_ctrl = cpuctrl; 3387 curcpu()->ci_ctrl = cpuctrl;
3366 /* cpu_control(0xffffffff, cpuctrl); */ 3388 /* cpu_control(0xffffffff, cpuctrl); */
3367 cpu_control(cpuctrlmask, cpuctrl); 3389 cpu_control(cpuctrlmask, cpuctrl);
3368} 3390}
3369#endif /* CPU_IXP12X0 */ 3391#endif /* CPU_IXP12X0 */
3370 3392
3371#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 3393#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
3372 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEX) 3394 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEX)
@@ -3410,28 +3432,30 @@ xscale_setup(char *args) @@ -3410,28 +3432,30 @@ xscale_setup(char *args)
3410 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE 3432 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
3411 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; 3433 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
3412 3434
3413#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS 3435#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
3414 cpuctrl |= CPU_CONTROL_AFLT_ENABLE; 3436 cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
3415#endif 3437#endif
3416 3438
3417 cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl); 3439 cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl);
3418 3440
3419#ifdef __ARMEB__ 3441#ifdef __ARMEB__
3420 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3442 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3421#endif 3443#endif
3422 3444
 3445#ifndef ARM_HAS_VBAR
3423 if (vector_page == ARM_VECTORS_HIGH) 3446 if (vector_page == ARM_VECTORS_HIGH)
3424 cpuctrl |= CPU_CONTROL_VECRELOC; 3447 cpuctrl |= CPU_CONTROL_VECRELOC;
 3448#endif
3425 3449
3426 /* Clear out the cache */ 3450 /* Clear out the cache */
3427 cpu_idcache_wbinv_all(); 3451 cpu_idcache_wbinv_all();
3428 3452
3429 /* 3453 /*
3430 * Set the control register. Note that bits 6:3 must always 3454 * Set the control register. Note that bits 6:3 must always
3431 * be set to 1. 3455 * be set to 1.
3432 */ 3456 */
3433 curcpu()->ci_ctrl = cpuctrl; 3457 curcpu()->ci_ctrl = cpuctrl;
3434/* cpu_control(cpuctrlmask, cpuctrl);*/ 3458/* cpu_control(cpuctrlmask, cpuctrl);*/
3435 cpu_control(0xffffffff, cpuctrl); 3459 cpu_control(0xffffffff, cpuctrl);
3436 3460
3437 /* Make sure write coalescing is turned on */ 3461 /* Make sure write coalescing is turned on */
@@ -3490,28 +3514,30 @@ sheeva_setup(char *args) @@ -3490,28 +3514,30 @@ sheeva_setup(char *args)
3490 3514
3491 __asm volatile("mcr p15, 1, %0, c15, c1, 0" 3515 __asm volatile("mcr p15, 1, %0, c15, c1, 0"
3492 :: "r" (sheeva_ext)); 3516 :: "r" (sheeva_ext));
3493 3517
3494 /* 3518 /*
3495 * Sheeva has L2 Cache. Enable/Disable it here. 3519 * Sheeva has L2 Cache. Enable/Disable it here.
3496 * Really not support yet... 3520 * Really not support yet...
3497 */ 3521 */
3498 3522
3499#ifdef __ARMEB__ 3523#ifdef __ARMEB__
3500 cpuctrl |= CPU_CONTROL_BEND_ENABLE; 3524 cpuctrl |= CPU_CONTROL_BEND_ENABLE;
3501#endif 3525#endif
3502 3526
 3527#ifndef ARM_HAS_VBAR
3503 if (vector_page == ARM_VECTORS_HIGH) 3528 if (vector_page == ARM_VECTORS_HIGH)
3504 cpuctrl |= CPU_CONTROL_VECRELOC; 3529 cpuctrl |= CPU_CONTROL_VECRELOC;
 3530#endif
3505 3531
3506 /* Clear out the cache */ 3532 /* Clear out the cache */
3507 cpu_idcache_wbinv_all(); 3533 cpu_idcache_wbinv_all();
3508 3534
3509 /* Now really make sure they are clean. */ 3535 /* Now really make sure they are clean. */
3510 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); 3536 __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
3511 3537
3512 /* Set the control register */ 3538 /* Set the control register */
3513 curcpu()->ci_ctrl = cpuctrl; 3539 curcpu()->ci_ctrl = cpuctrl;
3514 cpu_control(0xffffffff, cpuctrl); 3540 cpu_control(0xffffffff, cpuctrl);
3515 3541
3516 /* And again. */ 3542 /* And again. */
3517 cpu_idcache_wbinv_all(); 3543 cpu_idcache_wbinv_all();