 @@ -1,1805 +1,1811 @@
 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  */
 /*
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
  * without limitation the rights to use, copy, modify, merge, publish,
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
+ *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #ifndef __NetBSD__		/* XXX fb */
 #include <drm/drm_fb_helper.h>
 #endif
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <linux/pci.h>
 #include <linux/vgaarb.h>
 #include <linux/acpi.h>
 #include <linux/pnp.h>
 #include <linux/vga_switcheroo.h>
 #include <linux/slab.h>
 #include <acpi/video.h>
 #include <asm/pat.h>
 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
 #define BEGIN_LP_RING(n) \
 	intel_ring_begin(LP_RING(dev_priv), (n))
 #define OUT_RING(x) \
 	intel_ring_emit(LP_RING(dev_priv), x)
 #define ADVANCE_LP_RING() \
 	intel_ring_advance(LP_RING(dev_priv))
 /**
  * Lock test for when it's just for synchronization of ring access.
+ *
  * In that case, we don't need to do it when GEM is initialized as nobody else
  * has access to the ring.
  */
 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {			\
 	if (LP_RING(dev->dev_private)->obj == NULL)			\
 		LOCK_TEST_WITH_RETURN(dev, file);			\
 } while (0)
 static inline u32
 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
+{
 	if (I915_NEED_GFX_HWS(dev_priv->dev))
 #ifdef __NetBSD__
 		return DRM_READ32(&dev_priv->dri1.gfx_hws_cpu_map, reg);
 #else
 		return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
 #endif
 	else
 		return intel_read_status_page(LP_RING(dev_priv), reg);
+}
 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 #define I915_BREADCRUMB_INDEX		0x21
 void i915_update_dri1_breadcrumb(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv;
 	if (dev->primary->master) {
 		master_priv = dev->primary->master->driver_priv;
 		if (master_priv->sarea_priv)
 			master_priv->sarea_priv->last_dispatch =
 				READ_BREADCRUMB(dev_priv);
+	}
+}
 static void i915_write_hws_pga(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	u32 addr;
 	addr = dev_priv->status_page_dmah->busaddr;
 	if (INTEL_INFO(dev)->gen >= 4)
 		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 	I915_WRITE(HWS_PGA, addr);
+}
 /**
  * Frees the hardware status page, whether it's a physical address or a virtual
  * address set up by the X Server.
  */
 static void i915_free_hws(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 	if (dev_priv->status_page_dmah) {
 		drm_pci_free(dev, dev_priv->status_page_dmah);
 		dev_priv->status_page_dmah = NULL;
+	}
 	if (ring->status_page.gfx_addr) {
 		ring->status_page.gfx_addr = 0;
 #ifdef __NetBSD__
 		drm_iounmap(dev, &dev_priv->dri1.gfx_hws_cpu_map);
 #else
 		iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 #endif
+	}
 	/* Need to rewrite hardware status page */
 	I915_WRITE(HWS_PGA, 0x1ffff000);
+}
 void i915_kernel_lost_context(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv;
 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 	/*
 	 * We should never lose context on the ring with modesetting
 	 * as we don't expose it to userspace
 	 */
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return;
 	ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 	ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 	if (ring->space < 0)
 		ring->space += ring->size;
 	if (!dev->primary->master)
 		return;
 	master_priv = dev->primary->master->driver_priv;
 	if (ring->head == ring->tail && master_priv->sarea_priv)
 		master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
+}
 static int i915_dma_cleanup(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
 	if (dev->irq_enabled)
 		drm_irq_uninstall(dev);
 	mutex_lock(&dev->struct_mutex);
 	for (i = 0; i < I915_NUM_RINGS; i++)
 		intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 	mutex_unlock(&dev->struct_mutex);
 	/* Clear the HWS virtual address at teardown */
 	if (I915_NEED_GFX_HWS(dev))
 		i915_free_hws(dev);
 	return 0;
+}
 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	int ret;
 	master_priv->sarea = drm_getsarea(dev);
 	if (master_priv->sarea) {
 		master_priv->sarea_priv = (drm_i915_sarea_t *)
 			((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 	} else {
 		DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
+	}
 	if (init->ring_size != 0) {
 		if (LP_RING(dev_priv)->obj != NULL) {
 			i915_dma_cleanup(dev);
 			DRM_ERROR("Client tried to initialize ringbuffer in "
 				  "GEM mode\n");
 			return -EINVAL;
+		}
 		ret = intel_render_ring_init_dri(dev,
 						 init->ring_start,
 						 init->ring_size);
 		if (ret) {
 			i915_dma_cleanup(dev);
 			return ret;
+		}
+	}
 	dev_priv->dri1.cpp = init->cpp;
 	dev_priv->dri1.back_offset = init->back_offset;
 	dev_priv->dri1.front_offset = init->front_offset;
 	dev_priv->dri1.current_page = 0;
 	if (master_priv->sarea_priv)
 		master_priv->sarea_priv->pf_current_page = 0;
 	/* Allow hardware batchbuffers unless told otherwise.
 	 */
 	dev_priv->dri1.allow_batchbuffer = 1;
 	return 0;
+}
 static int i915_dma_resume(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 	DRM_DEBUG_DRIVER("%s\n", __func__);
 #ifdef __NetBSD__
 	if (!ring->virtual_start_mapped) {
 		DRM_ERROR("can not ioremap virtual address for"
 			  " ring buffer\n");
 		return -ENOMEM;
+	}
 #else
 	if (ring->virtual_start == NULL) {
 		DRM_ERROR("can not ioremap virtual address for"
 			  " ring buffer\n");
 		return -ENOMEM;
+	}
 #endif
 	/* Program Hardware Status Page */
 	if (!ring->status_page.page_addr) {
 		DRM_ERROR("Can not find hardware status page\n");
 		return -EINVAL;
+	}
 	DRM_DEBUG_DRIVER("hw status page @ %p\n",
 				ring->status_page.page_addr);
 	if (ring->status_page.gfx_addr != 0)
 		intel_ring_setup_status_page(ring);
 	else
 		i915_write_hws_pga(dev);
 	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 	return 0;
+}
 static int i915_dma_init(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_init_t *init = data;
 	int retcode = 0;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	switch (init->func) {
 	case I915_INIT_DMA:
 		retcode = i915_initialize(dev, init);
 		break;
 	case I915_CLEANUP_DMA:
 		retcode = i915_dma_cleanup(dev);
 		break;
 	case I915_RESUME_DMA:
 		retcode = i915_dma_resume(dev);
 		break;
 	default:
 		retcode = -EINVAL;
 		break;
+	}
 	return retcode;
+}
 /* Implement basically the same security restrictions as hardware does
  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
+ *
  * Most of the calculations below involve calculating the size of a
  * particular instruction.  It's important to get the size right as
  * that tells us where the next instruction to check is.  Any illegal
  * instruction detected will be given a size of zero, which is a
  * signal to abort the rest of the buffer.
  */
 static int validate_cmd(int cmd)
+{
 	switch (((cmd >> 29) & 0x7)) {
 	case 0x0:
 		switch ((cmd >> 23) & 0x3f) {
 		case 0x0:
 			return 1;	/* MI_NOOP */
 		case 0x4:
 			return 1;	/* MI_FLUSH */
 		default:
 			return 0;	/* disallow everything else */
+		}
 		break;
 	case 0x1:
 		return 0;	/* reserved */
 	case 0x2:
 		return (cmd & 0xff) + 2;	/* 2d commands */
 	case 0x3:
 		if (((cmd >> 24) & 0x1f) <= 0x18)
 			return 1;
 		switch ((cmd >> 24) & 0x1f) {
 		case 0x1c:
 			return 1;
 		case 0x1d:
 			switch ((cmd >> 16) & 0xff) {
 			case 0x3:
 				return (cmd & 0x1f) + 2;
 			case 0x4:
 				return (cmd & 0xf) + 2;
 			default:
 				return (cmd & 0xffff) + 2;
+			}
 		case 0x1e:
 			if (cmd & (1 << 23))
 				return (cmd & 0xffff) + 1;
 			else
 				return 1;
 		case 0x1f:
 			if ((cmd & (1 << 23)) == 0)	/* inline vertices */
 				return (cmd & 0x1ffff) + 2;
 			else if (cmd & (1 << 17))	/* indirect random */
 				if ((cmd & 0xffff) == 0)
 					return 0;	/* unknown length, too hard */
 				else
 					return (((cmd & 0xffff) + 1) / 2) + 1;
 			else
 				return 2;	/* indirect sequential */
 		default:
 			return 0;
+		}
 	default:
 		return 0;
+	}
 	return 0;
+}
 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i, ret;
 	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 		return -EINVAL;
 	for (i = 0; i < dwords;) {
 		int sz = validate_cmd(buffer[i]);
 		if (sz == 0 || i + sz > dwords)
 			return -EINVAL;
 		i += sz;
+	}
 	ret = BEGIN_LP_RING((dwords+1)&~1);
 	if (ret)
 		return ret;
 	for (i = 0; i < dwords; i++)
 		OUT_RING(buffer[i]);
 	if (dwords & 1)
 		OUT_RING(0);
 	ADVANCE_LP_RING();
 	return 0;
+}
 int
 i915_emit_box(struct drm_device *dev,
 	      struct drm_clip_rect *box,
 	      int DR1, int DR4)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 	    box->y2 <= 0 || box->x2 <= 0) {
 		DRM_ERROR("Bad box %d,%d..%d,%d\n",
 			  box->x1, box->y1, box->x2, box->y2);
 		return -EINVAL;
+	}
 	if (INTEL_INFO(dev)->gen >= 4) {
 		ret = BEGIN_LP_RING(4);
 		if (ret)
 			return ret;
 		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 		OUT_RING(DR4);
 	} else {
 		ret = BEGIN_LP_RING(6);
 		if (ret)
 			return ret;
 		OUT_RING(GFX_OP_DRAWRECT_INFO);
 		OUT_RING(DR1);
 		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 		OUT_RING(DR4);
 		OUT_RING(0);
+	}
 	ADVANCE_LP_RING();
 	return 0;
+}
 /* XXX: Emitting the counter should really be moved to part of the IRQ
  * emit. For now, do it in both places:
  */
 static void i915_emit_breadcrumb(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	dev_priv->dri1.counter++;
 	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 		dev_priv->dri1.counter = 0;
 	if (master_priv->sarea_priv)
 		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 	if (BEGIN_LP_RING(4) == 0) {
 		OUT_RING(MI_STORE_DWORD_INDEX);
 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 		OUT_RING(dev_priv->dri1.counter);
 		OUT_RING(0);
 		ADVANCE_LP_RING();
+	}
+}
 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 				   drm_i915_cmdbuffer_t *cmd,
 				   struct drm_clip_rect *cliprects,
 				   void *cmdbuf)
+{
 	int nbox = cmd->num_cliprects;
 	int i = 0, count, ret;
 	if (cmd->sz & 0x3) {
 		DRM_ERROR("alignment");
 		return -EINVAL;
+	}
 	i915_kernel_lost_context(dev);
 	count = nbox ? nbox : 1;
 	for (i = 0; i < count; i++) {
 		if (i < nbox) {
 			ret = i915_emit_box(dev, &cliprects[i],
 					    cmd->DR1, cmd->DR4);
 			if (ret)
 				return ret;
+		}
 		ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 		if (ret)
 			return ret;
+	}
 	i915_emit_breadcrumb(dev);
 	return 0;
+}
 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 				     drm_i915_batchbuffer_t * batch,
 				     struct drm_clip_rect *cliprects)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int nbox = batch->num_cliprects;
 	int i, count, ret;
 	if ((batch->start | batch->used) & 0x7) {
 		DRM_ERROR("alignment");
 		return -EINVAL;
+	}
 	i915_kernel_lost_context(dev);
 	count = nbox ? nbox : 1;
 	for (i = 0; i < count; i++) {
 		if (i < nbox) {
 			ret = i915_emit_box(dev, &cliprects[i],
 					    batch->DR1, batch->DR4);
 			if (ret)
 				return ret;
+		}
 		if (!IS_I830(dev) && !IS_845G(dev)) {
 			ret = BEGIN_LP_RING(2);
 			if (ret)
 				return ret;
 			if (INTEL_INFO(dev)->gen >= 4) {
 				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 				OUT_RING(batch->start);
 			} else {
 				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
+			}
 		} else {
 			ret = BEGIN_LP_RING(4);
 			if (ret)
 				return ret;
 			OUT_RING(MI_BATCH_BUFFER);
 			OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 			OUT_RING(batch->start + batch->used - 4);
 			OUT_RING(0);
+		}
 		ADVANCE_LP_RING();
+	}
 	if (IS_G4X(dev) || IS_GEN5(dev)) {
 		if (BEGIN_LP_RING(2) == 0) {
 			OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 			OUT_RING(MI_NOOP);
 			ADVANCE_LP_RING();
+		}
+	}
 	i915_emit_breadcrumb(dev);
 	return 0;
+}
 static int i915_dispatch_flip(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv =
 		dev->primary->master->driver_priv;
 	int ret;
 	if (!master_priv->sarea_priv)
 		return -EINVAL;
 	DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 			  __func__,
 			 dev_priv->dri1.current_page,
 			 master_priv->sarea_priv->pf_current_page);
 	i915_kernel_lost_context(dev);
 	ret = BEGIN_LP_RING(10);
 	if (ret)
 		return ret;
 	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 	OUT_RING(0);
 	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 	OUT_RING(0);
 	if (dev_priv->dri1.current_page == 0) {
 		OUT_RING(dev_priv->dri1.back_offset);
 		dev_priv->dri1.current_page = 1;
 	} else {
 		OUT_RING(dev_priv->dri1.front_offset);
 		dev_priv->dri1.current_page = 0;
+	}
 	OUT_RING(0);
 	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 	OUT_RING(0);
 	ADVANCE_LP_RING();
 	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 	if (BEGIN_LP_RING(4) == 0) {
 		OUT_RING(MI_STORE_DWORD_INDEX);
 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 		OUT_RING(dev_priv->dri1.counter);
 		OUT_RING(0);
 		ADVANCE_LP_RING();
+	}
 	master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 	return 0;
+}
 static int i915_quiescent(struct drm_device *dev)
+{
 	i915_kernel_lost_context(dev);
 	return intel_ring_idle(LP_RING(dev->dev_private));
+}
 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv)
+{
 	int ret;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_quiescent(dev);
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 static int i915_batchbuffer(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    master_priv->sarea_priv;
 	drm_i915_batchbuffer_t *batch = data;
 	int ret;
 	struct drm_clip_rect *cliprects = NULL;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	if (!dev_priv->dri1.allow_batchbuffer) {
 		DRM_ERROR("Batchbuffer ioctl disabled\n");
 		return -EINVAL;
+	}
 	DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 			batch->start, batch->used, batch->num_cliprects);
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 	if (batch->num_cliprects < 0)
 		return -EINVAL;
 	if (batch->num_cliprects) {
 		cliprects = kcalloc(batch->num_cliprects,
 				    sizeof(struct drm_clip_rect),
 				    GFP_KERNEL);
 		if (cliprects == NULL)
 			return -ENOMEM;
 		ret = copy_from_user(cliprects, batch->cliprects,
 				     batch->num_cliprects *
 				     sizeof(struct drm_clip_rect));
 		if (ret != 0) {
 			ret = -EFAULT;
 			goto fail_free;
+		}
+	}
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 	mutex_unlock(&dev->struct_mutex);
 	if (sarea_priv)
 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 fail_free:
 	kfree(cliprects);
 	return ret;
+}
 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    master_priv->sarea_priv;
 	drm_i915_cmdbuffer_t *cmdbuf = data;
 	struct drm_clip_rect *cliprects = NULL;
 	void *batch_data;
 	int ret;
 	DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 			cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 	if (cmdbuf->num_cliprects < 0)
 		return -EINVAL;
 	batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 	if (batch_data == NULL)
 		return -ENOMEM;
 	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 	if (ret != 0) {
 		ret = -EFAULT;
 		goto fail_batch_free;
+	}
 	if (cmdbuf->num_cliprects) {
 		cliprects = kcalloc(cmdbuf->num_cliprects,
 				    sizeof(struct drm_clip_rect), GFP_KERNEL);
 		if (cliprects == NULL) {
 			ret = -ENOMEM;
 			goto fail_batch_free;
+		}
 		ret = copy_from_user(cliprects, cmdbuf->cliprects,
 				     cmdbuf->num_cliprects *
 				     sizeof(struct drm_clip_rect));
 		if (ret != 0) {
 			ret = -EFAULT;
 			goto fail_clip_free;
+		}
+	}
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 	mutex_unlock(&dev->struct_mutex);
 	if (ret) {
 		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 		goto fail_clip_free;
+	}
 	if (sarea_priv)
 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 fail_clip_free:
 	kfree(cliprects);
 fail_batch_free:
 	kfree(batch_data);
 	return ret;
+}
 static int i915_emit_irq(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	i915_kernel_lost_context(dev);
 	DRM_DEBUG_DRIVER("\n");
 	dev_priv->dri1.counter++;
 	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 		dev_priv->dri1.counter = 1;
 	if (master_priv->sarea_priv)
 		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 	if (BEGIN_LP_RING(4) == 0) {
 		OUT_RING(MI_STORE_DWORD_INDEX);
 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 		OUT_RING(dev_priv->dri1.counter);
 		OUT_RING(MI_USER_INTERRUPT);
 		ADVANCE_LP_RING();
+	}
 	return dev_priv->dri1.counter;
+}
 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 	int ret = 0;
 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 	DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 		  READ_BREADCRUMB(dev_priv));
 	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 		if (master_priv->sarea_priv)
 			master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 		return 0;
+	}
 	if (master_priv->sarea_priv)
 		master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 	if (ring->irq_get(ring)) {
 #ifdef __NetBSD__
 		DRM_TIMED_WAIT_UNTIL(ret, &ring->irq_queue, &drm_global_mutex,
 * DRM_HZ,
 		    READ_BREADCRUMB(dev_priv) >= irq_nr);
 #else
 		DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 			    READ_BREADCRUMB(dev_priv) >= irq_nr);
 #endif
 		ring->irq_put(ring);
 	} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 		ret = -EBUSY;
 	if (ret == -EBUSY) {
 		DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
+	}
 	return ret;
+}
 /* Needs the lock as it touches the ring.
  */
 static int i915_irq_emit(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_irq_emit_t *emit = data;
 	int result;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 #ifdef __NetBSD__
 	if (!dev_priv || !LP_RING(dev_priv)->virtual_start_mapped) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 #else
 	if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 #endif
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 	mutex_lock(&dev->struct_mutex);
 	result = i915_emit_irq(dev);
 	mutex_unlock(&dev->struct_mutex);
 	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 		DRM_ERROR("copy_to_user\n");
 		return -EFAULT;
+	}
 	return 0;
+}
 /* Doesn't need the hardware lock.
  */
 static int i915_irq_wait(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_irq_wait_t *irqwait = data;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 	return i915_wait_irq(dev, irqwait->irq_seq);
+}
 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_vblank_pipe_t *pipe = data;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 	pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 	return 0;
+}
 /**
  * Schedule buffer swap at given vertical blank.
  */
 static int i915_vblank_swap(struct drm_device *dev, void *data,
 		     struct drm_file *file_priv)
+{
 	/* The delayed swap mechanism was fundamentally racy, and has been
 	 * removed.  The model was that the client requested a delayed flip/swap
 	 * from the kernel, then waited for vblank before continuing to perform
 	 * rendering.  The problem was that the kernel might wake the client
 	 * up before it dispatched the vblank swap (since the lock has to be
 	 * held while touching the ringbuffer), in which case the client would
 	 * clear and start the next frame before the swap occurred, and
 	 * flicker would occur in addition to likely missing the vblank.
+	 *
 	 * In the absence of this ioctl, userland falls back to a correct path
 	 * of waiting for a vblank, then dispatching the swap on its own.
 	 * Context switching to userland and back is plenty fast enough for
 	 * meeting the requirements of vblank swapping.
 	 */
 	return -EINVAL;
+}
 static int i915_flip_bufs(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv)
+{
 	int ret;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	DRM_DEBUG_DRIVER("%s\n", __func__);
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_dispatch_flip(dev);
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 static int i915_getparam(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_getparam_t *param = data;
 	int value;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 	switch (param->param) {
 	case I915_PARAM_IRQ_ACTIVE:
 		value = dev->pdev->irq ? 1 : 0;
 		break;
 	case I915_PARAM_ALLOW_BATCHBUFFER:
 		value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 		break;
 	case I915_PARAM_LAST_DISPATCH:
 		value = READ_BREADCRUMB(dev_priv);
 		break;
 	case I915_PARAM_CHIPSET_ID:
 		value = dev->pci_device;
 		break;
 	case I915_PARAM_HAS_GEM:
 		value = 1;
 		break;
 	case I915_PARAM_NUM_FENCES_AVAIL:
 		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 		break;
 	case I915_PARAM_HAS_OVERLAY:
 		value = dev_priv->overlay ? 1 : 0;
 		break;
 	case I915_PARAM_HAS_PAGEFLIPPING:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_EXECBUF2:
 		/* depends on GEM */
 		value = 1;
 		break;
 	case I915_PARAM_HAS_BSD:
 		value = intel_ring_initialized(&dev_priv->ring[VCS]);
 		break;
 	case I915_PARAM_HAS_BLT:
 		value = intel_ring_initialized(&dev_priv->ring[BCS]);
 		break;
 	case I915_PARAM_HAS_RELAXED_FENCING:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_COHERENT_RINGS:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_EXEC_CONSTANTS:
 		value = INTEL_INFO(dev)->gen >= 4;
 		break;
 	case I915_PARAM_HAS_RELAXED_DELTA:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_GEN7_SOL_RESET:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_LLC:
 		value = HAS_LLC(dev);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
 		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 		break;
 	case I915_PARAM_HAS_WAIT_TIMEOUT:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = i915_semaphore_is_enabled(dev);
 		break;
 	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 		value = 1;
 		break;
 	case I915_PARAM_HAS_SECURE_BATCHES:
 		value = capable(CAP_SYS_ADMIN);
 		break;
 	case I915_PARAM_HAS_PINNED_BATCHES:
 		value = 1;
 		break;
 	default:
 		DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 				 param->param);
 		return -EINVAL;
+	}
 	if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 		DRM_ERROR("DRM_COPY_TO_USER failed\n");
 		return -EFAULT;
+	}
 	return 0;
+}
 static int i915_setparam(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_setparam_t *param = data;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 	switch (param->param) {
 	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 		break;
 	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 		break;
 	case I915_SETPARAM_ALLOW_BATCHBUFFER:
 		dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
 		break;
 	case I915_SETPARAM_NUM_USED_FENCES:
 		if (param->value > dev_priv->num_fence_regs ||
 		    param->value < 0)
 			return -EINVAL;
 		/* Userspace can use first N regs */
 		dev_priv->fence_reg_start = param->value;
 		break;
 	default:
 		DRM_DEBUG_DRIVER("unknown parameter %d\n",
 					param->param);
 		return -EINVAL;
+	}
 	return 0;
+}
 static int i915_set_status_page(struct drm_device *dev, void *data,
 				struct drm_file *file_priv)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_hws_addr_t *hws = data;
 	struct intel_ring_buffer *ring;
 #ifdef __NetBSD__
 	struct drm_local_map *const gfx_hws_cpu_map =
 	    &dev_priv->dri1.gfx_hws_cpu_map;
 #endif
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	if (!I915_NEED_GFX_HWS(dev))
 		return -EINVAL;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
+	}
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		WARN(1, "tried to set status page when mode setting active\n");
 		return 0;
+	}
 	DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 	ring = LP_RING(dev_priv);
 	ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 #ifdef __NetBSD__
 	gfx_hws_cpu_map->offset = (dev_priv->mm.gtt_base_addr +
 	    hws->addr);
 	gfx_hws_cpu_map->size = 4096;
 	gfx_hws_cpu_map->flags = 0;
 	gfx_hws_cpu_map->flags |= _DRM_RESTRICTED;
 	gfx_hws_cpu_map->flags |= _DRM_KERNEL;
 	gfx_hws_cpu_map->flags |= _DRM_WRITE_COMBINING;
 	gfx_hws_cpu_map->flags |= _DRM_DRIVER;
 	if (drm_ioremap(dev, gfx_hws_cpu_map) == NULL) {
 		i915_dma_cleanup(dev);
 		ring->status_page.gfx_addr = 0;
 		DRM_ERROR("can not ioremap virtual address for"
 				" G33 hw status page\n");
 		return -ENOMEM;
+	}
 	/* XXX drm_local_map abstraction violation.  Pooh.  */
 	bus_space_set_region_1(gfx_hws_cpu_map->lm_data.bus_space.bst,
 	    gfx_hws_cpu_map->lm_data.bus_space.bsh, 0, 0, PAGE_SIZE);
 #else
 	dev_priv->dri1.gfx_hws_cpu_addr =
 		ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
 	if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
 		i915_dma_cleanup(dev);
 		ring->status_page.gfx_addr = 0;
 		DRM_ERROR("can not ioremap virtual address for"
 				" G33 hw status page\n");
 		return -ENOMEM;
+	}
 	memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
 #endif
 	I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 	DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 			 ring->status_page.gfx_addr);
 	DRM_DEBUG_DRIVER("load hws at %p\n",
 			 ring->status_page.page_addr);
 	return 0;
+}
 static int i915_get_bridge_dev(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 	if (!dev_priv->bridge_dev) {
 		DRM_ERROR("bridge device not found\n");
 		return -1;
+	}
 	return 0;
+}
 #define MCHBAR_I915 0x44
 #define MCHBAR_I965 0x48
 #define MCHBAR_SIZE (4*4096)
 #define DEVEN_REG 0x54
 #define   DEVEN_MCHBAR_EN (1 << 28)
 /* Allocate space for the MCH regs if needed, return nonzero on error */
 static int
 intel_alloc_mchbar_resource(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp_lo, temp_hi = 0;
 	u64 mchbar_addr;
 	int ret;
 	if (INTEL_INFO(dev)->gen >= 4)
 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
 #ifdef CONFIG_PNP
 	if (mchbar_addr &&
 	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 		return 0;
 #endif
 	/* Get some space for it */
 	dev_priv->mch_res.name = "i915 MCHBAR";
 	dev_priv->mch_res.flags = IORESOURCE_MEM;
 	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 				     &dev_priv->mch_res,
 				     MCHBAR_SIZE, MCHBAR_SIZE,
 				     PCIBIOS_MIN_MEM,
 , pcibios_align_resource,
 				     dev_priv->bridge_dev);
 	if (ret) {
 		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 		dev_priv->mch_res.start = 0;
 		return ret;
+	}
 	if (INTEL_INFO(dev)->gen >= 4)
 		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 				       upper_32_bits(dev_priv->mch_res.start));
 	pci_write_config_dword(dev_priv->bridge_dev, reg,
 			       lower_32_bits(dev_priv->mch_res.start));
 	return 0;
+}
 /* Setup MCHBAR if possible, return true if we should disable it again */
 static void
 intel_setup_mchbar(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	bool enabled;
 	dev_priv->mchbar_need_disable = false;
 	if (IS_I915G(dev) || IS_I915GM(dev)) {
 		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 		enabled = !!(temp & DEVEN_MCHBAR_EN);
 	} else {
 		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 		enabled = temp & 1;
+	}
 	/* If it's already enabled, don't have to do anything */
 	if (enabled)
 		return;
 	if (intel_alloc_mchbar_resource(dev))
 		return;
 	dev_priv->mchbar_need_disable = true;
 	/* Space is allocated or reserved, so enable it. */
 	if (IS_I915G(dev) || IS_I915GM(dev)) {
 		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 				       temp | DEVEN_MCHBAR_EN);
 	} else {
 		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
+	}
+}
 static void
 intel_teardown_mchbar(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	if (dev_priv->mchbar_need_disable) {
 		if (IS_I915G(dev) || IS_I915GM(dev)) {
 			pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 			temp &= ~DEVEN_MCHBAR_EN;
 			pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 		} else {
 			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 			temp &= ~1;
 			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
+		}
+	}
 	if (dev_priv->mch_res.start)
 		release_resource(&dev_priv->mch_res);
+}
 #ifndef __NetBSD__  /* XXX vga */
 /* true = enable decode, false = disable decoder */
 static unsigned int i915_vga_set_decode(void *cookie, bool state)
+{
 	struct drm_device *dev = cookie;
 	intel_modeset_vga_set_state(dev, state);
 	if (state)
 		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 	else
 		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+}
 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
+{
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 	if (state == VGA_SWITCHEROO_ON) {
 		pr_info("switched on\n");
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		/* i915 resume handler doesn't set to D0 */
 		pci_set_power_state(dev->pdev, PCI_D0);
 		i915_resume(dev);
 		dev->switch_power_state = DRM_SWITCH_POWER_ON;
 	} else {
 		pr_err("switched off\n");
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		i915_suspend(dev, pmm);
 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
+	}
+}
 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
+{
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	bool can_switch;
 	spin_lock(&dev->count_lock);
 	can_switch = (dev->open_count == 0);
 	spin_unlock(&dev->count_lock);
 	return can_switch;
+}
 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 	.set_gpu_state = i915_switcheroo_set_state,
 	.reprobe = NULL,
 	.can_switch = i915_switcheroo_can_switch,
 };
 #endif
 static int i915_load_modeset_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ret = intel_parse_bios(dev);
 	if (ret)
 		DRM_INFO("failed to find VBIOS tables\n");
 #ifndef __NetBSD__		/* XXX vga */
 	/* If we have > 1 VGA cards, then we need to arbitrate access
 	 * to the common VGA resources.
+	 *
 	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 	 * then we do not take part in VGA arbitration and the
 	 * vga_client_register() fails with -ENODEV.
 	 */
 	ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 	if (ret && ret != -ENODEV)
 		goto out;
 #endif
 	intel_register_dsm_handler();
 #ifndef __NetBSD__		/* XXX vga */
 	ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
 	if (ret)
 		goto cleanup_vga_client;
 #endif
 	/* Initialise stolen first so that we may reserve preallocated
 	 * objects for the BIOS to KMS transition.
 	 */
 	ret = i915_gem_init_stolen(dev);
 	if (ret)
 		goto cleanup_vga_switcheroo;
 	intel_modeset_init(dev);
 	ret = i915_gem_init(dev);
 	if (ret)
 		goto cleanup_gem_stolen;
 	intel_modeset_gem_init(dev);
 	INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
 	ret = drm_irq_install(dev);
 	if (ret)
 		goto cleanup_gem;
 	/* Always safe in the mode setting case. */
 	/* FIXME: do pre/post-mode set stuff in core KMS code */
 	dev->vblank_disable_allowed = 1;
 #ifndef __NetBSD__		/* XXX fb */
 	ret = intel_fbdev_init(dev);
 	if (ret)
 		goto cleanup_irq;
 #endif
 	drm_kms_helper_poll_init(dev);
 	/* We're off and running w/KMS */
 	dev_priv->mm.suspended = 0;
 	return 0;
 #ifndef __NetBSD__		/* XXX fb */
 cleanup_irq:
 	drm_irq_uninstall(dev);
 #endif
 cleanup_gem:
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_cleanup_ringbuffer(dev);
 	mutex_unlock(&dev->struct_mutex);
 	i915_gem_cleanup_aliasing_ppgtt(dev);
 cleanup_gem_stolen:
 	i915_gem_cleanup_stolen(dev);
 cleanup_vga_switcheroo:
 #ifndef __NetBSD__		/* XXX vga */
 	vga_switcheroo_unregister_client(dev->pdev);
 cleanup_vga_client:
 	vga_client_register(dev->pdev, NULL, NULL, NULL);
 out:
 #endif
 	return ret;
+}
 int i915_master_create(struct drm_device *dev, struct drm_master *master)
+{
 	struct drm_i915_master_private *master_priv;
 	master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
 	if (!master_priv)
 		return -ENOMEM;
 	master->driver_priv = master_priv;
 	return 0;
+}
 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
+{
 	struct drm_i915_master_private *master_priv = master->driver_priv;
 	if (!master_priv)
 		return;
 	kfree(master_priv);
 	master->driver_priv = NULL;
+}
 static void
 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
 		unsigned long size)
+{
 	dev_priv->mm.gtt_mtrr = -1;
 #if defined(CONFIG_X86_PAT)
 	if (cpu_has_pat)
 		return;
 #endif
 	/* Set up a WC MTRR for non-PAT systems.  This is more common than
 	 * one would think, because the kernel disables PAT on first
 	 * generation Core chips because WC PAT gets overridden by a UC
 	 * MTRR if present.  Even if a UC MTRR isn't present.
 	 */
 	dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
 	if (dev_priv->mm.gtt_mtrr < 0) {
 		DRM_INFO("MTRR allocation failed.  Graphics "
 			 "performance may suffer.\n");
+	}
+}
 #ifndef __NetBSD__		/* XXX fb */
 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
+{
 	struct apertures_struct *ap;
 	struct pci_dev *pdev = dev_priv->dev->pdev;
 	bool primary;
 	ap = alloc_apertures(1);
 	if (!ap)
 		return;
 	ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
 	ap->ranges[0].size =
 		dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 	primary =
 		pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 	remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 	kfree(ap);
+}
 #endif
 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
+{
 	const struct intel_device_info *info = dev_priv->info;
 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
 #define DEV_INFO_SEP ,
 	DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
 			 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 			 info->gen,
 			 dev_priv->dev->pdev->device,
 			 DEV_INFO_FLAGS);
 #undef DEV_INFO_FLAG
 #undef DEV_INFO_SEP
+}
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
  * @flags: startup flags
+ *
  * The driver load routine has to do several things:
  *   - drive output discovery via intel_modeset_init()
  *   - initialize the memory manager
  *   - allocate initial config memory
  *   - setup the DRM framebuffer with the allocated memory
  */
 int i915_driver_load(struct drm_device *dev, unsigned long flags)
+{
 	struct drm_i915_private *dev_priv;
 	struct intel_device_info *info;
 	int ret = 0, mmio_bar, mmio_size;
 	uint32_t aperture_size;
 	info = (struct intel_device_info *) flags;
 	/* Refuse to load on gen6+ without kms enabled. */
 	if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	/* i915 has 4 more counters */
 	dev->counters += 4;
 	dev->types[6] = _DRM_STAT_IRQ;
 	dev->types[7] = _DRM_STAT_PRIMARY;
 	dev->types[8] = _DRM_STAT_SECONDARY;
 	dev->types[9] = _DRM_STAT_DMA;
 	dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
 	if (dev_priv == NULL)
 		return -ENOMEM;
 	dev->dev_private = (void *)dev_priv;
 	dev_priv->dev = dev;
 	dev_priv->info = info;
 	i915_dump_device_info(dev_priv);
 	if (i915_get_bridge_dev(dev)) {
 		ret = -EIO;
 		goto free_priv;
+	}
 	ret = i915_gem_gtt_init(dev);
 	if (ret)
 		goto put_bridge;
 #ifndef __NetBSD__		/* XXX fb */
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		i915_kick_out_firmware_fb(dev_priv);
 #endif
 	pci_set_master(dev->pdev);
 	/* overlay on gen2 is broken and can't address above 1G */
 	if (IS_GEN2(dev))
 		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
 	 * using 32bit addressing, overwriting memory if HWS is located
 	 * above 4GB.
+	 *
 	 * The documentation also mentions an issue with undefined
 	 * behaviour if any general state is accessed within a page above 4GB,
 	 * which also needs to be handled carefully.
 	 */
 	if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 	mmio_bar = IS_GEN2(dev) ? 1 : 0;
 	/* Before gen4, the registers and the GTT are behind different BARs.
 	 * However, from gen4 onwards, the registers and the GTT are shared
 	 * in the same BAR, so we want to restrict this ioremap from
 	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
 	 */
 	if (info->gen < 5)
 		mmio_size = 512*1024;
 	else
 		mmio_size = 2*1024*1024;
 #ifdef __NetBSD__
 	/* XXX Maybe it would be better to just use pci_mapreg_map...  */
+	{
 		bus_addr_t addr;
 		bus_size_t size;
 		if (pci_mapreg_info(dev->pdev->pd_pa.pa_pc,
 			dev->pdev->pd_pa.pa_tag, mmio_bar, PCI_MAPREG_TYPE_MEM,
 			&addr, &size, NULL /* XXX flags? */)) {
 			ret = -EIO;	    /* XXX */
 			goto put_gmch;
+		}
 		ret = drm_addmap(dev, addr, size, _DRM_REGISTERS,
 		    (_DRM_KERNEL | _DRM_DRIVER), &dev_priv->regs_map);
 		if (ret)
 			goto put_gmch;
+	}
 #else
 	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 	if (!dev_priv->regs) {
 		DRM_ERROR("failed to map registers\n");
 		ret = -EIO;
 		goto put_gmch;
+	}
 #endif
 	aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 	dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
 	dev_priv->mm.gtt_mapping =
 		io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
 				     aperture_size);
 	if (dev_priv->mm.gtt_mapping == NULL) {
 		ret = -EIO;
 		goto out_rmmap;
+	}
 	i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
 			aperture_size);
 	/* The i915 workqueue is primarily used for batched retirement of
 	 * requests (and thus managing bo) once the task has been completed
 	 * by the GPU. i915_gem_retire_requests() is called directly when we
 	 * need high-priority retirement, such as waiting for an explicit
 	 * bo.
+	 *
 	 * It is also used for periodic low-priority events, such as
 	 * idle-timers and recording error state.
+	 *
 	 * All tasks on the workqueue are expected to acquire the dev mutex
 	 * so there is no point in running more than one instance of the
 	 * workqueue at any time.  Use an ordered one.
 	 */
 	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 	if (dev_priv->wq == NULL) {
 		DRM_ERROR("Failed to create our workqueue.\n");
 		ret = -ENOMEM;
 		goto out_mtrrfree;
+	}
 	/* This must be called before any calls to HAS_PCH_* */
 	intel_detect_pch(dev);
 	intel_irq_init(dev);
 	intel_gt_init(dev);
 	/* Try to make sure MCHBAR is enabled before poking at it */
 	intel_setup_mchbar(dev);
 	intel_setup_gmbus(dev);
 	intel_opregion_setup(dev);
 	intel_setup_bios(dev);
 	i915_gem_load(dev);
 	/* On the 945G/GM, the chipset reports the MSI capability on the
 	 * integrated graphics even though the support isn't actually there
 	 * according to the published specs.  It doesn't appear to function
 	 * correctly in testing on 945G.
 	 * This may be a side effect of MSI having been made available for PEG
 	 * and the registers being closely associated.
+	 *
 	 * According to chipset errata, on the 965GM, MSI interrupts may
 	 * be lost or delayed, but we use them anyways to avoid
 	 * stuck interrupts on some machines.
 	 */
 	if (!IS_I945G(dev) && !IS_I945GM(dev))
 		pci_enable_msi(dev->pdev);
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->error_lock);
 	spin_lock_init(&dev_priv->rps.lock);
 	spin_lock_init(&dev_priv->dpio_lock);
 	mutex_init(&dev_priv->rps.hw_lock);
 	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 		dev_priv->num_pipe = 3;
 	else if (IS_MOBILE(dev) || !IS_GEN2(dev))
 		dev_priv->num_pipe = 2;
 	else
 		dev_priv->num_pipe = 1;
 	ret = drm_vblank_init(dev, dev_priv->num_pipe);
 	if (ret)
 		goto out_gem_unload;
 	/* Start out suspended */
 	dev_priv->mm.suspended = 1;
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		ret = i915_load_modeset_init(dev);
 		if (ret < 0) {
 			DRM_ERROR("failed to init modeset\n");
 			goto out_gem_unload;
+		}
+	}
 	i915_setup_sysfs(dev);
 	/* Must be done after probing outputs */
 	intel_opregion_init(dev);
 	acpi_video_register();
 	setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
 		    (unsigned long) dev);
 	if (IS_GEN5(dev))
 		intel_gpu_ips_init(dev_priv);
 	return 0;
 out_gem_unload:
 	if (dev_priv->mm.inactive_shrinker.shrink)
 		unregister_shrinker(&dev_priv->mm.inactive_shrinker);
 	if (dev->pdev->msi_enabled)
 		pci_disable_msi(dev->pdev);
 	intel_teardown_gmbus(dev);
 	intel_teardown_mchbar(dev);
 	destroy_workqueue(dev_priv->wq);
 out_mtrrfree:
 	if (dev_priv->mm.gtt_mtrr >= 0) {
 		mtrr_del(dev_priv->mm.gtt_mtrr,
 			 dev_priv->mm.gtt_base_addr,
 			 aperture_size);
 		dev_priv->mm.gtt_mtrr = -1;
+	}
 	io_mapping_free(dev_priv->mm.gtt_mapping);
 out_rmmap:
 #ifdef __NetBSD__
 	(void)drm_rmmap(dev, dev_priv->regs_map);
 #else
 	pci_iounmap(dev->pdev, dev_priv->regs);
 #endif
 put_gmch:
 	i915_gem_gtt_fini(dev);
 put_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
 free_priv:
 	kfree(dev_priv);
 	return ret;
+}
 int i915_driver_unload(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	intel_gpu_ips_teardown();
 	i915_teardown_sysfs(dev);
 	if (dev_priv->mm.inactive_shrinker.shrink)
 		unregister_shrinker(&dev_priv->mm.inactive_shrinker);
 	mutex_lock(&dev->struct_mutex);
 	ret = i915_gpu_idle(dev);
 	if (ret)
 		DRM_ERROR("failed to idle hardware: %d\n", ret);
 	i915_gem_retire_requests(dev);
 	mutex_unlock(&dev->struct_mutex);
 	/* Cancel the retire work handler, which should be idle now. */
 	cancel_delayed_work_sync(&dev_priv->mm.retire_work);
 	io_mapping_free(dev_priv->mm.gtt_mapping);
 	if (dev_priv->mm.gtt_mtrr >= 0) {
 		mtrr_del(dev_priv->mm.gtt_mtrr,
 			 dev_priv->mm.gtt_base_addr,
 			 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
 		dev_priv->mm.gtt_mtrr = -1;
+	}
 	acpi_video_unregister();
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 #ifndef __NetBSD__		/* XXX fb */
 		intel_fbdev_fini(dev);
 #endif
 		intel_modeset_cleanup(dev);
 		cancel_work_sync(&dev_priv->console_resume_work);
 		/*
 		 * free the memory space allocated for the child device
 		 * config parsed from VBT
 		 */
 		if (dev_priv->child_dev && dev_priv->child_dev_num) {
 			kfree(dev_priv->child_dev);
 			dev_priv->child_dev = NULL;
 			dev_priv->child_dev_num = 0;
+		}
 #ifndef __NetBSD__		/* XXX vga */
 		vga_switcheroo_unregister_client(dev->pdev);
 		vga_client_register(dev->pdev, NULL, NULL, NULL);
 #endif
+	}
 	/* Free error state after interrupts are fully disabled. */
 	del_timer_sync(&dev_priv->hangcheck_timer);
 	cancel_work_sync(&dev_priv->error_work);
 	i915_destroy_error_state(dev);

 @@ -32,2006 +32,2016 @@
 #include "intel_drv.h"
 #include <linux/shmem_fs.h>
 #include <linux/slab.h>
 #include <linux/swap.h>
 #include <linux/pci.h>
 #include <linux/dma-buf.h>
 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
 						    unsigned alignment,
 						    bool map_and_fenceable,
 						    bool nonblocking);
 static int i915_gem_phys_pwrite(struct drm_device *dev,
 				struct drm_i915_gem_object *obj,
 				struct drm_i915_gem_pwrite *args,
 				struct drm_file *file);
 static void i915_gem_write_fence(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj);
 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
 					 struct drm_i915_fence_reg *fence,
 					 bool enable);
 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
 				    struct shrink_control *sc);
 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
+{
 	if (obj->tiling_mode)
 		i915_gem_release_mmap(obj);
 	/* As we do not have an associated fence register, we will force
 	 * a tiling change if we ever need to acquire one.
 	 */
 	obj->fence_dirty = false;
 	obj->fence_reg = I915_FENCE_REG_NONE;
+}
 /* some bookkeeping */
 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
 				  size_t size)
+{
 	dev_priv->mm.object_count++;
 	dev_priv->mm.object_memory += size;
+}
 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 				     size_t size)
+{
 	dev_priv->mm.object_count--;
 	dev_priv->mm.object_memory -= size;
+}
 static int
 i915_gem_wait_for_error(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct completion *x = &dev_priv->error_completion;
 	unsigned long flags;
 	int ret;
 	if (!atomic_read(&dev_priv->mm.wedged))
 		return 0;
 	/*
 	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 	 * userspace. If it takes that long something really bad is going on and
 	 * we should simply try to bail out and fail as gracefully as possible.
 	 */
 	ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
 	if (ret == 0) {
 		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 		return -EIO;
 	} else if (ret < 0) {
 		return ret;
+	}
 	if (atomic_read(&dev_priv->mm.wedged)) {
 		/* GPU is hung, bump the completion count to account for
 		 * the token we just consumed so that we never hit zero and
 		 * end up waiting upon a subsequent completion event that
 		 * will never happen.
 		 */
 		spin_lock_irqsave(&x->wait.lock, flags);
 		x->done++;
 		spin_unlock_irqrestore(&x->wait.lock, flags);
+	}
 	return 0;
+}
 int i915_mutex_lock_interruptible(struct drm_device *dev)
+{
 	int ret;
 	ret = i915_gem_wait_for_error(dev);
 	if (ret)
 		return ret;
 	ret = mutex_lock_interruptible(&dev->struct_mutex);
 	if (ret)
 		return ret;
 	WARN_ON(i915_verify_lists(dev));
 	return 0;
+}
 static inline bool
 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
+{
 	return obj->gtt_space && !obj->active;
+}
 int
 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 		    struct drm_file *file)
+{
 	struct drm_i915_gem_init *args = data;
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	if (args->gtt_start >= args->gtt_end ||
 	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 		return -EINVAL;
 	/* GEM with user mode setting was never supported on ilk and later. */
 	if (INTEL_INFO(dev)->gen >= 5)
 		return -ENODEV;
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_init_global_gtt(dev, args->gtt_start,
 				 args->gtt_end, args->gtt_end);
 	mutex_unlock(&dev->struct_mutex);
 	return 0;
+}
 int
 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 			    struct drm_file *file)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_get_aperture *args = data;
 	struct drm_i915_gem_object *obj;
 	size_t pinned;
 	pinned = 0;
 	mutex_lock(&dev->struct_mutex);
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
 		if (obj->pin_count)
 			pinned += obj->gtt_space->size;
 	mutex_unlock(&dev->struct_mutex);
 	args->aper_size = dev_priv->mm.gtt_total;
 	args->aper_available_size = args->aper_size - pinned;
 	return 0;
+}
 static int
 i915_gem_create(struct drm_file *file,
 		struct drm_device *dev,
 		uint64_t size,
 		uint32_t *handle_p)
+{
 	struct drm_i915_gem_object *obj;
 	int ret;
 	u32 handle;
 	size = roundup(size, PAGE_SIZE);
 	if (size == 0)
 		return -EINVAL;
 	/* Allocate the new object */
 	obj = i915_gem_alloc_object(dev, size);
 	if (obj == NULL)
 		return -ENOMEM;
 	ret = drm_gem_handle_create(file, &obj->base, &handle);
 	if (ret) {
 		drm_gem_object_release(&obj->base);
 		i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 		kfree(obj);
 		return ret;
+	}
 	/* drop reference from allocate - handle holds it now */
 	drm_gem_object_unreference(&obj->base);
 	trace_i915_gem_object_create(obj);
 	*handle_p = handle;
 	return 0;
+}
 int
 i915_gem_dumb_create(struct drm_file *file,
 		     struct drm_device *dev,
 		     struct drm_mode_create_dumb *args)
+{
 	/* have to work out size/pitch and return them */
 	args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 	args->size = args->pitch * args->height;
 	return i915_gem_create(file, dev,
 			       args->size, &args->handle);
+}
 int i915_gem_dumb_destroy(struct drm_file *file,
 			  struct drm_device *dev,
 			  uint32_t handle)
+{
 	return drm_gem_handle_delete(file, handle);
+}
 /**
  * Creates a new mm object and returns a handle to it.
  */
 int
 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 		      struct drm_file *file)
+{
 	struct drm_i915_gem_create *args = data;
 	return i915_gem_create(file, dev,
 			       args->size, &args->handle);
+}
 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
+{
 	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 		obj->tiling_mode != I915_TILING_NONE;
+}
 static inline int
 __copy_to_user_swizzled(char __user *cpu_vaddr,
 			const char *gpu_vaddr, int gpu_offset,
 			int length)
+{
 	int ret, cpu_offset = 0;
 	while (length > 0) {
 		int cacheline_end = ALIGN(gpu_offset + 1, 64);
 		int this_length = min(cacheline_end - gpu_offset, length);
 		int swizzled_gpu_offset = gpu_offset ^ 64;
 		ret = __copy_to_user(cpu_vaddr + cpu_offset,
 				     gpu_vaddr + swizzled_gpu_offset,
 				     this_length);
 		if (ret)
 			return ret + length;
 		cpu_offset += this_length;
 		gpu_offset += this_length;
 		length -= this_length;
+	}
 	return 0;
+}
 static inline int
 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 			  const char __user *cpu_vaddr,
 			  int length)
+{
 	int ret, cpu_offset = 0;
 	while (length > 0) {
 		int cacheline_end = ALIGN(gpu_offset + 1, 64);
 		int this_length = min(cacheline_end - gpu_offset, length);
 		int swizzled_gpu_offset = gpu_offset ^ 64;
 		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 				       cpu_vaddr + cpu_offset,
 				       this_length);
 		if (ret)
 			return ret + length;
 		cpu_offset += this_length;
 		gpu_offset += this_length;
 		length -= this_length;
+	}
 	return 0;
+}
 /* Per-page copy function for the shmem pread fastpath.
  * Flushes invalid cachelines before reading the target if
  * needs_clflush is set. */
 static int
 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 		 char __user *user_data,
 		 bool page_do_bit17_swizzling, bool needs_clflush)
+{
 	char *vaddr;
 	int ret;
 	if (unlikely(page_do_bit17_swizzling))
 		return -EINVAL;
 	vaddr = kmap_atomic(page);
 	if (needs_clflush)
 		drm_clflush_virt_range(vaddr + shmem_page_offset,
 				       page_length);
 	ret = __copy_to_user_inatomic(user_data,
 				      vaddr + shmem_page_offset,
 				      page_length);
 	kunmap_atomic(vaddr);
 	return ret ? -EFAULT : 0;
+}
 static void
 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 			     bool swizzled)
+{
 	if (unlikely(swizzled)) {
 		unsigned long start = (unsigned long) addr;
 		unsigned long end = (unsigned long) addr + length;
 		/* For swizzling simply ensure that we always flush both
 		 * channels. Lame, but simple and it works. Swizzled
 		 * pwrite/pread is far from a hotpath - current userspace
 		 * doesn't use it at all. */
 		start = round_down(start, 128);
 		end = round_up(end, 128);
 		drm_clflush_virt_range((void *)start, end - start);
 	} else {
 		drm_clflush_virt_range(addr, length);
+	}
+}
 /* Only difference to the fast-path function is that this can handle bit17
  * and uses non-atomic copy and kmap functions. */
 static int
 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 		 char __user *user_data,
 		 bool page_do_bit17_swizzling, bool needs_clflush)
+{
 	char *vaddr;
 	int ret;
 	vaddr = kmap(page);
 	if (needs_clflush)
 		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 					     page_length,
 					     page_do_bit17_swizzling);
 	if (page_do_bit17_swizzling)
 		ret = __copy_to_user_swizzled(user_data,
 					      vaddr, shmem_page_offset,
 					      page_length);
 	else
 		ret = __copy_to_user(user_data,
 				     vaddr + shmem_page_offset,
 				     page_length);
 	kunmap(page);
 	return ret ? - EFAULT : 0;
+}
 static int
 i915_gem_shmem_pread(struct drm_device *dev,
 		     struct drm_i915_gem_object *obj,
 		     struct drm_i915_gem_pread *args,
 		     struct drm_file *file)
+{
 	char __user *user_data;
 	ssize_t remain;
 	loff_t offset;
 	int shmem_page_offset, page_length, ret = 0;
 	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 	int hit_slowpath = 0;
 	int prefaulted = 0;
 	int needs_clflush = 0;
 	struct scatterlist *sg;
 	int i;
 	user_data = (char __user *) (uintptr_t) args->data_ptr;
 	remain = args->size;
 	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 		/* If we're not in the cpu read domain, set ourself into the gtt
 		 * read domain and manually flush cachelines (if required). This
 		 * optimizes for the case when the gpu will dirty the data
 		 * anyway again before the next pread happens. */
 		if (obj->cache_level == I915_CACHE_NONE)
 			needs_clflush = 1;
 		if (obj->gtt_space) {
 			ret = i915_gem_object_set_to_gtt_domain(obj, false);
 			if (ret)
 				return ret;
+		}
+	}
 	ret = i915_gem_object_get_pages(obj);
 	if (ret)
 		return ret;
 	i915_gem_object_pin_pages(obj);
 	offset = args->offset;
 	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 		struct page *page;
 		if (i < offset >> PAGE_SHIFT)
 			continue;
 		if (remain <= 0)
 			break;
 		/* Operation in this page
+		 *
 		 * shmem_page_offset = offset within page in shmem file
 		 * page_length = bytes to copy for this page
 		 */
 		shmem_page_offset = offset_in_page(offset);
 		page_length = remain;
 		if ((shmem_page_offset + page_length) > PAGE_SIZE)
 			page_length = PAGE_SIZE - shmem_page_offset;
 		page = sg_page(sg);
 		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 			(page_to_phys(page) & (1 << 17)) != 0;
 		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 				       user_data, page_do_bit17_swizzling,
 				       needs_clflush);
 		if (ret == 0)
 			goto next_page;
 		hit_slowpath = 1;
 		mutex_unlock(&dev->struct_mutex);
 		if (!prefaulted) {
 			ret = fault_in_multipages_writeable(user_data, remain);
 			/* Userspace is tricking us, but we've already clobbered
 			 * its pages with the prefault and promised to write the
 			 * data up to the first fault. Hence ignore any errors
 			 * and just continue. */
 			(void)ret;
 			prefaulted = 1;
+		}
 		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 				       user_data, page_do_bit17_swizzling,
 				       needs_clflush);
 		mutex_lock(&dev->struct_mutex);
 next_page:
 		mark_page_accessed(page);
 		if (ret)
 			goto out;
 		remain -= page_length;
 		user_data += page_length;
 		offset += page_length;
+	}
 out:
 	i915_gem_object_unpin_pages(obj);
 	if (hit_slowpath) {
 		/* Fixup: Kill any reinstated backing storage pages */
 		if (obj->madv == __I915_MADV_PURGED)
 			i915_gem_object_truncate(obj);
+	}
 	return ret;
+}
 /**
  * Reads data from the object referenced by handle.
+ *
  * On error, the contents of *data are undefined.
  */
 int
 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 		     struct drm_file *file)
+{
 	struct drm_i915_gem_pread *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret = 0;
 	if (args->size == 0)
 		return 0;
 	if (!access_ok(VERIFY_WRITE,
 		       (char __user *)(uintptr_t)args->data_ptr,
 		       args->size))
 		return -EFAULT;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		return ret;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 	if (&obj->base == NULL) {
 		ret = -ENOENT;
 		goto unlock;
+	}
 	/* Bounds check source.  */
 	if (args->offset > obj->base.size ||
 	    args->size > obj->base.size - args->offset) {
 		ret = -EINVAL;
 		goto out;
+	}
 	/* prime objects have no backing filp to GEM pread/pwrite
 	 * pages from.
 	 */
 	if (!obj->base.filp) {
 		ret = -EINVAL;
 		goto out;
+	}
 	trace_i915_gem_object_pread(obj, args->offset, args->size);
 	ret = i915_gem_shmem_pread(dev, obj, args, file);
 out:
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 /* This is the fast write path which cannot handle
  * page faults in the source data
  */
 static inline int
 fast_user_write(struct io_mapping *mapping,
 		loff_t page_base, int page_offset,
 		char __user *user_data,
 		int length)
+{
 	void __iomem *vaddr_atomic;
 	void *vaddr;
 	unsigned long unwritten;
 	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 	/* We can use the cpu mem copy function because this is X86. */
 	vaddr = (void __force*)vaddr_atomic + page_offset;
 	unwritten = __copy_from_user_inatomic_nocache(vaddr,
 						      user_data, length);
 	io_mapping_unmap_atomic(vaddr_atomic);
 	return unwritten;
+}
 /**
  * This is the fast pwrite path, where we copy the data directly from the
  * user into the GTT, uncached.
  */
 static int
 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 			 struct drm_i915_gem_object *obj,
 			 struct drm_i915_gem_pwrite *args,
 			 struct drm_file *file)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	ssize_t remain;
 	loff_t offset, page_base;
 	char __user *user_data;
 	int page_offset, page_length, ret;
 	ret = i915_gem_object_pin(obj, 0, true, true);
 	if (ret)
 		goto out;
 	ret = i915_gem_object_set_to_gtt_domain(obj, true);
 	if (ret)
 		goto out_unpin;
 	ret = i915_gem_object_put_fence(obj);
 	if (ret)
 		goto out_unpin;
 	user_data = (char __user *) (uintptr_t) args->data_ptr;
 	remain = args->size;
 	offset = obj->gtt_offset + args->offset;
 	while (remain > 0) {
 		/* Operation in this page
+		 *
 		 * page_base = page offset within aperture
 		 * page_offset = offset within page
 		 * page_length = bytes to copy for this page
 		 */
 		page_base = offset & PAGE_MASK;
 		page_offset = offset_in_page(offset);
 		page_length = remain;
 		if ((page_offset + remain) > PAGE_SIZE)
 			page_length = PAGE_SIZE - page_offset;
 		/* If we get a fault while copying data, then (presumably) our
 		 * source page isn't available.  Return the error and we'll
 		 * retry in the slow path.
 		 */
 		if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 				    page_offset, user_data, page_length)) {
 			ret = -EFAULT;
 			goto out_unpin;
+		}
 		remain -= page_length;
 		user_data += page_length;
 		offset += page_length;
+	}
 out_unpin:
 	i915_gem_object_unpin(obj);
 out:
 	return ret;
+}
 /* Per-page copy function for the shmem pwrite fastpath.
  * Flushes invalid cachelines before writing to the target if
  * needs_clflush_before is set and flushes out any written cachelines after
  * writing if needs_clflush is set. */
 static int
 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 		  char __user *user_data,
 		  bool page_do_bit17_swizzling,
 		  bool needs_clflush_before,
 		  bool needs_clflush_after)
+{
 	char *vaddr;
 	int ret;
 	if (unlikely(page_do_bit17_swizzling))
 		return -EINVAL;
 	vaddr = kmap_atomic(page);
 	if (needs_clflush_before)
 		drm_clflush_virt_range(vaddr + shmem_page_offset,
 				       page_length);
 	ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 						user_data,
 						page_length);
 	if (needs_clflush_after)
 		drm_clflush_virt_range(vaddr + shmem_page_offset,
 				       page_length);
 	kunmap_atomic(vaddr);
 	return ret ? -EFAULT : 0;
+}
 /* Only difference to the fast-path function is that this can handle bit17
  * and uses non-atomic copy and kmap functions. */
 static int
 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 		  char __user *user_data,
 		  bool page_do_bit17_swizzling,
 		  bool needs_clflush_before,
 		  bool needs_clflush_after)
+{
 	char *vaddr;
 	int ret;
 	vaddr = kmap(page);
 	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 					     page_length,
 					     page_do_bit17_swizzling);
 	if (page_do_bit17_swizzling)
 		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 						user_data,
 						page_length);
 	else
 		ret = __copy_from_user(vaddr + shmem_page_offset,
 				       user_data,
 				       page_length);
 	if (needs_clflush_after)
 		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 					     page_length,
 					     page_do_bit17_swizzling);
 	kunmap(page);
 	return ret ? -EFAULT : 0;
+}
 static int
 i915_gem_shmem_pwrite(struct drm_device *dev,
 		      struct drm_i915_gem_object *obj,
 		      struct drm_i915_gem_pwrite *args,
 		      struct drm_file *file)
+{
 	ssize_t remain;
 	loff_t offset;
 	char __user *user_data;
 	int shmem_page_offset, page_length, ret = 0;
 	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 	int hit_slowpath = 0;
 	int needs_clflush_after = 0;
 	int needs_clflush_before = 0;
 	int i;
 	struct scatterlist *sg;
 	user_data = (char __user *) (uintptr_t) args->data_ptr;
 	remain = args->size;
 	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 		/* If we're not in the cpu write domain, set ourself into the gtt
 		 * write domain and manually flush cachelines (if required). This
 		 * optimizes for the case when the gpu will use the data
 		 * right away and we therefore have to clflush anyway. */
 		if (obj->cache_level == I915_CACHE_NONE)
 			needs_clflush_after = 1;
 		if (obj->gtt_space) {
 			ret = i915_gem_object_set_to_gtt_domain(obj, true);
 			if (ret)
 				return ret;
+		}
+	}
 	/* Same trick applies for invalidate partially written cachelines before
 	 * writing.  */
 	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 	    && obj->cache_level == I915_CACHE_NONE)
 		needs_clflush_before = 1;
 	ret = i915_gem_object_get_pages(obj);
 	if (ret)
 		return ret;
 	i915_gem_object_pin_pages(obj);
 	offset = args->offset;
 	obj->dirty = 1;
 	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 		struct page *page;
 		int partial_cacheline_write;
 		if (i < offset >> PAGE_SHIFT)
 			continue;
 		if (remain <= 0)
 			break;
 		/* Operation in this page
+		 *
 		 * shmem_page_offset = offset within page in shmem file
 		 * page_length = bytes to copy for this page
 		 */
 		shmem_page_offset = offset_in_page(offset);
 		page_length = remain;
 		if ((shmem_page_offset + page_length) > PAGE_SIZE)
 			page_length = PAGE_SIZE - shmem_page_offset;
 		/* If we don't overwrite a cacheline completely we need to be
 		 * careful to have up-to-date data by first clflushing. Don't
 		 * overcomplicate things and flush the entire patch. */
 		partial_cacheline_write = needs_clflush_before &&
 			((shmem_page_offset | page_length)
 				& (boot_cpu_data.x86_clflush_size - 1));
 		page = sg_page(sg);
 		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 			(page_to_phys(page) & (1 << 17)) != 0;
 		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 					user_data, page_do_bit17_swizzling,
 					partial_cacheline_write,
 					needs_clflush_after);
 		if (ret == 0)
 			goto next_page;
 		hit_slowpath = 1;
 		mutex_unlock(&dev->struct_mutex);
 		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 					user_data, page_do_bit17_swizzling,
 					partial_cacheline_write,
 					needs_clflush_after);
 		mutex_lock(&dev->struct_mutex);
 next_page:
 		set_page_dirty(page);
 		mark_page_accessed(page);
 		if (ret)
 			goto out;
 		remain -= page_length;
 		user_data += page_length;
 		offset += page_length;
+	}
 out:
 	i915_gem_object_unpin_pages(obj);
 	if (hit_slowpath) {
 		/* Fixup: Kill any reinstated backing storage pages */
 		if (obj->madv == __I915_MADV_PURGED)
 			i915_gem_object_truncate(obj);
 		/* and flush dirty cachelines in case the object isn't in the cpu write
 		 * domain anymore. */
 		if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 			i915_gem_clflush_object(obj);
 			i915_gem_chipset_flush(dev);
+		}
+	}
 	if (needs_clflush_after)
 		i915_gem_chipset_flush(dev);
 	return ret;
+}
 /**
  * Writes data to the object referenced by handle.
+ *
  * On error, the contents of the buffer that were to be modified are undefined.
  */
 int
 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 		      struct drm_file *file)
+{
 	struct drm_i915_gem_pwrite *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	if (args->size == 0)
 		return 0;
 	if (!access_ok(VERIFY_READ,
 		       (char __user *)(uintptr_t)args->data_ptr,
 		       args->size))
 		return -EFAULT;
 	ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
 					   args->size);
 	if (ret)
 		return -EFAULT;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		return ret;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 	if (&obj->base == NULL) {
 		ret = -ENOENT;
 		goto unlock;
+	}
 	/* Bounds check destination. */
 	if (args->offset > obj->base.size ||
 	    args->size > obj->base.size - args->offset) {
 		ret = -EINVAL;
 		goto out;
+	}
 	/* prime objects have no backing filp to GEM pread/pwrite
 	 * pages from.
 	 */
 	if (!obj->base.filp) {
 		ret = -EINVAL;
 		goto out;
+	}
 	trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 	ret = -EFAULT;
 	/* We can only do the GTT pwrite on untiled buffers, as otherwise
 	 * it would end up going through the fenced access, and we'll get
 	 * different detiling behavior between reading and writing.
 	 * pread/pwrite currently are reading and writing from the CPU
 	 * perspective, requiring manual detiling by the client.
 	 */
 	if (obj->phys_obj) {
 		ret = i915_gem_phys_pwrite(dev, obj, args, file);
 		goto out;
+	}
 	if (obj->cache_level == I915_CACHE_NONE &&
 	    obj->tiling_mode == I915_TILING_NONE &&
 	    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 		/* Note that the gtt paths might fail with non-page-backed user
 		 * pointers (e.g. gtt mappings when moving data between
 		 * textures). Fallback to the shmem path in that case. */
+	}
 	if (ret == -EFAULT || ret == -ENOSPC)
 		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 out:
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 int
 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
 		     bool interruptible)
+{
 	if (atomic_read(&dev_priv->mm.wedged)) {
 		struct completion *x = &dev_priv->error_completion;
 		bool recovery_complete;
 		unsigned long flags;
 		/* Give the error handler a chance to run. */
 		spin_lock_irqsave(&x->wait.lock, flags);
 		recovery_complete = x->done > 0;
 		spin_unlock_irqrestore(&x->wait.lock, flags);
 		/* Non-interruptible callers can't handle -EAGAIN, hence return
 		 * -EIO unconditionally for these. */
 		if (!interruptible)
 			return -EIO;
 		/* Recovery complete, but still wedged means reset failure. */
 		if (recovery_complete)
 			return -EIO;
 		return -EAGAIN;
+	}
 	return 0;
+}
 /*
  * Compare seqno against outstanding lazy request. Emit a request if they are
  * equal.
  */
 static int
 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
+{
 	int ret;
 	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 	ret = 0;
 	if (seqno == ring->outstanding_lazy_request)
 		ret = i915_add_request(ring, NULL, NULL);
 	return ret;
+}
 /**
  * __wait_seqno - wait until execution of seqno has finished
  * @ring: the ring expected to report seqno
  * @seqno: duh!
  * @interruptible: do an interruptible wait (normally yes)
  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
+ *
  * Returns 0 if the seqno was found within the alloted time. Else returns the
  * errno with remaining time filled in timeout argument.
  */
 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 			bool interruptible, struct timespec *timeout)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	struct timespec before, now, wait_time={1,0};
 	unsigned long timeout_jiffies;
 	long end;
 	bool wait_forever = true;
 	int ret;
 	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 		return 0;
 	trace_i915_gem_request_wait_begin(ring, seqno);
 	if (timeout != NULL) {
 		wait_time = *timeout;
 		wait_forever = false;
+	}
 	timeout_jiffies = timespec_to_jiffies(&wait_time);
 	if (WARN_ON(!ring->irq_get(ring)))
 		return -ENODEV;
 	/* Record current time in case interrupted by signal, or wedged * */
 	getrawmonotonic(&before);
 #define EXIT_COND \
 	(i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
 	atomic_read(&dev_priv->mm.wedged))
 	do {
 #ifdef __NetBSD__
 		/*
 		 * XXX This wait is always interruptible; we should
 		 * heed the flag `interruptible'.
 		 */
 		DRM_TIMED_WAIT_UNTIL(end, &ring->irq_queue, &drm_global_mutex,
 		    timeout_jiffies,
 		    EXIT_COND);
 #else
 		if (interruptible)
 			end = wait_event_interruptible_timeout(ring->irq_queue,
 							       EXIT_COND,
 							       timeout_jiffies);
 		else
 			end = wait_event_timeout(ring->irq_queue, EXIT_COND,
 						 timeout_jiffies);
 #endif
 		ret = i915_gem_check_wedge(dev_priv, interruptible);
 		if (ret)
 			end = ret;
 	} while (end == 0 && wait_forever);
 	getrawmonotonic(&now);
 	ring->irq_put(ring);
 	trace_i915_gem_request_wait_end(ring, seqno);
 #undef EXIT_COND
 	if (timeout) {
 		struct timespec sleep_time = timespec_sub(now, before);
 		*timeout = timespec_sub(*timeout, sleep_time);
+	}
 	switch (end) {
 	case -EIO:
 	case -EAGAIN: /* Wedged */
 	case -ERESTARTSYS: /* Signal */
 		return (int)end;
 	case 0: /* Timeout */
 		if (timeout)
 			set_normalized_timespec(timeout, 0, 0);
 		return -ETIME;
 	default: /* Completed */
 		WARN_ON(end < 0); /* We're not aware of other errors */
 		return 0;
+	}
+}
 /**
  * Waits for a sequence number to be signaled, and cleans up the
  * request and object lists appropriately for that event.
  */
 int
 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
+{
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	bool interruptible = dev_priv->mm.interruptible;
 	int ret;
 	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 	BUG_ON(seqno == 0);
 	ret = i915_gem_check_wedge(dev_priv, interruptible);
 	if (ret)
 		return ret;
 	ret = i915_gem_check_olr(ring, seqno);
 	if (ret)
 		return ret;
 	return __wait_seqno(ring, seqno, interruptible, NULL);
+}
 /**
  * Ensures that all rendering to the object has completed and the object is
  * safe to unbind from the GTT or access from the CPU.
  */
 static __must_check int
 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
 			       bool readonly)
+{
 	struct intel_ring_buffer *ring = obj->ring;
 	u32 seqno;
 	int ret;
 	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
 	if (seqno == 0)
 		return 0;
 	ret = i915_wait_seqno(ring, seqno);
 	if (ret)
 		return ret;
 	i915_gem_retire_requests_ring(ring);
 	/* Manually manage the write flush as we may have not yet
 	 * retired the buffer.
 	 */
 	if (obj->last_write_seqno &&
 	    i915_seqno_passed(seqno, obj->last_write_seqno)) {
 		obj->last_write_seqno = 0;
 		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+	}
 	return 0;
+}
 /* A nonblocking variant of the above wait. This is a highly dangerous routine
  * as the object state may change during this call.
  */
 static __must_check int
 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
 					    bool readonly)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = obj->ring;
 	u32 seqno;
 	int ret;
 	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 	BUG_ON(!dev_priv->mm.interruptible);
 	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
 	if (seqno == 0)
 		return 0;
 	ret = i915_gem_check_wedge(dev_priv, true);
 	if (ret)
 		return ret;
 	ret = i915_gem_check_olr(ring, seqno);
 	if (ret)
 		return ret;
 	mutex_unlock(&dev->struct_mutex);
 	ret = __wait_seqno(ring, seqno, true, NULL);
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_retire_requests_ring(ring);
 	/* Manually manage the write flush as we may have not yet
 	 * retired the buffer.
 	 */
 	if (obj->last_write_seqno &&
 	    i915_seqno_passed(seqno, obj->last_write_seqno)) {
 		obj->last_write_seqno = 0;
 		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+	}
 	return ret;
+}
 /**
  * Called when user space prepares to use an object with the CPU, either
  * through the mmap ioctl's mapping or a GTT mapping.
  */
 int
 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *file)
+{
 	struct drm_i915_gem_set_domain *args = data;
 	struct drm_i915_gem_object *obj;
 	uint32_t read_domains = args->read_domains;
 	uint32_t write_domain = args->write_domain;
 	int ret;
 	/* Only handle setting domains to types used by the CPU. */
 	if (write_domain & I915_GEM_GPU_DOMAINS)
 		return -EINVAL;
 	if (read_domains & I915_GEM_GPU_DOMAINS)
 		return -EINVAL;
 	/* Having something in the write domain implies it's in the read
 	 * domain, and only that read domain.  Enforce that in the request.
 	 */
 	if (write_domain != 0 && read_domains != write_domain)
 		return -EINVAL;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		return ret;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 	if (&obj->base == NULL) {
 		ret = -ENOENT;
 		goto unlock;
+	}
 	/* Try to flush the object off the GPU without holding the lock.
 	 * We will repeat the flush holding the lock in the normal manner
 	 * to catch cases where we are gazumped.
 	 */
 	ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
 	if (ret)
 		goto unref;
 	if (read_domains & I915_GEM_DOMAIN_GTT) {
 		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 		/* Silently promote "you're not bound, there was nothing to do"
 		 * to success, since the client was just asking us to
 		 * make sure everything was done.
 		 */
 		if (ret == -EINVAL)
 			ret = 0;
 	} else {
 		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
+	}
 unref:
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 /**
  * Called when user space has done writes to this buffer
  */
 int
 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 			 struct drm_file *file)
+{
 	struct drm_i915_gem_sw_finish *args = data;
 	struct drm_i915_gem_object *obj;
 	int ret = 0;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		return ret;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 	if (&obj->base == NULL) {
 		ret = -ENOENT;
 		goto unlock;
+	}
 	/* Pinned buffers may be scanout, so flush the cache */
 	if (obj->pin_count)
 		i915_gem_object_flush_cpu_write_domain(obj);
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 /**
  * Maps the contents of an object, returning the address it is mapped
  * into.
+ *
  * While the mapping holds a reference on the contents of the object, it doesn't
  * imply a ref on the object itself.
  */
 int
 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 		    struct drm_file *file)
+{
 	struct drm_i915_gem_mmap *args = data;
 	struct drm_gem_object *obj;
 	unsigned long addr;
 	obj = drm_gem_object_lookup(dev, file, args->handle);
 	if (obj == NULL)
 		return -ENOENT;
 	/* prime objects have no backing filp to GEM mmap
 	 * pages from.
 	 */
 	if (!obj->filp) {
 		drm_gem_object_unreference_unlocked(obj);
 		return -EINVAL;
+	}
 	addr = vm_mmap(obj->filp, 0, args->size,
 		       PROT_READ | PROT_WRITE, MAP_SHARED,
 		       args->offset);
 	drm_gem_object_unreference_unlocked(obj);
 	if (IS_ERR((void *)addr))
 		return addr;
 	args->addr_ptr = (uint64_t) addr;
 	return 0;
+}
 /**
  * i915_gem_fault - fault a page into the GTT
  * vma: VMA in question
  * vmf: fault info
+ *
  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
  * from userspace.  The fault handler takes care of binding the object to
  * the GTT (if needed), allocating and programming a fence register (again,
  * only if needed based on whether the old reg is still valid or the object
  * is tiled) and inserting a new PTE into the faulting process.
+ *
  * Note that the faulting process may involve evicting existing objects
  * from the GTT and/or fence registers to make room.  So performance may
  * suffer if the GTT working set is large or there are few fence registers
  * left.
  */
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
 	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
 	struct drm_device *dev = obj->base.dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	pgoff_t page_offset;
 	unsigned long pfn;
 	int ret = 0;
 	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
 	/* We don't use vmf->pgoff since that has the fake offset */
 	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
 		PAGE_SHIFT;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		goto out;
 	trace_i915_gem_object_fault(obj, page_offset, true, write);
 	/* Now bind it into the GTT if needed */
 	ret = i915_gem_object_pin(obj, 0, true, false);
 	if (ret)
 		goto unlock;
 	ret = i915_gem_object_set_to_gtt_domain(obj, write);
 	if (ret)
 		goto unpin;
 	ret = i915_gem_object_get_fence(obj);
 	if (ret)
 		goto unpin;
 	obj->fault_mappable = true;
 	pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
 		page_offset;
 	/* Finally, remap it using the new GTT offset */
 	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
 unpin:
 	i915_gem_object_unpin(obj);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 out:
 	switch (ret) {
 	case -EIO:
 		/* If this -EIO is due to a gpu hang, give the reset code a
 		 * chance to clean up the mess. Otherwise return the proper
 		 * SIGBUS. */
 		if (!atomic_read(&dev_priv->mm.wedged))
 			return VM_FAULT_SIGBUS;
 	case -EAGAIN:
 		/* Give the error handler a chance to run and move the
 		 * objects off the GPU active list. Next time we service the
 		 * fault, we should be able to transition the page into the
 		 * GTT without touching the GPU (and so avoid further
 		 * EIO/EGAIN). If the GPU is wedged, then there is no issue
 		 * with coherency, just lost writes.
 		 */
 		set_need_resched();
 	case 0:
 	case -ERESTARTSYS:
 	case -EINTR:
 	case -EBUSY:
 		/*
 		 * EBUSY is ok: this just means that another thread
 		 * already did the job.
 		 */
 		return VM_FAULT_NOPAGE;
 	case -ENOMEM:
 		return VM_FAULT_OOM;
 	case -ENOSPC:
 		return VM_FAULT_SIGBUS;
 	default:
 		WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
 		return VM_FAULT_SIGBUS;
+	}
+}
 /**
  * i915_gem_release_mmap - remove physical page mappings
  * @obj: obj in question
+ *
  * Preserve the reservation of the mmapping with the DRM core code, but
  * relinquish ownership of the pages back to the system.
+ *
  * It is vital that we remove the page mapping if we have mapped a tiled
  * object through the GTT and then lose the fence register due to
  * resource pressure. Similarly if the object has been moved out of the
  * aperture, than pages mapped into userspace must be revoked. Removing the
  * mapping will then trigger a page fault on the next user access, allowing
  * fixup by i915_gem_fault().
  */
 void
 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
+{
 	if (!obj->fault_mappable)
 		return;
 	if (obj->base.dev->dev_mapping)
 		unmap_mapping_range(obj->base.dev->dev_mapping,
 				    (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
 				    obj->base.size, 1);
 	obj->fault_mappable = false;
+}
 static uint32_t
 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
+{
 	uint32_t gtt_size;
 	if (INTEL_INFO(dev)->gen >= 4 ||
 	    tiling_mode == I915_TILING_NONE)
 		return size;
 	/* Previous chips need a power-of-two fence region when tiling */
 	if (INTEL_INFO(dev)->gen == 3)
 		gtt_size = 1024*1024;
 	else
 		gtt_size = 512*1024;
 	while (gtt_size < size)
 		gtt_size <<= 1;
 	return gtt_size;
+}
 /**
  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
  * @obj: object to check
+ *
  * Return the required GTT alignment for an object, taking into account
  * potential fence register mapping.
  */
 static uint32_t
 i915_gem_get_gtt_alignment(struct drm_device *dev,
 			   uint32_t size,
 			   int tiling_mode)
+{
 	/*
 	 * Minimum alignment is 4k (GTT page size), but might be greater
 	 * if a fence register is needed for the object.
 	 */
 	if (INTEL_INFO(dev)->gen >= 4 ||
 	    tiling_mode == I915_TILING_NONE)
 		return 4096;
 	/*
 	 * Previous chips need to be aligned to the size of the smallest
 	 * fence register that can contain the object.
 	 */
 	return i915_gem_get_gtt_size(dev, size, tiling_mode);
+}
 /**
  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
  *					 unfenced object
  * @dev: the device
  * @size: size of the object
  * @tiling_mode: tiling mode of the object
+ *
  * Return the required GTT alignment for an object, only taking into account
  * unfenced tiled surface requirements.
  */
 uint32_t
 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
 				    uint32_t size,
 				    int tiling_mode)
+{
 	/*
 	 * Minimum alignment is 4k (GTT page size) for sane hw.
 	 */
 	if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
 	    tiling_mode == I915_TILING_NONE)
 		return 4096;
 	/* Previous hardware however needs to be aligned to a power-of-two
 	 * tile height. The simplest method for determining this is to reuse
 	 * the power-of-tile object size.
 	 */
 	return i915_gem_get_gtt_size(dev, size, tiling_mode);
+}
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
+{
 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	int ret;
 	if (obj->base.map_list.map)
 		return 0;
 	dev_priv->mm.shrinker_no_lock_stealing = true;
 	ret = drm_gem_create_mmap_offset(&obj->base);
 	if (ret != -ENOSPC)
 		goto out;
 	/* Badly fragmented mmap space? The only way we can recover
 	 * space is by destroying unwanted objects. We can't randomly release
 	 * mmap_offsets as userspace expects them to be persistent for the
 	 * lifetime of the objects. The closest we can is to release the
 	 * offsets on purgeable objects by truncating it and marking it purged,
 	 * which prevents userspace from ever using that object again.
 	 */
 	i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
 	ret = drm_gem_create_mmap_offset(&obj->base);
 	if (ret != -ENOSPC)
 		goto out;
 	i915_gem_shrink_all(dev_priv);
 	ret = drm_gem_create_mmap_offset(&obj->base);
 out:
 	dev_priv->mm.shrinker_no_lock_stealing = false;
 	return ret;
+}
 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
+{
 	if (!obj->base.map_list.map)
 		return;
 	drm_gem_free_mmap_offset(&obj->base);
+}
 int
 i915_gem_mmap_gtt(struct drm_file *file,
 		  struct drm_device *dev,
 		  uint32_t handle,
 		  uint64_t *offset)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
 		return ret;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
 	if (&obj->base == NULL) {
 		ret = -ENOENT;
 		goto unlock;
+	}
 	if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
 		ret = -E2BIG;
 		goto out;
+	}
 	if (obj->madv != I915_MADV_WILLNEED) {
 		DRM_ERROR("Attempting to mmap a purgeable buffer\n");
 		ret = -EINVAL;
 		goto out;
+	}
 	ret = i915_gem_object_create_mmap_offset(obj);
 	if (ret)
 		goto out;
 	*offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
 out:
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
+}
 /**
  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
  * @dev: DRM device
  * @data: GTT mapping ioctl data
  * @file: GEM object info
+ *
  * Simply returns the fake offset to userspace so it can mmap it.
  * The mmap call will end up in drm_gem_mmap(), which will set things
  * up so we can get faults in the handler above.
+ *
  * The fault handler will take care of binding the object into the GTT
  * (since it may have been evicted to make room for something), allocating
  * a fence register, and mapping the appropriate aperture address into
  * userspace.
  */
 int
 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file)
+{
 	struct drm_i915_gem_mmap_gtt *args = data;
 	return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
+}
 /* Immediately discard the backing storage */
 static void
 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
+{
 	struct inode *inode;
 	i915_gem_object_free_mmap_offset(obj);
 	if (obj->base.filp == NULL)
 		return;
 	/* Our goal here is to return as much of the memory as
 	 * is possible back to the system as we are called from OOM.
 	 * To do this we must instruct the shmfs to drop all of its
 	 * backing pages, *now*.
 	 */
 	inode = obj->base.filp->f_path.dentry->d_inode;
 	shmem_truncate_range(inode, 0, (loff_t)-1);
 	obj->madv = __I915_MADV_PURGED;
+}
 static inline int
 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
+{
 	return obj->madv == I915_MADV_DONTNEED;
+}
 static void
 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
+{
 	int page_count = obj->base.size / PAGE_SIZE;
 	struct scatterlist *sg;
 	int ret, i;
 	BUG_ON(obj->madv == __I915_MADV_PURGED);
 	ret = i915_gem_object_set_to_cpu_domain(obj, true);
 	if (ret) {
 		/* In the event of a disaster, abandon all caches and
 		 * hope for the best.
 		 */
 		WARN_ON(ret != -EIO);
 		i915_gem_clflush_object(obj);
 		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+	}
 	if (i915_gem_object_needs_bit17_swizzle(obj))
 		i915_gem_object_save_bit_17_swizzle(obj);
 	if (obj->madv == I915_MADV_DONTNEED)
 		obj->dirty = 0;
 	for_each_sg(obj->pages->sgl, sg, page_count, i) {
 		struct page *page = sg_page(sg);
 		if (obj->dirty)
 			set_page_dirty(page);
 		if (obj->madv == I915_MADV_WILLNEED)
 			mark_page_accessed(page);
 		page_cache_release(page);
+	}
 	obj->dirty = 0;
 	sg_free_table(obj->pages);
 	kfree(obj->pages);
+}
 static int
 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
+{
 	const struct drm_i915_gem_object_ops *ops = obj->ops;
 	if (obj->pages == NULL)
 		return 0;
 	BUG_ON(obj->gtt_space);
 	if (obj->pages_pin_count)
 		return -EBUSY;
 	/* ->put_pages might need to allocate memory for the bit17 swizzle
 	 * array, hence protect them from being reaped by removing them from gtt
 	 * lists early. */
 	list_del(&obj->gtt_list);
 	ops->put_pages(obj);
 	obj->pages = NULL;
 	if (i915_gem_object_is_purgeable(obj))
 		i915_gem_object_truncate(obj);
 	return 0;
+}
 static long
 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
 		  bool purgeable_only)
+{
 	struct drm_i915_gem_object *obj, *next;
 	long count = 0;
 	list_for_each_entry_safe(obj, next,
 				 &dev_priv->mm.unbound_list,
 				 gtt_list) {
 		if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
 		    i915_gem_object_put_pages(obj) == 0) {
 			count += obj->base.size >> PAGE_SHIFT;
 			if (count >= target)
 				return count;
+		}
+	}
 	list_for_each_entry_safe(obj, next,
 				 &dev_priv->mm.inactive_list,
 				 mm_list) {
 		if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
 		    i915_gem_object_unbind(obj) == 0 &&
 		    i915_gem_object_put_pages(obj) == 0) {
 			count += obj->base.size >> PAGE_SHIFT;
 			if (count >= target)
 				return count;
+		}
+	}
 	return count;
+}
 static long
 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
+{
 	return __i915_gem_shrink(dev_priv, target, true);
+}
 static void
 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
+{
 	struct drm_i915_gem_object *obj, *next;
 	i915_gem_evict_everything(dev_priv->dev);
 	list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
 		i915_gem_object_put_pages(obj);
+}
 static int
 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
+{
 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	int page_count, i;
 	struct address_space *mapping;
 	struct sg_table *st;
 	struct scatterlist *sg;
 	struct page *page;
 	gfp_t gfp;
 	/* Assert that the object is not currently in any GPU domain. As it
 	 * wasn't in the GTT, there shouldn't be any way it could have been in
 	 * a GPU cache
 	 */
 	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
 	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (st == NULL)
 		return -ENOMEM;
 	page_count = obj->base.size / PAGE_SIZE;
 	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
 		sg_free_table(st);
 		kfree(st);
 		return -ENOMEM;
+	}
 	/* Get the list of pages out of our struct file.  They'll be pinned
 	 * at this point until we release them.
+	 *
 	 * Fail silently without starting the shrinker
 	 */
 	mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 	gfp = mapping_gfp_mask(mapping);
 	gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
 	gfp &= ~(__GFP_IO | __GFP_WAIT);
 	for_each_sg(st->sgl, sg, page_count, i) {
 		page = shmem_read_mapping_page_gfp(mapping, i, gfp);
 		if (IS_ERR(page)) {
 			i915_gem_purge(dev_priv, page_count);
 			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
+		}
 		if (IS_ERR(page)) {
 			/* We've tried hard to allocate the memory by reaping
 			 * our own buffer, now let the real VM do its job and
 			 * go down in flames if truly OOM.
 			 */
 			gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
 			gfp |= __GFP_IO | __GFP_WAIT;
 			i915_gem_shrink_all(dev_priv);
 			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
 			if (IS_ERR(page))
 				goto err_pages;
 			gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
 			gfp &= ~(__GFP_IO | __GFP_WAIT);
+		}
 		sg_set_page(sg, page, PAGE_SIZE, 0);
+	}
 	obj->pages = st;
 	if (i915_gem_object_needs_bit17_swizzle(obj))
 		i915_gem_object_do_bit_17_swizzle(obj);
 	return 0;
 err_pages:
 	for_each_sg(st->sgl, sg, i, page_count)
 		page_cache_release(sg_page(sg));
 	sg_free_table(st);
 	kfree(st);
 	return PTR_ERR(page);
+}
 /* Ensure that the associated pages are gathered from the backing storage
  * and pinned into our object. i915_gem_object_get_pages() may be called
  * multiple times before they are released by a single call to
  * i915_gem_object_put_pages() - once the pages are no longer referenced
  * either as a result of memory pressure (reaping pages under the shrinker)
  * or as the object is itself released.
  */
 int
 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
+{
 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	const struct drm_i915_gem_object_ops *ops = obj->ops;
 	int ret;
 	if (obj->pages)
 		return 0;
 	BUG_ON(obj->pages_pin_count);
 	ret = ops->get_pages(obj);
 	if (ret)
 		return ret;
 	list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
 	return 0;
+}
 void
 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
 			       struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 seqno = intel_ring_get_seqno(ring);
 	BUG_ON(ring == NULL);
 	obj->ring = ring;
 	/* Add a reference if we're newly entering the active list. */
 	if (!obj->active) {
 		drm_gem_object_reference(&obj->base);
 		obj->active = 1;
+	}
 	/* Move from whatever list we were on to the tail of execution. */
 	list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
 	list_move_tail(&obj->ring_list, &ring->active_list);
 	obj->last_read_seqno = seqno;
 	if (obj->fenced_gpu_access) {
 		obj->last_fenced_seqno = seqno;
 		/* Bump MRU to take account of the delayed flush */
 		if (obj->fence_reg != I915_FENCE_REG_NONE) {
 			struct drm_i915_fence_reg *reg;
 			reg = &dev_priv->fence_regs[obj->fence_reg];
 			list_move_tail(&reg->lru_list,
 				       &dev_priv->mm.fence_list);
+		}
+	}
+}
 static void
 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
 	BUG_ON(!obj->active);
 	if (obj->pin_count) /* are we a framebuffer? */
 		intel_mark_fb_idle(obj);
 	list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
 	list_del_init(&obj->ring_list);
 	obj->ring = NULL;
 	obj->last_read_seqno = 0;
 	obj->last_write_seqno = 0;
 	obj->base.write_domain = 0;
 	obj->last_fenced_seqno = 0;
 	obj->fenced_gpu_access = false;
 	obj->active = 0;
 	drm_gem_object_unreference(&obj->base);
 	WARN_ON(i915_verify_lists(dev));
+}
 static int
 i915_gem_handle_seqno_wrap(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	int ret, i, j;
 	/* The hardware uses various monotonic 32-bit counters, if we
 	 * detect that they will wraparound we need to idle the GPU
 	 * and reset those counters.
 	 */
 	ret = 0;
 	for_each_ring(ring, dev_priv, i) {
 		for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
 			ret |= ring->sync_seqno[j] != 0;
+	}
 	if (ret == 0)
 		return ret;
 	ret = i915_gpu_idle(dev);
 	if (ret)
 		return ret;
 	i915_gem_retire_requests(dev);
 	for_each_ring(ring, dev_priv, i) {
 		for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
 			ring->sync_seqno[j] = 0;
+	}
 	return 0;
+}
 int
 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* reserve 0 for non-seqno */
 	if (dev_priv->next_seqno == 0) {
 		int ret = i915_gem_handle_seqno_wrap(dev);
 		if (ret)
 			return ret;
 		dev_priv->next_seqno = 1;
+	}
 	*seqno = dev_priv->next_seqno++;
 	return 0;
+}
 int
 i915_add_request(struct intel_ring_buffer *ring,
 		 struct drm_file *file,
 		 u32 *out_seqno)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	struct drm_i915_gem_request *request;
 	u32 request_ring_position;
 	int was_empty;
 	int ret;
 	/*
 	 * Emit any outstanding flushes - execbuf can fail to emit the flush
 	 * after having emitted the batchbuffer command. Hence we need to fix
 	 * things up similar to emitting the lazy request. The difference here
 	 * is that the flush _must_ happen before the next request, no matter
 	 * what.
 	 */
 	ret = intel_ring_flush_all_caches(ring);
 	if (ret)
 		return ret;
 	request = kmalloc(sizeof(*request), GFP_KERNEL);
 	if (request == NULL)
 		return -ENOMEM;
 	/* Record the position of the start of the request so that
 	 * should we detect the updated seqno part-way through the
 	 * GPU processing the request, we never over-estimate the
 	 * position of the head.
 	 */
 	request_ring_position = intel_ring_get_tail(ring);
 	ret = ring->add_request(ring);
 	if (ret) {
 		kfree(request);
 		return ret;
+	}
 	request->seqno = intel_ring_get_seqno(ring);
 	request->ring = ring;
 	request->tail = request_ring_position;
 	request->emitted_jiffies = jiffies;
 	was_empty = list_empty(&ring->request_list);
 	list_add_tail(&request->list, &ring->request_list);

 @@ -1,2678 +1,2700 @@
 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  */
 /*
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
  * without limitation the rights to use, copy, modify, merge, publish,
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
+ *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/sysrq.h>
 #include <linux/slab.h>
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
 /* For display hotplug interrupt */
 static void
 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
+{
 	if ((dev_priv->irq_mask & mask) != 0) {
 		dev_priv->irq_mask &= ~mask;
 		I915_WRITE(DEIMR, dev_priv->irq_mask);
 		POSTING_READ(DEIMR);
+	}
+}
 static inline void
 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
+{
 	if ((dev_priv->irq_mask & mask) != mask) {
 		dev_priv->irq_mask |= mask;
 		I915_WRITE(DEIMR, dev_priv->irq_mask);
 		POSTING_READ(DEIMR);
+	}
+}
 void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+{
 	if ((dev_priv->pipestat[pipe] & mask) != mask) {
 		u32 reg = PIPESTAT(pipe);
 		dev_priv->pipestat[pipe] |= mask;
 		/* Enable the interrupt, clear any pending status */
 		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 		POSTING_READ(reg);
+	}
+}
 void
 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+{
 	if ((dev_priv->pipestat[pipe] & mask) != 0) {
 		u32 reg = PIPESTAT(pipe);
 		dev_priv->pipestat[pipe] &= ~mask;
 		I915_WRITE(reg, dev_priv->pipestat[pipe]);
 		POSTING_READ(reg);
+	}
+}
 /**
  * intel_enable_asle - enable ASLE interrupt for OpRegion
  */
 void intel_enable_asle(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long irqflags;
 	/* FIXME: opregion/asle for VLV */
 	if (IS_VALLEYVIEW(dev))
 		return;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	if (HAS_PCH_SPLIT(dev))
 		ironlake_enable_display_irq(dev_priv, DE_GSE);
 	else {
 		i915_enable_pipestat(dev_priv, 1,
 				     PIPE_LEGACY_BLC_EVENT_ENABLE);
 		if (INTEL_INFO(dev)->gen >= 4)
 			i915_enable_pipestat(dev_priv, 0,
 					     PIPE_LEGACY_BLC_EVENT_ENABLE);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 /**
  * i915_pipe_enabled - check if a pipe is enabled
  * @dev: DRM device
  * @pipe: pipe to check
+ *
  * Reading certain registers when the pipe is disabled can hang the chip.
  * Use this routine to make sure the PLL is running and the pipe is active
  * before reading such registers if unsure.
  */
 static int
 i915_pipe_enabled(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
+}
 /* Called from drm generic code, passed a 'crtc', which
  * we use as a pipe index
  */
 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long high_frame;
 	unsigned long low_frame;
 	u32 high1, high2, low;
 	if (!i915_pipe_enabled(dev, pipe)) {
 		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 				"pipe %c\n", pipe_name(pipe));
 		return 0;
+	}
 	high_frame = PIPEFRAME(pipe);
 	low_frame = PIPEFRAMEPIXEL(pipe);
 	/*
 	 * High & low register fields aren't synchronized, so make sure
 	 * we get a low value that's stable across two reads of the high
 	 * register.
 	 */
 	do {
 		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 	} while (high1 != high2);
 	high1 >>= PIPE_FRAME_HIGH_SHIFT;
 	low >>= PIPE_FRAME_LOW_SHIFT;
 	return (high1 << 8) | low;
+}
 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int reg = PIPE_FRMCOUNT_GM45(pipe);
 	if (!i915_pipe_enabled(dev, pipe)) {
 		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 				 "pipe %c\n", pipe_name(pipe));
 		return 0;
+	}
 	return I915_READ(reg);
+}
 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 			     int *vpos, int *hpos)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 vbl = 0, position = 0;
 	int vbl_start, vbl_end, htotal, vtotal;
 	bool in_vbl = true;
 	int ret = 0;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	if (!i915_pipe_enabled(dev, pipe)) {
 		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 				 "pipe %c\n", pipe_name(pipe));
 		return 0;
+	}
 	/* Get vtotal. */
 	vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		/* No obvious pixelcount register. Only query vertical
 		 * scanout position from Display scan line register.
 		 */
 		position = I915_READ(PIPEDSL(pipe));
 		/* Decode into vertical scanout position. Don't have
 		 * horizontal scanout position.
 		 */
 		*vpos = position & 0x1fff;
 		*hpos = 0;
 	} else {
 		/* Have access to pixelcount since start of frame.
 		 * We can split this into vertical and horizontal
 		 * scanout position.
 		 */
 		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 		htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 		*vpos = position / htotal;
 		*hpos = position - (*vpos * htotal);
+	}
 	/* Query vblank area. */
 	vbl = I915_READ(VBLANK(cpu_transcoder));
 	/* Test position against vblank region. */
 	vbl_start = vbl & 0x1fff;
 	vbl_end = (vbl >> 16) & 0x1fff;
 	if ((*vpos < vbl_start) || (*vpos > vbl_end))
 		in_vbl = false;
 	/* Inside "upper part" of vblank area? Apply corrective offset: */
 	if (in_vbl && (*vpos >= vbl_start))
 		*vpos = *vpos - vtotal;
 	/* Readouts valid? */
 	if (vbl > 0)
 		ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 	/* In vblank? */
 	if (in_vbl)
 		ret |= DRM_SCANOUTPOS_INVBL;
 	return ret;
+}
 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 			      int *max_error,
 			      struct timeval *vblank_time,
 			      unsigned flags)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 		DRM_ERROR("Invalid crtc %d\n", pipe);
 		return -EINVAL;
+	}
 	/* Get drm_crtc to timestamp: */
 	crtc = intel_get_crtc_for_pipe(dev, pipe);
 	if (crtc == NULL) {
 		DRM_ERROR("Invalid crtc %d\n", pipe);
 		return -EINVAL;
+	}
 	if (!crtc->enabled) {
 		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 		return -EBUSY;
+	}
 	/* Helper routine in DRM core does all the work: */
 	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 						     vblank_time, flags,
 						     crtc);
+}
 /*
  * Handle hotplug events outside the interrupt handler proper.
  */
 static void i915_hotplug_work_func(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    hotplug_work);
 	struct drm_device *dev = dev_priv->dev;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	mutex_lock(&mode_config->mutex);
 	DRM_DEBUG_KMS("running encoder hotplug functions\n");
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 		if (encoder->hot_plug)
 			encoder->hot_plug(encoder);
 	mutex_unlock(&mode_config->mutex);
 	/* Just fire off a uevent and let userspace tell us what to do */
 	drm_helper_hpd_irq_event(dev);
+}
 /* defined intel_pm.c */
 extern spinlock_t mchdev_lock;
 static void ironlake_handle_rps_change(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	u32 busy_up, busy_down, max_avg, min_avg;
 	u8 new_delay;
 	unsigned long flags;
 	spin_lock_irqsave(&mchdev_lock, flags);
 	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 	new_delay = dev_priv->ips.cur_delay;
 	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 	busy_up = I915_READ(RCPREVBSYTUPAVG);
 	busy_down = I915_READ(RCPREVBSYTDNAVG);
 	max_avg = I915_READ(RCBMAXAVG);
 	min_avg = I915_READ(RCBMINAVG);
 	/* Handle RCS change request from hw */
 	if (busy_up > max_avg) {
 		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 			new_delay = dev_priv->ips.cur_delay - 1;
 		if (new_delay < dev_priv->ips.max_delay)
 			new_delay = dev_priv->ips.max_delay;
 	} else if (busy_down < min_avg) {
 		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 			new_delay = dev_priv->ips.cur_delay + 1;
 		if (new_delay > dev_priv->ips.min_delay)
 			new_delay = dev_priv->ips.min_delay;
+	}
 	if (ironlake_set_drps(dev, new_delay))
 		dev_priv->ips.cur_delay = new_delay;
 	spin_unlock_irqrestore(&mchdev_lock, flags);
 	return;
+}
 static void notify_ring(struct drm_device *dev,
 			struct intel_ring_buffer *ring)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (ring->obj == NULL)
 		return;
 	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 #ifdef __NetBSD__
 	DRM_WAKEUP_ALL(&ring->irq_queue, &drm_global_mutex);
 #else
 	wake_up_all(&ring->irq_queue);
 #endif
 	if (i915_enable_hangcheck) {
 		dev_priv->hangcheck_count = 0;
 		mod_timer(&dev_priv->hangcheck_timer,
 			  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
+	}
+}
 static void gen6_pm_rps_work(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    rps.work);
 	u32 pm_iir, pm_imr;
 	u8 new_delay;
 	spin_lock_irq(&dev_priv->rps.lock);
 	pm_iir = dev_priv->rps.pm_iir;
 	dev_priv->rps.pm_iir = 0;
 	pm_imr = I915_READ(GEN6_PMIMR);
 	I915_WRITE(GEN6_PMIMR, 0);
 	spin_unlock_irq(&dev_priv->rps.lock);
 	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 		return;
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 		new_delay = dev_priv->rps.cur_delay + 1;
 	else
 		new_delay = dev_priv->rps.cur_delay - 1;
 	/* sysfs frequency interfaces may have snuck in while servicing the
 	 * interrupt
 	 */
 	if (!(new_delay > dev_priv->rps.max_delay ||
 	      new_delay < dev_priv->rps.min_delay)) {
 		gen6_set_rps(dev_priv->dev, new_delay);
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
+}
 /**
  * ivybridge_parity_work - Workqueue called when a parity error interrupt
  * occurred.
  * @work: workqueue struct
+ *
  * Doesn't actually do anything except notify userspace. As a consequence of
  * this event, userspace should try to remap the bad rows since statistically
  * it is likely the same row is more likely to go bad again.
  */
 static void ivybridge_parity_work(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    l3_parity.error_work);
 	u32 error_status, row, bank, subbank;
 	char *parity_event[5];
 	uint32_t misccpctl;
 	unsigned long flags;
 	/* We must turn off DOP level clock gating to access the L3 registers.
 	 * In order to prevent a get/put style interface, acquire struct mutex
 	 * any time we access those registers.
 	 */
 	mutex_lock(&dev_priv->dev->struct_mutex);
 	misccpctl = I915_READ(GEN7_MISCCPCTL);
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 	POSTING_READ(GEN7_MISCCPCTL);
 	error_status = I915_READ(GEN7_L3CDERRST1);
 	row = GEN7_PARITY_ERROR_ROW(error_status);
 	bank = GEN7_PARITY_ERROR_BANK(error_status);
 	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 				    GEN7_L3CDERRST1_ENABLE);
 	POSTING_READ(GEN7_L3CDERRST1);
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 	parity_event[0] = "L3_PARITY_ERROR=1";
 	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 	parity_event[4] = NULL;
 	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 			   KOBJ_CHANGE, parity_event);
 	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 		  row, bank, subbank);
 	kfree(parity_event[3]);
 	kfree(parity_event[2]);
 	kfree(parity_event[1]);
+}
 static void ivybridge_handle_parity_error(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long flags;
 	if (!HAS_L3_GPU_CACHE(dev))
 		return;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
+}
 static void snb_gt_irq_handler(struct drm_device *dev,
 			       struct drm_i915_private *dev_priv,
 			       u32 gt_iir)
+{
 	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 		      GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 		notify_ring(dev, &dev_priv->ring[RCS]);
 	if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 		notify_ring(dev, &dev_priv->ring[VCS]);
 	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 		notify_ring(dev, &dev_priv->ring[BCS]);
 	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 		      GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 		      GT_RENDER_CS_ERROR_INTERRUPT)) {
 		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 		i915_handle_error(dev, false);
+	}
 	if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 		ivybridge_handle_parity_error(dev);
+}
 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 				u32 pm_iir)
+{
 	unsigned long flags;
 	/*
 	 * IIR bits should never already be set because IMR should
 	 * prevent an interrupt from being shown in IIR. The warning
 	 * displays a case where we've unsafely cleared
 	 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 	 * type is not a problem, it displays a problem in the logic.
+	 *
 	 * The mask bit in IMR is cleared by dev_priv->rps.work.
 	 */
 	spin_lock_irqsave(&dev_priv->rps.lock, flags);
 	dev_priv->rps.pm_iir |= pm_iir;
 	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 	POSTING_READ(GEN6_PMIMR);
 	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 	queue_work(dev_priv->wq, &dev_priv->rps.work);
+}
 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 iir, gt_iir, pm_iir;
 	irqreturn_t ret = IRQ_NONE;
 	unsigned long irqflags;
 	int pipe;
 	u32 pipe_stats[I915_MAX_PIPES];
 	bool blc_event;
 	atomic_inc(&dev_priv->irq_received);
 	while (true) {
 		iir = I915_READ(VLV_IIR);
 		gt_iir = I915_READ(GTIIR);
 		pm_iir = I915_READ(GEN6_PMIIR);
 		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 			goto out;
 		ret = IRQ_HANDLED;
 		snb_gt_irq_handler(dev, dev_priv, gt_iir);
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/*
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
 			if (pipe_stats[pipe] & 0x8000ffff) {
 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
 							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 		for_each_pipe(pipe) {
 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 				drm_handle_vblank(dev, pipe);
 			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 				intel_prepare_page_flip(dev, pipe);
 				intel_finish_page_flip(dev, pipe);
+			}
+		}
 		/* Consume port.  Then clear IIR or we'll miss events */
 		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 					 hotplug_status);
 			if (hotplug_status & dev_priv->hotplug_supported_mask)
 				queue_work(dev_priv->wq,
 					   &dev_priv->hotplug_work);
 			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 			I915_READ(PORT_HOTPLUG_STAT);
+		}
 		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 			blc_event = true;
 		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 			gen6_queue_rps_work(dev_priv, pm_iir);
 		I915_WRITE(GTIIR, gt_iir);
 		I915_WRITE(GEN6_PMIIR, pm_iir);
 		I915_WRITE(VLV_IIR, iir);
+	}
 out:
 	return ret;
+}
 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	if (pch_iir & SDE_HOTPLUG_MASK)
 		queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 	if (pch_iir & SDE_AUDIO_POWER_MASK)
 		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
 				 SDE_AUDIO_POWER_SHIFT);
 	if (pch_iir & SDE_GMBUS)
 		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 	if (pch_iir & SDE_AUDIO_HDCP_MASK)
 		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 	if (pch_iir & SDE_AUDIO_TRANS_MASK)
 		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 	if (pch_iir & SDE_POISON)
 		DRM_ERROR("PCH poison interrupt\n");
 	if (pch_iir & SDE_FDI_MASK)
 		for_each_pipe(pipe)
 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 					 pipe_name(pipe),
 					 I915_READ(FDI_RX_IIR(pipe)));
 	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 		DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
+}
 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 		queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 				 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 				 SDE_AUDIO_POWER_SHIFT_CPT);
 	if (pch_iir & SDE_AUX_MASK_CPT)
 		DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 	if (pch_iir & SDE_GMBUS_CPT)
 		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 	if (pch_iir & SDE_FDI_MASK_CPT)
 		for_each_pipe(pipe)
 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 					 pipe_name(pipe),
 					 I915_READ(FDI_RX_IIR(pipe)));
+}
 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 de_iir, gt_iir, de_ier, pm_iir;
 	irqreturn_t ret = IRQ_NONE;
 	int i;
 	atomic_inc(&dev_priv->irq_received);
 	/* disable master interrupt before clearing iir  */
 	de_ier = I915_READ(DEIER);
 	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 	gt_iir = I915_READ(GTIIR);
 	if (gt_iir) {
 		snb_gt_irq_handler(dev, dev_priv, gt_iir);
 		I915_WRITE(GTIIR, gt_iir);
 		ret = IRQ_HANDLED;
+	}
 	de_iir = I915_READ(DEIIR);
 	if (de_iir) {
 		if (de_iir & DE_GSE_IVB)
 			intel_opregion_gse_intr(dev);
 		for (i = 0; i < 3; i++) {
 			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 				drm_handle_vblank(dev, i);
 			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 				intel_prepare_page_flip(dev, i);
 				intel_finish_page_flip_plane(dev, i);
+			}
+		}
 		/* check event from PCH */
 		if (de_iir & DE_PCH_EVENT_IVB) {
 			u32 pch_iir = I915_READ(SDEIIR);
 			cpt_irq_handler(dev, pch_iir);
 			/* clear PCH hotplug event before clear CPU irq */
 			I915_WRITE(SDEIIR, pch_iir);
+		}
 		I915_WRITE(DEIIR, de_iir);
 		ret = IRQ_HANDLED;
+	}
 	pm_iir = I915_READ(GEN6_PMIIR);
 	if (pm_iir) {
 		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 			gen6_queue_rps_work(dev_priv, pm_iir);
 		I915_WRITE(GEN6_PMIIR, pm_iir);
 		ret = IRQ_HANDLED;
+	}
 	I915_WRITE(DEIER, de_ier);
 	POSTING_READ(DEIER);
 	return ret;
+}
 static void ilk_gt_irq_handler(struct drm_device *dev,
 			       struct drm_i915_private *dev_priv,
 			       u32 gt_iir)
+{
 	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 		notify_ring(dev, &dev_priv->ring[RCS]);
 	if (gt_iir & GT_BSD_USER_INTERRUPT)
 		notify_ring(dev, &dev_priv->ring[VCS]);
+}
 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int ret = IRQ_NONE;
 	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 	atomic_inc(&dev_priv->irq_received);
 	/* disable master interrupt before clearing iir  */
 	de_ier = I915_READ(DEIER);
 	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 	POSTING_READ(DEIER);
 	de_iir = I915_READ(DEIIR);
 	gt_iir = I915_READ(GTIIR);
 	pch_iir = I915_READ(SDEIIR);
 	pm_iir = I915_READ(GEN6_PMIIR);
 	if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 	    (!IS_GEN6(dev) || pm_iir == 0))
 		goto done;
 	ret = IRQ_HANDLED;
 	if (IS_GEN5(dev))
 		ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 	else
 		snb_gt_irq_handler(dev, dev_priv, gt_iir);
 	if (de_iir & DE_GSE)
 		intel_opregion_gse_intr(dev);
 	if (de_iir & DE_PIPEA_VBLANK)
 		drm_handle_vblank(dev, 0);
 	if (de_iir & DE_PIPEB_VBLANK)
 		drm_handle_vblank(dev, 1);
 	if (de_iir & DE_PLANEA_FLIP_DONE) {
 		intel_prepare_page_flip(dev, 0);
 		intel_finish_page_flip_plane(dev, 0);
+	}
 	if (de_iir & DE_PLANEB_FLIP_DONE) {
 		intel_prepare_page_flip(dev, 1);
 		intel_finish_page_flip_plane(dev, 1);
+	}
 	/* check event from PCH */
 	if (de_iir & DE_PCH_EVENT) {
 		if (HAS_PCH_CPT(dev))
 			cpt_irq_handler(dev, pch_iir);
 		else
 			ibx_irq_handler(dev, pch_iir);
+	}
 	if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 		ironlake_handle_rps_change(dev);
 	if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 		gen6_queue_rps_work(dev_priv, pm_iir);
 	/* should clear PCH hotplug event before clear CPU irq */
 	I915_WRITE(SDEIIR, pch_iir);
 	I915_WRITE(GTIIR, gt_iir);
 	I915_WRITE(DEIIR, de_iir);
 	I915_WRITE(GEN6_PMIIR, pm_iir);
 done:
 	I915_WRITE(DEIER, de_ier);
 	POSTING_READ(DEIER);
 	return ret;
+}
 /**
  * i915_error_work_func - do process context error handling work
  * @work: work struct
+ *
  * Fire an error uevent so userspace can see that a hang or error
  * was detected.
  */
 static void i915_error_work_func(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    error_work);
 	struct drm_device *dev = dev_priv->dev;
 	char *error_event[] = { "ERROR=1", NULL };
 	char *reset_event[] = { "RESET=1", NULL };
 	char *reset_done_event[] = { "ERROR=0", NULL };
 	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 	if (atomic_read(&dev_priv->mm.wedged)) {
 		DRM_DEBUG_DRIVER("resetting chip\n");
 		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 		if (!i915_reset(dev)) {
 			atomic_set(&dev_priv->mm.wedged, 0);
 			kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
+		}
 		complete_all(&dev_priv->error_completion);
+	}
+}
 /* NB: please notice the memset */
 static void i915_get_extra_instdone(struct drm_device *dev,
 				    uint32_t *instdone)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 	switch(INTEL_INFO(dev)->gen) {
 	case 2:
 	case 3:
 		instdone[0] = I915_READ(INSTDONE);
 		break;
 	case 4:
 	case 5:
 	case 6:
 		instdone[0] = I915_READ(INSTDONE_I965);
 		instdone[1] = I915_READ(INSTDONE1);
 		break;
 	default:
 		WARN_ONCE(1, "Unsupported platform\n");
 	case 7:
 		instdone[0] = I915_READ(GEN7_INSTDONE_1);
 		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 		break;
+	}
+}
 #ifdef CONFIG_DEBUG_FS
 static struct drm_i915_error_object *
 i915_error_object_create(struct drm_i915_private *dev_priv,
 			 struct drm_i915_gem_object *src)
+{
 	struct drm_i915_error_object *dst;
 	int i, count;
 	u32 reloc_offset;
 	if (src == NULL || src->pages == NULL)
 		return NULL;
 	count = src->base.size / PAGE_SIZE;
 	dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 	if (dst == NULL)
 		return NULL;
 	reloc_offset = src->gtt_offset;
 	for (i = 0; i < count; i++) {
 		unsigned long flags;
 		void *d;
 		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 		if (d == NULL)
 			goto unwind;
 		local_irq_save(flags);
 		if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 		    src->has_global_gtt_mapping) {
 			void __iomem *s;
 			/* Simply ignore tiling or any overlapping fence.
 			 * It's part of the error state, and this hopefully
 			 * captures what the GPU read.
 			 */
 			s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 						     reloc_offset);
 			memcpy_fromio(d, s, PAGE_SIZE);
 			io_mapping_unmap_atomic(s);
 		} else {
 			struct page *page;
 			void *s;
 			page = i915_gem_object_get_page(src, i);
 			drm_clflush_pages(&page, 1);
 			s = kmap_atomic(page);
 			memcpy(d, s, PAGE_SIZE);
 			kunmap_atomic(s);
 			drm_clflush_pages(&page, 1);
+		}
 		local_irq_restore(flags);
 		dst->pages[i] = d;
 		reloc_offset += PAGE_SIZE;
+	}
 	dst->page_count = count;
 	dst->gtt_offset = src->gtt_offset;
 	return dst;
 unwind:
 	while (i--)
 		kfree(dst->pages[i]);
 	kfree(dst);
 	return NULL;
+}
 static void
 i915_error_object_free(struct drm_i915_error_object *obj)
+{
 	int page;
 	if (obj == NULL)
 		return;
 	for (page = 0; page < obj->page_count; page++)
 		kfree(obj->pages[page]);
 	kfree(obj);
+}
 void
 i915_error_state_free(struct kref *error_ref)
+{
 	struct drm_i915_error_state *error = container_of(error_ref,
 							  typeof(*error), ref);
 	int i;
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 		i915_error_object_free(error->ring[i].batchbuffer);
 		i915_error_object_free(error->ring[i].ringbuffer);
 		kfree(error->ring[i].requests);
+	}
 	kfree(error->active_bo);
 	kfree(error->overlay);
 	kfree(error);
+}
 static void capture_bo(struct drm_i915_error_buffer *err,
 		       struct drm_i915_gem_object *obj)
+{
 	err->size = obj->base.size;
 	err->name = obj->base.name;
 	err->rseqno = obj->last_read_seqno;
 	err->wseqno = obj->last_write_seqno;
 	err->gtt_offset = obj->gtt_offset;
 	err->read_domains = obj->base.read_domains;
 	err->write_domain = obj->base.write_domain;
 	err->fence_reg = obj->fence_reg;
 	err->pinned = 0;
 	if (obj->pin_count > 0)
 		err->pinned = 1;
 	if (obj->user_pin_count > 0)
 		err->pinned = -1;
 	err->tiling = obj->tiling_mode;
 	err->dirty = obj->dirty;
 	err->purgeable = obj->madv != I915_MADV_WILLNEED;
 	err->ring = obj->ring ? obj->ring->id : -1;
 	err->cache_level = obj->cache_level;
+}
 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 			     int count, struct list_head *head)
+{
 	struct drm_i915_gem_object *obj;
 	int i = 0;
 	list_for_each_entry(obj, head, mm_list) {
 		capture_bo(err++, obj);
 		if (++i == count)
 			break;
+	}
 	return i;
+}
 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 			     int count, struct list_head *head)
+{
 	struct drm_i915_gem_object *obj;
 	int i = 0;
 	list_for_each_entry(obj, head, gtt_list) {
 		if (obj->pin_count == 0)
 			continue;
 		capture_bo(err++, obj);
 		if (++i == count)
 			break;
+	}
 	return i;
+}
 static void i915_gem_record_fences(struct drm_device *dev,
 				   struct drm_i915_error_state *error)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
 	/* Fences */
 	switch (INTEL_INFO(dev)->gen) {
 	case 7:
 	case 6:
 		for (i = 0; i < 16; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 		break;
 	case 5:
 	case 4:
 		for (i = 0; i < 16; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 		break;
 	case 3:
 		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 			for (i = 0; i < 8; i++)
 				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 	case 2:
 		for (i = 0; i < 8; i++)
 			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 		break;
+	}
+}
 static struct drm_i915_error_object *
 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 			     struct intel_ring_buffer *ring)
+{
 	struct drm_i915_gem_object *obj;
 	u32 seqno;
 	if (!ring->get_seqno)
 		return NULL;
 	if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
 		u32 acthd = I915_READ(ACTHD);
 		if (WARN_ON(ring->id != RCS))
 			return NULL;
 		obj = ring->private;
 		if (acthd >= obj->gtt_offset &&
 		    acthd < obj->gtt_offset + obj->base.size)
 			return i915_error_object_create(dev_priv, obj);
+	}
 	seqno = ring->get_seqno(ring, false);
 	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 		if (obj->ring != ring)
 			continue;
 		if (i915_seqno_passed(seqno, obj->last_read_seqno))
 			continue;
 		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 			continue;
 		/* We need to copy these to an anonymous buffer as the simplest
 		 * method to avoid being overwritten by userspace.
 		 */
 		return i915_error_object_create(dev_priv, obj);
+	}
 	return NULL;
+}
 static void i915_record_ring_state(struct drm_device *dev,
 				   struct drm_i915_error_state *error,
 				   struct intel_ring_buffer *ring)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
 		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 		error->semaphore_mboxes[ring->id][0]
 			= I915_READ(RING_SYNC_0(ring->mmio_base));
 		error->semaphore_mboxes[ring->id][1]
 			= I915_READ(RING_SYNC_1(ring->mmio_base));
 		error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
 		error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
+	}
 	if (INTEL_INFO(dev)->gen >= 4) {
 		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
 		error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
 		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
 		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 		if (ring->id == RCS)
 			error->bbaddr = I915_READ64(BB_ADDR);
 	} else {
 		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
 		error->ipeir[ring->id] = I915_READ(IPEIR);
 		error->ipehr[ring->id] = I915_READ(IPEHR);
 		error->instdone[ring->id] = I915_READ(INSTDONE);
+	}
 #ifdef __NetBSD__
 	error->waiting[ring->id] = DRM_WAITERS_P(&ring->irq_queue,
 	    &drm_global_mutex);
 #else
 	error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
 #endif
 	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
 	error->seqno[ring->id] = ring->get_seqno(ring, false);
 	error->acthd[ring->id] = intel_ring_get_active_head(ring);
 	error->head[ring->id] = I915_READ_HEAD(ring);
 	error->tail[ring->id] = I915_READ_TAIL(ring);
 	error->ctl[ring->id] = I915_READ_CTL(ring);
 	error->cpu_ring_head[ring->id] = ring->head;
 	error->cpu_ring_tail[ring->id] = ring->tail;
+}
 static void i915_gem_record_rings(struct drm_device *dev,
 				  struct drm_i915_error_state *error)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	struct drm_i915_gem_request *request;
 	int i, count;
 	for_each_ring(ring, dev_priv, i) {
 		i915_record_ring_state(dev, error, ring);
 		error->ring[i].batchbuffer =
 			i915_error_first_batchbuffer(dev_priv, ring);
 		error->ring[i].ringbuffer =
 			i915_error_object_create(dev_priv, ring->obj);
 		count = 0;
 		list_for_each_entry(request, &ring->request_list, list)
 			count++;
 		error->ring[i].num_requests = count;
 		error->ring[i].requests =
 			kmalloc(count*sizeof(struct drm_i915_error_request),
 				GFP_ATOMIC);
 		if (error->ring[i].requests == NULL) {
 			error->ring[i].num_requests = 0;
 			continue;
+		}
 		count = 0;
 		list_for_each_entry(request, &ring->request_list, list) {
 			struct drm_i915_error_request *erq;
 			erq = &error->ring[i].requests[count++];
 			erq->seqno = request->seqno;
 			erq->jiffies = request->emitted_jiffies;
 			erq->tail = request->tail;
+		}
+	}
+}
 /**
  * i915_capture_error_state - capture an error record for later analysis
  * @dev: drm device
+ *
  * Should be called when an error is detected (either a hang or an error
  * interrupt) to capture error state from the time of the error.  Fills
  * out a structure which becomes available in debugfs for user level tools
  * to pick up.
  */
 static void i915_capture_error_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	struct drm_i915_error_state *error;
 	unsigned long flags;
 	int i, pipe;
 	spin_lock_irqsave(&dev_priv->error_lock, flags);
 	error = dev_priv->first_error;
 	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 	if (error)
 		return;
 	/* Account for pipe specific data like PIPE*STAT */
 	error = kzalloc(sizeof(*error), GFP_ATOMIC);
 	if (!error) {
 		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 		return;
+	}
 	DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 		 dev->primary->index);
 	kref_init(&error->ref);
 	error->eir = I915_READ(EIR);
 	error->pgtbl_er = I915_READ(PGTBL_ER);
 	error->ccid = I915_READ(CCID);
 	if (HAS_PCH_SPLIT(dev))
 		error->ier = I915_READ(DEIER) | I915_READ(GTIER);
 	else if (IS_VALLEYVIEW(dev))
 		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
 	else if (IS_GEN2(dev))
 		error->ier = I915_READ16(IER);
 	else
 		error->ier = I915_READ(IER);
 	if (INTEL_INFO(dev)->gen >= 6)
 		error->derrmr = I915_READ(DERRMR);
 	if (IS_VALLEYVIEW(dev))
 		error->forcewake = I915_READ(FORCEWAKE_VLV);
 	else if (INTEL_INFO(dev)->gen >= 7)
 		error->forcewake = I915_READ(FORCEWAKE_MT);
 	else if (INTEL_INFO(dev)->gen == 6)
 		error->forcewake = I915_READ(FORCEWAKE);
 	for_each_pipe(pipe)
 		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 	if (INTEL_INFO(dev)->gen >= 6) {
 		error->error = I915_READ(ERROR_GEN6);
 		error->done_reg = I915_READ(DONE_REG);
+	}
 	if (INTEL_INFO(dev)->gen == 7)
 		error->err_int = I915_READ(GEN7_ERR_INT);
 	i915_get_extra_instdone(dev, error->extra_instdone);
 	i915_gem_record_fences(dev, error);
 	i915_gem_record_rings(dev, error);
 	/* Record buffers on the active and pinned lists. */
 	error->active_bo = NULL;
 	error->pinned_bo = NULL;
 	i = 0;
 	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 		i++;
 	error->active_bo_count = i;
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
 		if (obj->pin_count)
 			i++;
 	error->pinned_bo_count = i - error->active_bo_count;
 	error->active_bo = NULL;
 	error->pinned_bo = NULL;
 	if (i) {
 		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 					   GFP_ATOMIC);
 		if (error->active_bo)
 			error->pinned_bo =
 				error->active_bo + error->active_bo_count;
+	}
 	if (error->active_bo)
 		error->active_bo_count =
 			capture_active_bo(error->active_bo,
 					  error->active_bo_count,
 					  &dev_priv->mm.active_list);
 	if (error->pinned_bo)
 		error->pinned_bo_count =
 			capture_pinned_bo(error->pinned_bo,
 					  error->pinned_bo_count,
 					  &dev_priv->mm.bound_list);
 	do_gettimeofday(&error->time);
 	error->overlay = intel_overlay_capture_error_state(dev);
 	error->display = intel_display_capture_error_state(dev);
 	spin_lock_irqsave(&dev_priv->error_lock, flags);
 	if (dev_priv->first_error == NULL) {
 		dev_priv->first_error = error;
 		error = NULL;
+	}
 	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 	if (error)
 		i915_error_state_free(&error->ref);
+}
 void i915_destroy_error_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_error_state *error;
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->error_lock, flags);
 	error = dev_priv->first_error;
 	dev_priv->first_error = NULL;
 	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 	if (error)
 		kref_put(&error->ref, i915_error_state_free);
+}
 #else
 #define i915_capture_error_state(x)
 #endif
 static void i915_report_and_clear_eir(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t instdone[I915_NUM_INSTDONE_REG];
 	u32 eir = I915_READ(EIR);
 	int pipe, i;
 	if (!eir)
 		return;
 	pr_err("render error detected, EIR: 0x%08x\n", eir);
 	i915_get_extra_instdone(dev, instdone);
 	if (IS_G4X(dev)) {
 		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 			u32 ipeir = I915_READ(IPEIR_I965);
 			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
 			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
 			for (i = 0; i < ARRAY_SIZE(instdone); i++)
 				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
 			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
 			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
 			I915_WRITE(IPEIR_I965, ipeir);
 			POSTING_READ(IPEIR_I965);
+		}
 		if (eir & GM45_ERROR_PAGE_TABLE) {
 			u32 pgtbl_err = I915_READ(PGTBL_ER);
 			pr_err("page table error\n");
 			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
 			I915_WRITE(PGTBL_ER, pgtbl_err);
 			POSTING_READ(PGTBL_ER);
+		}
+	}
 	if (!IS_GEN2(dev)) {
 		if (eir & I915_ERROR_PAGE_TABLE) {
 			u32 pgtbl_err = I915_READ(PGTBL_ER);
 			pr_err("page table error\n");
 			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
 			I915_WRITE(PGTBL_ER, pgtbl_err);
 			POSTING_READ(PGTBL_ER);
+		}
+	}
 	if (eir & I915_ERROR_MEMORY_REFRESH) {
 		pr_err("memory refresh error:\n");
 		for_each_pipe(pipe)
 			pr_err("pipe %c stat: 0x%08x\n",
 			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
 		/* pipestat has already been acked */
+	}
 	if (eir & I915_ERROR_INSTRUCTION) {
 		pr_err("instruction error\n");
 		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
 		for (i = 0; i < ARRAY_SIZE(instdone); i++)
 			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
 		if (INTEL_INFO(dev)->gen < 4) {
 			u32 ipeir = I915_READ(IPEIR);
 			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
 			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
 			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
 			I915_WRITE(IPEIR, ipeir);
 			POSTING_READ(IPEIR);
 		} else {
 			u32 ipeir = I915_READ(IPEIR_I965);
 			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
 			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
 			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
 			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
 			I915_WRITE(IPEIR_I965, ipeir);
 			POSTING_READ(IPEIR_I965);
+		}
+	}
 	I915_WRITE(EIR, eir);
 	POSTING_READ(EIR);
 	eir = I915_READ(EIR);
 	if (eir) {
 		/*
 		 * some errors might have become stuck,
 		 * mask them.
 		 */
 		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 		I915_WRITE(EMR, I915_READ(EMR) | eir);
 		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
+	}
+}
 /**
  * i915_handle_error - handle an error interrupt
  * @dev: drm device
+ *
  * Do some basic checking of regsiter state at error interrupt time and
  * dump it to the syslog.  Also call i915_capture_error_state() to make
  * sure we get a record and make it available in debugfs.  Fire a uevent
  * so userspace knows something bad happened (should trigger collection
  * of a ring dump etc.).
  */
 void i915_handle_error(struct drm_device *dev, bool wedged)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	int i;
 	i915_capture_error_state(dev);
 	i915_report_and_clear_eir(dev);
 	if (wedged) {
 		INIT_COMPLETION(dev_priv->error_completion);
 		atomic_set(&dev_priv->mm.wedged, 1);
 		/*
 		 * Wakeup waiting processes so they don't hang
 		 */
 		for_each_ring(ring, dev_priv, i)
 #ifdef __NetBSD__
 			DRM_WAKEUP_ALL(&ring->irq_queue, &drm_global_mutex);
 #else
 			wake_up_all(&ring->irq_queue);
 #endif
+	}
 	queue_work(dev_priv->wq, &dev_priv->error_work);
+}
 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_i915_gem_object *obj;
 	struct intel_unpin_work *work;
 	unsigned long flags;
 	bool stall_detected;
 	/* Ignore early vblank irqs */
 	if (intel_crtc == NULL)
 		return;
 	spin_lock_irqsave(&dev->event_lock, flags);
 	work = intel_crtc->unpin_work;
 	if (work == NULL ||
 	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
 	    !work->enable_stall_check) {
 		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
 		spin_unlock_irqrestore(&dev->event_lock, flags);
 		return;
+	}
 	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 	obj = work->pending_flip_obj;
 	if (INTEL_INFO(dev)->gen >= 4) {
 		int dspsurf = DSPSURF(intel_crtc->plane);
 		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
 					obj->gtt_offset;
 	} else {
 		int dspaddr = DSPADDR(intel_crtc->plane);
 		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
 							crtc->y * crtc->fb->pitches[0] +
 							crtc->x * crtc->fb->bits_per_pixel/8);
+	}
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	if (stall_detected) {
 		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 		intel_prepare_page_flip(dev, intel_crtc->plane);
+	}
+}
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
 static int i915_enable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	if (INTEL_INFO(dev)->gen >= 4)
 		i915_enable_pipestat(dev_priv, pipe,
 				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	else
 		i915_enable_pipestat(dev_priv, pipe,
 				     PIPE_VBLANK_INTERRUPT_ENABLE);
 	/* maintain vblank delivery even in deep C-states */
 	if (dev_priv->info->gen == 3)
 		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
 				    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	ironlake_enable_display_irq(dev_priv,
 				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	u32 imr;
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	imr = I915_READ(VLV_IMR);
 	if (pipe == 0)
 		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 	else
 		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	I915_WRITE(VLV_IMR, imr);
 	i915_enable_pipestat(dev_priv, pipe,
 			     PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
 static void i915_disable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	if (dev_priv->info->gen == 3)
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
 	i915_disable_pipestat(dev_priv, pipe,
 			      PIPE_VBLANK_INTERRUPT_ENABLE |
 			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
 				     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	ironlake_disable_display_irq(dev_priv,
 				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	u32 imr;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	i915_disable_pipestat(dev_priv, pipe,
 			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	imr = I915_READ(VLV_IMR);
 	if (pipe == 0)
 		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 	else
 		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	I915_WRITE(VLV_IMR, imr);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 static u32
 ring_last_seqno(struct intel_ring_buffer *ring)
+{
 	return list_entry(ring->request_list.prev,
 			  struct drm_i915_gem_request, list)->seqno;
+}
 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
+{
 	if (list_empty(&ring->request_list) ||
 	    i915_seqno_passed(ring->get_seqno(ring, false),
 			      ring_last_seqno(ring))) {
 		/* Issue a wake-up to catch stuck h/w. */
 #ifdef __NetBSD__
 		if (DRM_WAITERS_P(&ring->irq_queue, &drm_global_mutex)) {
 			DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
 				  ring->name);
 			DRM_WAKEUP_ALL(&ring->irq_queue, &drm_global_mutex);
 			*err = true;
+		}
 #else
 		if (waitqueue_active(&ring->irq_queue)) {
 			DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
 				  ring->name);
 			wake_up_all(&ring->irq_queue);
 			*err = true;
+		}
 #endif
 		return true;
+	}
 	return false;
+}
 static bool kick_ring(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 tmp = I915_READ_CTL(ring);
 	if (tmp & RING_WAIT) {
 		DRM_ERROR("Kicking stuck wait on %s\n",
 			  ring->name);
 		I915_WRITE_CTL(ring, tmp);
 		return true;
+	}
 	return false;
+}
 static bool i915_hangcheck_hung(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	if (dev_priv->hangcheck_count++ > 1) {
 		bool hung = true;
 		DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 		i915_handle_error(dev, true);
 		if (!IS_GEN2(dev)) {
 			struct intel_ring_buffer *ring;
 			int i;
 			/* Is the chip hanging on a WAIT_FOR_EVENT?
 			 * If so we can simply poke the RB_WAIT bit
 			 * and break the hang. This should work on
 			 * all but the second generation chipsets.
 			 */
 			for_each_ring(ring, dev_priv, i)
 				hung &= !kick_ring(ring);
+		}
 		return hung;
+	}
 	return false;
+}
 /**
  * This is called when the chip hasn't reported back with completed
  * batchbuffers in a long time. The first time this is called we simply record
  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  * again, we assume the chip is wedged and try to fix it.
  */
 void i915_hangcheck_elapsed(unsigned long data)
+{
 	struct drm_device *dev = (struct drm_device *)data;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
 	struct intel_ring_buffer *ring;
 	bool err = false, idle;
 	int i;
 	if (!i915_enable_hangcheck)
 		return;
 	memset(acthd, 0, sizeof(acthd));
 	idle = true;
 	for_each_ring(ring, dev_priv, i) {
 	    idle &= i915_hangcheck_ring_idle(ring, &err);
 	    acthd[i] = intel_ring_get_active_head(ring);
+	}
 	/* If all work is done then ACTHD clearly hasn't advanced. */
 	if (idle) {
 		if (err) {
 			if (i915_hangcheck_hung(dev))
 				return;
 			goto repeat;
+		}
 		dev_priv->hangcheck_count = 0;
 		return;
+	}
 	i915_get_extra_instdone(dev, instdone);
 	if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
 	    memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
 		if (i915_hangcheck_hung(dev))
 			return;
 	} else {
 		dev_priv->hangcheck_count = 0;
 		memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
 		memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
+	}
 repeat:
 	/* Reset timer case chip hangs without another request being added */
 	mod_timer(&dev_priv->hangcheck_timer,
 		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
+}
 /* drm_dma.h hooks
 */
 static void ironlake_irq_preinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	atomic_set(&dev_priv->irq_received, 0);
 	I915_WRITE(HWSTAM, 0xeffe);
 	/* XXX hotplug from PCH */
 	I915_WRITE(DEIMR, 0xffffffff);
 	I915_WRITE(DEIER, 0x0);
 	POSTING_READ(DEIER);
 	/* and GT */
 	I915_WRITE(GTIMR, 0xffffffff);
 	I915_WRITE(GTIER, 0x0);
 	POSTING_READ(GTIER);
 	/* south display irq */
 	I915_WRITE(SDEIMR, 0xffffffff);
 	I915_WRITE(SDEIER, 0x0);
 	POSTING_READ(SDEIER);
+}
 static void valleyview_irq_preinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	atomic_set(&dev_priv->irq_received, 0);
 	/* VLV magic */
 	I915_WRITE(VLV_IMR, 0);
 	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
 	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
 	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
 	/* and GT */
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIMR, 0xffffffff);
 	I915_WRITE(GTIER, 0x0);
 	POSTING_READ(GTIER);
 	I915_WRITE(DPINVGTT, 0xff);
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0xffff);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(VLV_IMR, 0xffffffff);
 	I915_WRITE(VLV_IER, 0x0);
 	POSTING_READ(VLV_IER);
+}
 /*
  * Enable digital hotplug on the PCH, and configure the DP short pulse
  * duration to 2ms (which is the minimum in the Display Port spec)
+ *
  * This register is the same on all known PCH chips.
  */
 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32	hotplug;
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
 	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
 	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
 	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
 	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
+}
 static int ironlake_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	/* enable kind of interrupts always enabled */
 	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
 			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
 	u32 render_irqs;
 	u32 hotplug_mask;
 	dev_priv->irq_mask = ~display_mask;
 	/* should always can generate irq */
 	I915_WRITE(DEIIR, I915_READ(DEIIR));
 	I915_WRITE(DEIMR, dev_priv->irq_mask);
 	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
 	POSTING_READ(DEIER);
 	dev_priv->gt_irq_mask = ~0;
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 	if (IS_GEN6(dev))
 		render_irqs =
 			GT_USER_INTERRUPT |
 			GEN6_BSD_USER_INTERRUPT |
 			GEN6_BLITTER_USER_INTERRUPT;
 	else
 		render_irqs =
 			GT_USER_INTERRUPT |
 			GT_PIPE_NOTIFY |
 			GT_BSD_USER_INTERRUPT;
 	I915_WRITE(GTIER, render_irqs);
 	POSTING_READ(GTIER);
 	if (HAS_PCH_CPT(dev)) {
 		hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
 				SDE_PORTB_HOTPLUG_CPT |
 				SDE_PORTC_HOTPLUG_CPT |
 				SDE_PORTD_HOTPLUG_CPT);
 	} else {
 		hotplug_mask = (SDE_CRT_HOTPLUG |
 				SDE_PORTB_HOTPLUG |
 				SDE_PORTC_HOTPLUG |
 				SDE_PORTD_HOTPLUG |
 				SDE_AUX_MASK);
+	}
 	dev_priv->pch_irq_mask = ~hotplug_mask;
 	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
 	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
 	I915_WRITE(SDEIER, hotplug_mask);
 	POSTING_READ(SDEIER);
 	ironlake_enable_pch_hotplug(dev);
 	if (IS_IRONLAKE_M(dev)) {
 		/* Clear & enable PCU event interrupts */
 		I915_WRITE(DEIIR, DE_PCU_EVENT);
 		I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
 		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
+	}
 	return 0;
+}
 static int ivybridge_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	/* enable kind of interrupts always enabled */
 	u32 display_mask =
 		DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
 		DE_PLANEC_FLIP_DONE_IVB |
 		DE_PLANEB_FLIP_DONE_IVB |
 		DE_PLANEA_FLIP_DONE_IVB;
 	u32 render_irqs;
 	u32 hotplug_mask;
 	dev_priv->irq_mask = ~display_mask;
 	/* should always can generate irq */
 	I915_WRITE(DEIIR, I915_READ(DEIIR));
 	I915_WRITE(DEIMR, dev_priv->irq_mask);
 	I915_WRITE(DEIER,
 		   display_mask |
 		   DE_PIPEC_VBLANK_IVB |
 		   DE_PIPEB_VBLANK_IVB |
 		   DE_PIPEA_VBLANK_IVB);
 	POSTING_READ(DEIER);
 	dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
 		GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 	I915_WRITE(GTIER, render_irqs);
 	POSTING_READ(GTIER);
 	hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
 			SDE_PORTB_HOTPLUG_CPT |
 			SDE_PORTC_HOTPLUG_CPT |
 			SDE_PORTD_HOTPLUG_CPT);
 	dev_priv->pch_irq_mask = ~hotplug_mask;
 	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
 	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
 	I915_WRITE(SDEIER, hotplug_mask);
 	POSTING_READ(SDEIER);
 	ironlake_enable_pch_hotplug(dev);
 	return 0;
+}
 static int valleyview_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 enable_mask;
 	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
 	u32 render_irqs;
 	u16 msid;
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
 	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	/*
 	 *Leave vblank interrupts masked initially.  enable/disable will
 	 * toggle them based on usage.
 	 */
 	dev_priv->irq_mask = (~enable_mask) |
 		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
 		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 	/* Hack for broken MSIs on VLV */
 	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
 	pci_read_config_word(dev->pdev, 0x98, &msid);
 	msid &= 0xff; /* mask out delivery bits */
 	msid |= (1<<14);
 	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
 	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
 	I915_WRITE(VLV_IER, enable_mask);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(PIPESTAT(0), 0xffff);
 	I915_WRITE(PIPESTAT(1), 0xffff);
 	POSTING_READ(VLV_IER);
 	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
 	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
 		GEN6_BLITTER_USER_INTERRUPT;
 	I915_WRITE(GTIER, render_irqs);
 	POSTING_READ(GTIER);
 	/* ack & enable invalid PTE error interrupts */
 #if 0 /* FIXME: add support to irq handler for checking these bits */
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
 	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
 #endif
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 	/* Note HDMI and DP share bits */
 	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMID_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
 		hotplug_en |= CRT_HOTPLUG_INT_EN;
 		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+	}
 	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 	return 0;
+}
 static void valleyview_irq_uninstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	if (!dev_priv)
 		return;
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0xffff);
 	I915_WRITE(HWSTAM, 0xffffffff);
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0xffff);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(VLV_IMR, 0xffffffff);
 	I915_WRITE(VLV_IER, 0x0);
 	POSTING_READ(VLV_IER);
+}
 static void ironlake_irq_uninstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	if (!dev_priv)
 		return;
 	I915_WRITE(HWSTAM, 0xffffffff);
 	I915_WRITE(DEIMR, 0xffffffff);
 	I915_WRITE(DEIER, 0x0);
 	I915_WRITE(DEIIR, I915_READ(DEIIR));
 	I915_WRITE(GTIMR, 0xffffffff);
 	I915_WRITE(GTIER, 0x0);
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(SDEIMR, 0xffffffff);
 	I915_WRITE(SDEIER, 0x0);
 	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+}
 static void i8xx_irq_preinstall(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	atomic_set(&dev_priv->irq_received, 0);
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0);
 	I915_WRITE16(IMR, 0xffff);
 	I915_WRITE16(IER, 0x0);
 	POSTING_READ16(IER);
+}
 static int i8xx_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 	I915_WRITE16(EMR,
 		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask =
 		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
 		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 	I915_WRITE16(IMR, dev_priv->irq_mask);
 	I915_WRITE16(IER,
 		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
 		     I915_USER_INTERRUPT);
 	POSTING_READ16(IER);
 	return 0;
+}
 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u16 iir, new_iir;
 	u32 pipe_stats[2];
 	unsigned long irqflags;
 	int irq_received;
 	int pipe;
 	u16 flip_mask =
 		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
 	atomic_inc(&dev_priv->irq_received);
 	iir = I915_READ16(IIR);
 	if (iir == 0)
 		return IRQ_NONE;
 	while (iir & ~flip_mask) {
 		/* Can't rely on pipestat interrupt bit in iir as it might
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/*
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
 			if (pipe_stats[pipe] & 0x8000ffff) {
 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
 							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
 				irq_received = 1;
+			}
+		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 		I915_WRITE16(IIR, iir & ~flip_mask);
 		new_iir = I915_READ16(IIR); /* Flush posted writes */
 		i915_update_dri1_breadcrumb(dev);
 		if (iir & I915_USER_INTERRUPT)
 			notify_ring(dev, &dev_priv->ring[RCS]);
 		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
 		    drm_handle_vblank(dev, 0)) {
 			if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
 				intel_prepare_page_flip(dev, 0);
 				intel_finish_page_flip(dev, 0);
 				flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+			}
+		}
 		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
 		    drm_handle_vblank(dev, 1)) {
 			if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
 				intel_prepare_page_flip(dev, 1);
 				intel_finish_page_flip(dev, 1);
 				flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+			}
+		}
 		iir = new_iir;
+	}
 	return IRQ_HANDLED;
+}
 static void i8xx_irq_uninstall(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	for_each_pipe(pipe) {
 		/* Clear enable bits; then clear status bits */
 		I915_WRITE(PIPESTAT(pipe), 0);
 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
+	}
 	I915_WRITE16(IMR, 0xffff);
 	I915_WRITE16(IER, 0x0);
 	I915_WRITE16(IIR, I915_READ16(IIR));
+}
 static void i915_irq_preinstall(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	atomic_set(&dev_priv->irq_received, 0);
 	if (I915_HAS_HOTPLUG(dev)) {
 		I915_WRITE(PORT_HOTPLUG_EN, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	}
 	I915_WRITE16(HWSTAM, 0xeffe);
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0);
 	I915_WRITE(IMR, 0xffffffff);
 	I915_WRITE(IER, 0x0);
 	POSTING_READ(IER);
+}
 static int i915_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 enable_mask;
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask =
 		~(I915_ASLE_INTERRUPT |
 		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
 		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 	enable_mask =
 		I915_ASLE_INTERRUPT |
 		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
 		I915_USER_INTERRUPT;
 	if (I915_HAS_HOTPLUG(dev)) {
 		/* Enable in IER... */
 		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
 		/* and unmask in IMR */
 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
+	}
 	I915_WRITE(IMR, dev_priv->irq_mask);
 	I915_WRITE(IER, enable_mask);
 	POSTING_READ(IER);
 	if (I915_HAS_HOTPLUG(dev)) {
 		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
 			hotplug_en |= HDMIB_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
 			hotplug_en |= HDMIC_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
 			hotplug_en |= HDMID_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
 			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
 			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
 			hotplug_en |= CRT_HOTPLUG_INT_EN;
 			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+		}
 		/* Ignore TV since it's buggy */
 		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
+	}
 	intel_opregion_enable_asle(dev);
 	return 0;
+}
 static irqreturn_t i915_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
 	unsigned long irqflags;
 	u32 flip_mask =
 		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
 	u32 flip[2] = {
 		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
 		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
 	};
 	int pipe, ret = IRQ_NONE;
 	atomic_inc(&dev_priv->irq_received);
 	iir = I915_READ(IIR);
 	do {
 		bool irq_received = (iir & ~flip_mask) != 0;
 		bool blc_event = false;
 		/* Can't rely on pipestat interrupt bit in iir as it might
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/* Clear the PIPE*STAT regs before the IIR */
 			if (pipe_stats[pipe] & 0x8000ffff) {
 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
 							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
 				irq_received = true;
+			}
+		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 		if (!irq_received)
 			break;
 		/* Consume port.  Then clear IIR or we'll miss events */
 		if ((I915_HAS_HOTPLUG(dev)) &&
 		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 				  hotplug_status);
 			if (hotplug_status & dev_priv->hotplug_supported_mask)
 				queue_work(dev_priv->wq,
 					   &dev_priv->hotplug_work);
 			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 			POSTING_READ(PORT_HOTPLUG_STAT);
+		}
 		I915_WRITE(IIR, iir & ~flip_mask);
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 		if (iir & I915_USER_INTERRUPT)
 			notify_ring(dev, &dev_priv->ring[RCS]);
 		for_each_pipe(pipe) {
 			int plane = pipe;
 			if (IS_MOBILE(dev))
 				plane = !plane;
 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
 			    drm_handle_vblank(dev, pipe)) {
 				if (iir & flip[plane]) {
 					intel_prepare_page_flip(dev, plane);
 					intel_finish_page_flip(dev, pipe);
 					flip_mask &= ~flip[plane];
+				}
+			}
 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 				blc_event = true;
+		}
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
 			intel_opregion_asle_intr(dev);
 		/* With MSI, interrupts are only generated when iir
 		 * transitions from zero to nonzero.  If another bit got
 		 * set while we were handling the existing iir bits, then
 		 * we would never get another interrupt.
+		 *
 		 * This is fine on non-MSI as well, as if we hit this path
 		 * we avoid exiting the interrupt handler only to generate
 		 * another one.
+		 *
 		 * Note that for MSI this could cause a stray interrupt report
 		 * if an interrupt landed in the time between writing IIR and
 		 * the posting read.  This should be rare enough to never
 		 * trigger the 99% of 100,000 interrupts test for disabling
 		 * stray interrupts.
 		 */
 		ret = IRQ_HANDLED;
 		iir = new_iir;
 	} while (iir & ~flip_mask);
 	i915_update_dri1_breadcrumb(dev);
 	return ret;
+}
 static void i915_irq_uninstall(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	if (I915_HAS_HOTPLUG(dev)) {
 		I915_WRITE(PORT_HOTPLUG_EN, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	}
 	I915_WRITE16(HWSTAM, 0xffff);
 	for_each_pipe(pipe) {
 		/* Clear enable bits; then clear status bits */
 		I915_WRITE(PIPESTAT(pipe), 0);
 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
+	}
 	I915_WRITE(IMR, 0xffffffff);
 	I915_WRITE(IER, 0x0);
 	I915_WRITE(IIR, I915_READ(IIR));
+}
 static void i965_irq_preinstall(struct drm_device * dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 	atomic_set(&dev_priv->irq_received, 0);
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 	I915_WRITE(HWSTAM, 0xeffe);
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0);
 	I915_WRITE(IMR, 0xffffffff);
 	I915_WRITE(IER, 0x0);
 	POSTING_READ(IER);
+}
 static int i965_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 hotplug_en;
 	u32 enable_mask;
 	u32 error_mask;
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
 			       I915_DISPLAY_PORT_INTERRUPT |
 			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
 			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 	enable_mask = ~dev_priv->irq_mask;
 	enable_mask |= I915_USER_INTERRUPT;
 	if (IS_G4X(dev))
 		enable_mask |= I915_BSD_USER_INTERRUPT;
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 	/*
 	 * Enable some error detection, note the instruction error mask
 	 * bit is reserved, so we leave it masked.
 	 */
 	if (IS_G4X(dev)) {
 		error_mask = ~(GM45_ERROR_PAGE_TABLE |
 			       GM45_ERROR_MEM_PRIV |
 			       GM45_ERROR_CP_PRIV |
 			       I915_ERROR_MEMORY_REFRESH);
 	} else {
 		error_mask = ~(I915_ERROR_PAGE_TABLE |
 			       I915_ERROR_MEMORY_REFRESH);
+	}
 	I915_WRITE(EMR, error_mask);
 	I915_WRITE(IMR, dev_priv->irq_mask);
 	I915_WRITE(IER, enable_mask);
 	POSTING_READ(IER);
 	/* Note HDMI and DP share hotplug bits */
 	hotplug_en = 0;
 	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMID_HOTPLUG_INT_EN;
 	if (IS_G4X(dev)) {
 		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
 			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
 			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
 	} else {
 		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
 			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
 		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
 			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+	}
 	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
 		hotplug_en |= CRT_HOTPLUG_INT_EN;
 		/* Programming the CRT detection parameters tends
 		   to generate a spurious hotplug event about three
 		   seconds later.  So just do it once.
 		   */
 		if (IS_G4X(dev))
 			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
 		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+	}
 	/* Ignore TV since it's buggy */
 	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 	intel_opregion_enable_asle(dev);
 	return 0;
+}
 static irqreturn_t i965_irq_handler(int irq, void *arg)
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 iir, new_iir;
 	u32 pipe_stats[I915_MAX_PIPES];
 	unsigned long irqflags;
 	int irq_received;
 	int ret = IRQ_NONE, pipe;
 	atomic_inc(&dev_priv->irq_received);
 	iir = I915_READ(IIR);
 	for (;;) {
 		bool blc_event = false;
 		irq_received = iir != 0;
 		/* Can't rely on pipestat interrupt bit in iir as it might
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/*
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
 			if (pipe_stats[pipe] & 0x8000ffff) {
 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
 							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
 				irq_received = 1;
+			}
+		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 		if (!irq_received)
 			break;
 		ret = IRQ_HANDLED;
 		/* Consume port.  Then clear IIR or we'll miss events */
 		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 				  hotplug_status);
 			if (hotplug_status & dev_priv->hotplug_supported_mask)
 				queue_work(dev_priv->wq,
 					   &dev_priv->hotplug_work);
 			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 			I915_READ(PORT_HOTPLUG_STAT);
+		}
 		I915_WRITE(IIR, iir);
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 		if (iir & I915_USER_INTERRUPT)
 			notify_ring(dev, &dev_priv->ring[RCS]);
 		if (iir & I915_BSD_USER_INTERRUPT)
 			notify_ring(dev, &dev_priv->ring[VCS]);
 		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 			intel_prepare_page_flip(dev, 0);
 		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 			intel_prepare_page_flip(dev, 1);
 		for_each_pipe(pipe) {
 			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
 			    drm_handle_vblank(dev, pipe)) {
 				i915_pageflip_stall_check(dev, pipe);
 				intel_finish_page_flip(dev, pipe);
+			}
 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 				blc_event = true;
+		}
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
 			intel_opregion_asle_intr(dev);
 		/* With MSI, interrupts are only generated when iir
 		 * transitions from zero to nonzero.  If another bit got
 		 * set while we were handling the existing iir bits, then
 		 * we would never get another interrupt.
+		 *
 		 * This is fine on non-MSI as well, as if we hit this path
 		 * we avoid exiting the interrupt handler only to generate
 		 * another one.
+		 *
 		 * Note that for MSI this could cause a stray interrupt report
 		 * if an interrupt landed in the time between writing IIR and
 		 * the posting read.  This should be rare enough to never
 		 * trigger the 99% of 100,000 interrupts test for disabling
 		 * stray interrupts.
 		 */
 		iir = new_iir;
+	}
 	i915_update_dri1_breadcrumb(dev);
 	return ret;

 @@ -155,1743 +155,1747 @@ gen4_render_ring_flush(struct intel_ring
  * flushes.
+ *
  * And this last workaround is tricky because of the requirements on
  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
  * volume 2 part 1:
+ *
  *     "1 of the following must also be set:
  *      - Render Target Cache Flush Enable ([12] of DW1)
  *      - Depth Cache Flush Enable ([0] of DW1)
  *      - Stall at Pixel Scoreboard ([1] of DW1)
  *      - Depth Stall ([13] of DW1)
  *      - Post-Sync Operation ([13] of DW1)
  *      - Notify Enable ([8] of DW1)"
+ *
  * The cache flushes require the workaround flush that triggered this
  * one, so we can't use it.  Depth stall would trigger the same.
  * Post-sync nonzero is what triggered this second workaround, so we
  * can't use that one either.  Notify enable is IRQs, which aren't
  * really our business.  That leaves only stall at scoreboard.
  */
 static int
 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
+{
 	struct pipe_control *pc = ring->private;
 	u32 scratch_addr = pc->gtt_offset + 128;
 	int ret;
 	ret = intel_ring_begin(ring, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 			PIPE_CONTROL_STALL_AT_SCOREBOARD);
 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 	intel_ring_emit(ring, 0); /* low dword */
 	intel_ring_emit(ring, 0); /* high dword */
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	ret = intel_ring_begin(ring, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 gen6_render_ring_flush(struct intel_ring_buffer *ring,
                          u32 invalidate_domains, u32 flush_domains)
+{
 	u32 flags = 0;
 	struct pipe_control *pc = ring->private;
 	u32 scratch_addr = pc->gtt_offset + 128;
 	int ret;
 	/* Force SNB workarounds for PIPE_CONTROL flushes */
 	ret = intel_emit_post_sync_nonzero_flush(ring);
 	if (ret)
 		return ret;
 	/* Just flush everything.  Experiments have shown that reducing the
 	 * number of bits based on the write domains has little performance
 	 * impact.
 	 */
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		/*
 		 * Ensure that any following seqno writes only happen
 		 * when the render cache is indeed flushed.
 		 */
 		flags |= PIPE_CONTROL_CS_STALL;
+	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
 		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
+	}
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 	intel_ring_emit(ring, flags);
 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 			      PIPE_CONTROL_STALL_AT_SCOREBOARD);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 		       u32 invalidate_domains, u32 flush_domains)
+{
 	u32 flags = 0;
 	struct pipe_control *pc = ring->private;
 	u32 scratch_addr = pc->gtt_offset + 128;
 	int ret;
 	/*
 	 * Ensure that any following seqno writes only happen when the render
 	 * cache is indeed flushed.
+	 *
 	 * Workaround: 4th PIPE_CONTROL command (except the ones with only
 	 * read-cache invalidate bits set) must have the CS_STALL bit set. We
 	 * don't try to be clever and just set it unconditionally.
 	 */
 	flags |= PIPE_CONTROL_CS_STALL;
 	/* Just flush everything.  Experiments have shown that reducing the
 	 * number of bits based on the write domains has little performance
 	 * impact.
 	 */
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
 		flags |= PIPE_CONTROL_QW_WRITE;
 		/* Workaround: we must issue a pipe_control with CS-stall bit
 		 * set before a pipe_control command that has the state cache
 		 * invalidate bit set. */
 		gen7_render_ring_cs_stall_wa(ring);
+	}
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 	intel_ring_emit(ring, flags);
 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 	return 0;
+}
 static void ring_write_tail(struct intel_ring_buffer *ring,
 			    u32 value)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	I915_WRITE_TAIL(ring, value);
+}
 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 			RING_ACTHD(ring->mmio_base) : ACTHD;
 	return I915_READ(acthd_reg);
+}
 static int init_ring_common(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj = ring->obj;
 	int ret = 0;
 	u32 head;
 	if (HAS_FORCE_WAKE(dev))
 		gen6_gt_force_wake_get(dev_priv);
 	/* Stop the ring if it's running. */
 	I915_WRITE_CTL(ring, 0);
 	I915_WRITE_HEAD(ring, 0);
 	ring->write_tail(ring, 0);
 	head = I915_READ_HEAD(ring) & HEAD_ADDR;
 	/* G45 ring initialization fails to reset head to zero */
 	if (head != 0) {
 		DRM_DEBUG_KMS("%s head not reset to zero "
 			      "ctl %08x head %08x tail %08x start %08x\n",
 			      ring->name,
 			      I915_READ_CTL(ring),
 			      I915_READ_HEAD(ring),
 			      I915_READ_TAIL(ring),
 			      I915_READ_START(ring));
 		I915_WRITE_HEAD(ring, 0);
 		if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 			DRM_ERROR("failed to set %s head to zero "
 				  "ctl %08x head %08x tail %08x start %08x\n",
 				  ring->name,
 				  I915_READ_CTL(ring),
 				  I915_READ_HEAD(ring),
 				  I915_READ_TAIL(ring),
 				  I915_READ_START(ring));
+		}
+	}
 	/* Initialize the ring. This must happen _after_ we've cleared the ring
 	 * registers with the above sequence (the readback of the HEAD registers
 	 * also enforces ordering), otherwise the hw might lose the new ring
 	 * register values. */
 	I915_WRITE_START(ring, obj->gtt_offset);
 	I915_WRITE_CTL(ring,
 			((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 			| RING_VALID);
 	/* If the head is still not zero, the ring is dead */
 	if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 		     I915_READ_START(ring) == obj->gtt_offset &&
 		     (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 		DRM_ERROR("%s initialization failed "
 				"ctl %08x head %08x tail %08x start %08x\n",
 				ring->name,
 				I915_READ_CTL(ring),
 				I915_READ_HEAD(ring),
 				I915_READ_TAIL(ring),
 				I915_READ_START(ring));
 		ret = -EIO;
 		goto out;
+	}
 	if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 		i915_kernel_lost_context(ring->dev);
 	else {
 		ring->head = I915_READ_HEAD(ring);
 		ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 		ring->space = ring_space(ring);
 		ring->last_retired_head = -1;
+	}
 out:
 	if (HAS_FORCE_WAKE(dev))
 		gen6_gt_force_wake_put(dev_priv);
 	return ret;
+}
 static int
 init_pipe_control(struct intel_ring_buffer *ring)
+{
 	struct pipe_control *pc;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	if (ring->private)
 		return 0;
 	pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 	if (!pc)
 		return -ENOMEM;
 	obj = i915_gem_alloc_object(ring->dev, 4096);
 	if (obj == NULL) {
 		DRM_ERROR("Failed to allocate seqno page\n");
 		ret = -ENOMEM;
 		goto err;
+	}
 	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 	ret = i915_gem_object_pin(obj, 4096, true, false);
 	if (ret)
 		goto err_unref;
 	pc->gtt_offset = obj->gtt_offset;
 	pc->cpu_page =  kmap(sg_page(obj->pages->sgl));
 	if (pc->cpu_page == NULL)
 		goto err_unpin;
 	pc->obj = obj;
 	ring->private = pc;
 	return 0;
 err_unpin:
 	i915_gem_object_unpin(obj);
 err_unref:
 	drm_gem_object_unreference(&obj->base);
 err:
 	kfree(pc);
 	return ret;
+}
 static void
 cleanup_pipe_control(struct intel_ring_buffer *ring)
+{
 	struct pipe_control *pc = ring->private;
 	struct drm_i915_gem_object *obj;
 	if (!ring->private)
 		return;
 	obj = pc->obj;
 	kunmap(sg_page(obj->pages->sgl));
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 	kfree(pc);
 	ring->private = NULL;
+}
 static int init_render_ring(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = init_ring_common(ring);
 	if (INTEL_INFO(dev)->gen > 3)
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 	/* We need to disable the AsyncFlip performance optimisations in order
 	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 	 * programmed to '1' on all products.
 	 */
 	if (INTEL_INFO(dev)->gen >= 6)
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 	/* Required for the hardware to program scanline values for waiting */
 	if (INTEL_INFO(dev)->gen == 6)
 		I915_WRITE(GFX_MODE,
 			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 	if (IS_GEN7(dev))
 		I915_WRITE(GFX_MODE_GEN7,
 			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 	if (INTEL_INFO(dev)->gen >= 5) {
 		ret = init_pipe_control(ring);
 		if (ret)
 			return ret;
+	}
 	if (IS_GEN6(dev)) {
 		/* From the Sandybridge PRM, volume 1 part 3, page 24:
 		 * "If this bit is set, STCunit will have LRA as replacement
 		 *  policy. [...] This bit must be reset.  LRA replacement
 		 *  policy is not supported."
 		 */
 		I915_WRITE(CACHE_MODE_0,
 			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 		/* This is not explicitly set for GEN6, so read the register.
 		 * see intel_ring_mi_set_context() for why we care.
 		 * TODO: consider explicitly setting the bit for GEN5
 		 */
 		ring->itlb_before_ctx_switch =
 			!!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
+	}
 	if (INTEL_INFO(dev)->gen >= 6)
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 	if (HAS_L3_GPU_CACHE(dev))
 		I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 	return ret;
+}
 static void render_ring_cleanup(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	if (!ring->private)
 		return;
 	if (HAS_BROKEN_CS_TLB(dev))
 		drm_gem_object_unreference(to_gem_object(ring->private));
 	cleanup_pipe_control(ring);
+}
 static void
 update_mboxes(struct intel_ring_buffer *ring,
 	      u32 mmio_offset)
+{
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 	intel_ring_emit(ring, mmio_offset);
 	intel_ring_emit(ring, ring->outstanding_lazy_request);
+}
 /**
  * gen6_add_request - Update the semaphore mailbox registers
+ *
  * @ring - ring that is adding a request
  * @seqno - return seqno stuck into the ring
+ *
  * Update the mailbox registers in the *other* rings with the current seqno.
  * This acts like a signal in the canonical semaphore.
  */
 static int
 gen6_add_request(struct intel_ring_buffer *ring)
+{
 	u32 mbox1_reg;
 	u32 mbox2_reg;
 	int ret;
 	ret = intel_ring_begin(ring, 10);
 	if (ret)
 		return ret;
 	mbox1_reg = ring->signal_mbox[0];
 	mbox2_reg = ring->signal_mbox[1];
 	update_mboxes(ring, mbox1_reg);
 	update_mboxes(ring, mbox2_reg);
 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 	intel_ring_emit(ring, ring->outstanding_lazy_request);
 	intel_ring_emit(ring, MI_USER_INTERRUPT);
 	intel_ring_advance(ring);
 	return 0;
+}
 /**
  * intel_ring_sync - sync the waiter to the signaller on seqno
+ *
  * @waiter - ring that is waiting
  * @signaller - ring which has, or will signal
  * @seqno - seqno which the waiter will block on
  */
 static int
 gen6_ring_sync(struct intel_ring_buffer *waiter,
 	       struct intel_ring_buffer *signaller,
 	       u32 seqno)
+{
 	int ret;
 	u32 dw1 = MI_SEMAPHORE_MBOX |
 		  MI_SEMAPHORE_COMPARE |
 		  MI_SEMAPHORE_REGISTER;
 	/* Throughout all of the GEM code, seqno passed implies our current
 	 * seqno is >= the last seqno executed. However for hardware the
 	 * comparison is strictly greater than.
 	 */
 	seqno -= 1;
 	WARN_ON(signaller->semaphore_register[waiter->id] ==
 		MI_SEMAPHORE_SYNC_INVALID);
 	ret = intel_ring_begin(waiter, 4);
 	if (ret)
 		return ret;
 	intel_ring_emit(waiter,
 			dw1 | signaller->semaphore_register[waiter->id]);
 	intel_ring_emit(waiter, seqno);
 	intel_ring_emit(waiter, 0);
 	intel_ring_emit(waiter, MI_NOOP);
 	intel_ring_advance(waiter);
 	return 0;
+}
 #define PIPE_CONTROL_FLUSH(ring__, addr__)					\
 do {									\
 	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
 		 PIPE_CONTROL_DEPTH_STALL);				\
 	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
 	intel_ring_emit(ring__, 0);							\
 	intel_ring_emit(ring__, 0);							\
 } while (0)
 static int
 pc_render_add_request(struct intel_ring_buffer *ring)
+{
 	struct pipe_control *pc = ring->private;
 	u32 scratch_addr = pc->gtt_offset + 128;
 	int ret;
 	/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 	 * incoherent with writes to memory, i.e. completely fubar,
 	 * so we need to use PIPE_NOTIFY instead.
+	 *
 	 * However, we also need to workaround the qword write
 	 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 	 * memory before requesting an interrupt.
 	 */
 	ret = intel_ring_begin(ring, 32);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 			PIPE_CONTROL_WRITE_FLUSH |
 			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 	intel_ring_emit(ring, ring->outstanding_lazy_request);
 	intel_ring_emit(ring, 0);
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	scratch_addr += 128; /* write to separate cachelines */
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	scratch_addr += 128;
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	scratch_addr += 128;
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	scratch_addr += 128;
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	scratch_addr += 128;
 	PIPE_CONTROL_FLUSH(ring, scratch_addr);
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 			PIPE_CONTROL_WRITE_FLUSH |
 			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 			PIPE_CONTROL_NOTIFY);
 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 	intel_ring_emit(ring, ring->outstanding_lazy_request);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 	return 0;
+}
 static u32
 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
+{
 	/* Workaround to force correct ordering between irq and seqno writes on
 	 * ivb (and maybe also on snb) by reading from a CS register (like
 	 * ACTHD) before reading the status page. */
 	if (!lazy_coherency)
 		intel_ring_get_active_head(ring);
 	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
+}
 static u32
 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
+{
 	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
+}
 static u32
 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
+{
 	struct pipe_control *pc = ring->private;
 	return pc->cpu_page[0];
+}
 static bool
 gen5_ring_get_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	if (!dev->irq_enabled)
 		return false;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (ring->irq_refcount++ == 0) {
 		dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 		POSTING_READ(GTIMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	return true;
+}
 static void
 gen5_ring_put_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (--ring->irq_refcount == 0) {
 		dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 		POSTING_READ(GTIMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
 static bool
 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	if (!dev->irq_enabled)
 		return false;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (ring->irq_refcount++ == 0) {
 		dev_priv->irq_mask &= ~ring->irq_enable_mask;
 		I915_WRITE(IMR, dev_priv->irq_mask);
 		POSTING_READ(IMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	return true;
+}
 static void
 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (--ring->irq_refcount == 0) {
 		dev_priv->irq_mask |= ring->irq_enable_mask;
 		I915_WRITE(IMR, dev_priv->irq_mask);
 		POSTING_READ(IMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
 static bool
 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	if (!dev->irq_enabled)
 		return false;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (ring->irq_refcount++ == 0) {
 		dev_priv->irq_mask &= ~ring->irq_enable_mask;
 		I915_WRITE16(IMR, dev_priv->irq_mask);
 		POSTING_READ16(IMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	return true;
+}
 static void
 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (--ring->irq_refcount == 0) {
 		dev_priv->irq_mask |= ring->irq_enable_mask;
 		I915_WRITE16(IMR, dev_priv->irq_mask);
 		POSTING_READ16(IMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	u32 mmio = 0;
 	/* The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN7(dev)) {
 		switch (ring->id) {
 		case RCS:
 			mmio = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
 			mmio = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
 			mmio = BSD_HWS_PGA_GEN7;
 			break;
+		}
 	} else if (IS_GEN6(ring->dev)) {
 		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 	} else {
 		mmio = RING_HWS_PGA(ring->mmio_base);
+	}
 	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 	POSTING_READ(mmio);
+}
 static int
 bsd_ring_flush(struct intel_ring_buffer *ring,
 	       u32     invalidate_domains,
 	       u32     flush_domains)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 2);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_FLUSH);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 i9xx_add_request(struct intel_ring_buffer *ring)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 	intel_ring_emit(ring, ring->outstanding_lazy_request);
 	intel_ring_emit(ring, MI_USER_INTERRUPT);
 	intel_ring_advance(ring);
 	return 0;
+}
 static bool
 gen6_ring_get_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	if (!dev->irq_enabled)
 	       return false;
 	/* It looks like we need to prevent the gt from suspending while waiting
 	 * for an notifiy irq, otherwise irqs seem to get lost on at least the
 	 * blt/bsd rings on ivb. */
 	gen6_gt_force_wake_get(dev_priv);
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (ring->irq_refcount++ == 0) {
 		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 			I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 						GEN6_RENDER_L3_PARITY_ERROR));
 		else
 			I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 		dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 		POSTING_READ(GTIMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	return true;
+}
 static void
 gen6_ring_put_irq(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	if (--ring->irq_refcount == 0) {
 		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 			I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 		else
 			I915_WRITE_IMR(ring, ~0);
 		dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 		POSTING_READ(GTIMR);
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	gen6_gt_force_wake_put(dev_priv);
+}
 static int
 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			 u32 offset, u32 length,
 			 unsigned flags)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 2);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring,
 			MI_BATCH_BUFFER_START |
 			MI_BATCH_GTT |
 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
 	intel_ring_emit(ring, offset);
 	intel_ring_advance(ring);
 	return 0;
+}
 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 #define I830_BATCH_LIMIT (256*1024)
 static int
 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 				u32 offset, u32 len,
 				unsigned flags)
+{
 	int ret;
 	if (flags & I915_DISPATCH_PINNED) {
 		ret = intel_ring_begin(ring, 4);
 		if (ret)
 			return ret;
 		intel_ring_emit(ring, MI_BATCH_BUFFER);
 		intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
 		intel_ring_emit(ring, offset + len - 8);
 		intel_ring_emit(ring, MI_NOOP);
 		intel_ring_advance(ring);
 	} else {
 		struct drm_i915_gem_object *obj = ring->private;
 		u32 cs_offset = obj->gtt_offset;
 		if (len > I830_BATCH_LIMIT)
 			return -ENOSPC;
 		ret = intel_ring_begin(ring, 9+3);
 		if (ret)
 			return ret;
 		/* Blit the batch (which has now all relocs applied) to the stable batch
 		 * scratch bo area (so that the CS never stumbles over its tlb
 		 * invalidation bug) ... */
 		intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
 				XY_SRC_COPY_BLT_WRITE_ALPHA |
 				XY_SRC_COPY_BLT_WRITE_RGB);
 		intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
 		intel_ring_emit(ring, 0);
 		intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
 		intel_ring_emit(ring, cs_offset);
 		intel_ring_emit(ring, 0);
 		intel_ring_emit(ring, 4096);
 		intel_ring_emit(ring, offset);
 		intel_ring_emit(ring, MI_FLUSH);
 		/* ... and execute it. */
 		intel_ring_emit(ring, MI_BATCH_BUFFER);
 		intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
 		intel_ring_emit(ring, cs_offset + len - 8);
 		intel_ring_advance(ring);
+	}
 	return 0;
+}
 static int
 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			 u32 offset, u32 len,
 			 unsigned flags)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 2);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
 	intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
 	intel_ring_advance(ring);
 	return 0;
+}
 static void cleanup_status_page(struct intel_ring_buffer *ring)
+{
 	struct drm_i915_gem_object *obj;
 	obj = ring->status_page.obj;
 	if (obj == NULL)
 		return;
 	kunmap(sg_page(obj->pages->sgl));
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 	ring->status_page.obj = NULL;
+}
 static int init_status_page(struct intel_ring_buffer *ring)
+{
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	obj = i915_gem_alloc_object(dev, 4096);
 	if (obj == NULL) {
 		DRM_ERROR("Failed to allocate status page\n");
 		ret = -ENOMEM;
 		goto err;
+	}
 	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 	ret = i915_gem_object_pin(obj, 4096, true, false);
 	if (ret != 0) {
 		goto err_unref;
+	}
 	ring->status_page.gfx_addr = obj->gtt_offset;
 	ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
 	if (ring->status_page.page_addr == NULL) {
 		ret = -ENOMEM;
 		goto err_unpin;
+	}
 	ring->status_page.obj = obj;
 	memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 	intel_ring_setup_status_page(ring);
 	DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 			ring->name, ring->status_page.gfx_addr);
 	return 0;
 err_unpin:
 	i915_gem_object_unpin(obj);
 err_unref:
 	drm_gem_object_unreference(&obj->base);
 err:
 	return ret;
+}
 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
+{
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	u32 addr;
 	if (!dev_priv->status_page_dmah) {
 		dev_priv->status_page_dmah =
 			drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
 		if (!dev_priv->status_page_dmah)
 			return -ENOMEM;
+	}
 	addr = dev_priv->status_page_dmah->busaddr;
 	if (INTEL_INFO(ring->dev)->gen >= 4)
 		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 	I915_WRITE(HWS_PGA, addr);
 	ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
 	memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 	return 0;
+}
 static int intel_init_ring_buffer(struct drm_device *dev,
 				  struct intel_ring_buffer *ring)
+{
 	struct drm_i915_gem_object *obj;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ring->dev = dev;
 	INIT_LIST_HEAD(&ring->active_list);
 	INIT_LIST_HEAD(&ring->request_list);
 	ring->size = 32 * PAGE_SIZE;
 	memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
 #ifdef __NetBSD__
 	DRM_INIT_WAITQUEUE(&ring->irq_queue, "i915irq");
 #else
 	init_waitqueue_head(&ring->irq_queue);
 #endif
 	if (I915_NEED_GFX_HWS(dev)) {
 		ret = init_status_page(ring);
 		if (ret)
 			return ret;
 	} else {
 		BUG_ON(ring->id != RCS);
 		ret = init_phys_hws_pga(ring);
 		if (ret)
 			return ret;
+	}
 	obj = i915_gem_alloc_object(dev, ring->size);
 	if (obj == NULL) {
 		DRM_ERROR("Failed to allocate ringbuffer\n");
 		ret = -ENOMEM;
 		goto err_hws;
+	}
 	ring->obj = obj;
 	ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
 	if (ret)
 		goto err_unref;
 	ret = i915_gem_object_set_to_gtt_domain(obj, true);
 	if (ret)
 		goto err_unpin;
 #ifdef __NetBSD__
 	ring->virtual_start_map.offset = (dev_priv->mm.gtt->gma_bus_addr +
 	    obj->gtt_offset);
 	ring->virtual_start_map.size = ring->size;
 	ring->virtual_start_map.flags = 0;
 	ring->virtual_start_map.flags |= _DRM_RESTRICTED;
 	ring->virtual_start_map.flags |= _DRM_KERNEL;
 	ring->virtual_start_map.flags |= _DRM_WRITE_COMBINING;
 	ring->virtual_start_map.flags |= _DRM_DRIVER;
 	ret = drm_ioremap(dev, &ring->virtual_start_map);
 	if (ret) {
 		DRM_ERROR("failed to map ring buffer\n");
 		goto err_unpin;
+	}
 	ring->virtual_start_mapped = true;
 #else
 	ring->virtual_start =
 		ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
 			   ring->size);
 	if (ring->virtual_start == NULL) {
 		DRM_ERROR("Failed to map ringbuffer.\n");
 		ret = -EINVAL;
 		goto err_unpin;
+	}
 #endif
 	ret = ring->init(ring);
 	if (ret)
 		goto err_unmap;
 	/* Workaround an erratum on the i830 which causes a hang if
 	 * the TAIL pointer points to within the last 2 cachelines
 	 * of the buffer.
 	 */
 	ring->effective_size = ring->size;
 	if (IS_I830(ring->dev) || IS_845G(ring->dev))
 		ring->effective_size -= 128;
 	return 0;
 err_unmap:
 #ifdef __NetBSD__
 	drm_iounmap(dev, &ring->virtual_start_map);
 	ring->virtual_start_mapped = false;
 #else
 	iounmap(ring->virtual_start);
 #endif
 err_unpin:
 	i915_gem_object_unpin(obj);
 err_unref:
 	drm_gem_object_unreference(&obj->base);
 	ring->obj = NULL;
 err_hws:
 	cleanup_status_page(ring);
 	return ret;
+}
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
+{
 	struct drm_i915_private *dev_priv;
 	int ret;
 	if (ring->obj == NULL)
 		return;
 	/* Disable the ring buffer. The ring must be idle at this point */
 	dev_priv = ring->dev->dev_private;
 	ret = intel_ring_idle(ring);
 	if (ret)
 		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 			  ring->name, ret);
 	I915_WRITE_CTL(ring, 0);
 #ifdef __NetBSD__
 	drm_iounmap(dev, &ring->virtual_start_map);
 	ring->virtual_start_mapped = false;
 #else
 	iounmap(ring->virtual_start);
 #endif
 	i915_gem_object_unpin(ring->obj);
 	drm_gem_object_unreference(&ring->obj->base);
 	ring->obj = NULL;
 	if (ring->cleanup)
 		ring->cleanup(ring);
 	cleanup_status_page(ring);
+}
 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
+{
 	int ret;
 	ret = i915_wait_seqno(ring, seqno);
 	if (!ret)
 		i915_gem_retire_requests_ring(ring);
 	return ret;
+}
 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
+{
 	struct drm_i915_gem_request *request;
 	u32 seqno = 0;
 	int ret;
 	i915_gem_retire_requests_ring(ring);
 	if (ring->last_retired_head != -1) {
 		ring->head = ring->last_retired_head;
 		ring->last_retired_head = -1;
 		ring->space = ring_space(ring);
 		if (ring->space >= n)
 			return 0;
+	}
 	list_for_each_entry(request, &ring->request_list, list) {
 		int space;
 		if (request->tail == -1)
 			continue;
 		space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
 		if (space < 0)
 			space += ring->size;
 		if (space >= n) {
 			seqno = request->seqno;
 			break;
+		}
 		/* Consume this request in case we need more space than
 		 * is available and so need to prevent a race between
 		 * updating last_retired_head and direct reads of
 		 * I915_RING_HEAD. It also provides a nice sanity check.
 		 */
 		request->tail = -1;
+	}
 	if (seqno == 0)
 		return -ENOSPC;
 	ret = intel_ring_wait_seqno(ring, seqno);
 	if (ret)
 		return ret;
 	if (WARN_ON(ring->last_retired_head == -1))
 		return -ENOSPC;
 	ring->head = ring->last_retired_head;
 	ring->last_retired_head = -1;
 	ring->space = ring_space(ring);
 	if (WARN_ON(ring->space < n))
 		return -ENOSPC;
 	return 0;
+}
 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
+{
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long end;
 	int ret;
 	ret = intel_ring_wait_request(ring, n);
 	if (ret != -ENOSPC)
 		return ret;
 	trace_i915_ring_wait_begin(ring);
 	/* With GEM the hangcheck timer should kick us out of the loop,
 	 * leaving it early runs the risk of corrupting GEM state (due
 	 * to running on almost untested codepaths). But on resume
 	 * timers don't work yet, so prevent a complete hang in that
 	 * case by choosing an insanely large timeout. */
 	end = jiffies + 60 * HZ;
 	do {
 		ring->head = I915_READ_HEAD(ring);
 		ring->space = ring_space(ring);
 		if (ring->space >= n) {
 			trace_i915_ring_wait_end(ring);
 			return 0;
+		}
 		if (dev->primary->master) {
 			struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 			if (master_priv->sarea_priv)
 				master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+		}
 		msleep(1);
 		ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
 		if (ret)
 			return ret;
 	} while (!time_after(jiffies, end));
 	trace_i915_ring_wait_end(ring);
 	return -EBUSY;
+}
 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
+{
 	uint32_t __iomem *virt;
 	int rem = ring->size - ring->tail;
 	if (ring->space < rem) {
 		int ret = ring_wait_for_space(ring, rem);
 		if (ret)
 			return ret;
+	}
 	virt = ring->virtual_start + ring->tail;
 	rem /= 4;
 	while (rem--)
 		iowrite32(MI_NOOP, virt++);
 	ring->tail = 0;
 	ring->space = ring_space(ring);
 	return 0;
+}
 int intel_ring_idle(struct intel_ring_buffer *ring)
+{
 	u32 seqno;
 	int ret;
 	/* We need to add any requests required to flush the objects and ring */
 	if (ring->outstanding_lazy_request) {
 		ret = i915_add_request(ring, NULL, NULL);
 		if (ret)
 			return ret;
+	}
 	/* Wait upon the last request to be completed */
 	if (list_empty(&ring->request_list))
 		return 0;
 	seqno = list_entry(ring->request_list.prev,
 			   struct drm_i915_gem_request,
 			   list)->seqno;
 	return i915_wait_seqno(ring, seqno);
+}
 static int
 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
+{
 	if (ring->outstanding_lazy_request)
 		return 0;
 	return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
+}
 int intel_ring_begin(struct intel_ring_buffer *ring,
 		     int num_dwords)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
 	int n = 4*num_dwords;
 	int ret;
 	ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
 	if (ret)
 		return ret;
 	/* Preallocate the olr before touching the ring */
 	ret = intel_ring_alloc_seqno(ring);
 	if (ret)
 		return ret;
 	if (unlikely(ring->tail + n > ring->effective_size)) {
 		ret = intel_wrap_ring_buffer(ring);
 		if (unlikely(ret))
 			return ret;
+	}
 	if (unlikely(ring->space < n)) {
 		ret = ring_wait_for_space(ring, n);
 		if (unlikely(ret))
 			return ret;
+	}
 	ring->space -= n;
 	return 0;
+}
 void intel_ring_advance(struct intel_ring_buffer *ring)
+{
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	ring->tail &= ring->size - 1;
 	if (dev_priv->stop_rings & intel_ring_flag(ring))
 		return;
 	ring->write_tail(ring, ring->tail);
+}
 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
 				     u32 value)
+{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
        /* Every tail move must follow the sequence below */
 	/* Disable notification that the ring is IDLE. The GT
 	 * will then assume that it is busy and bring it out of rc6.
 	 */
 	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
 	/* Clear the context id. Here be magic! */
 	I915_WRITE64(GEN6_BSD_RNCID, 0x0);
 	/* Wait for the ring not to be idle, i.e. for it to wake up. */
 	if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
 		      GEN6_BSD_SLEEP_INDICATOR) == 0,
 ))
 		DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
 	/* Now that the ring is fully powered up, update the tail */
 	I915_WRITE_TAIL(ring, value);
 	POSTING_READ(RING_TAIL(ring->mmio_base));
 	/* Let the ring send IDLE messages to the GT again,
 	 * and so let it sleep to conserve power when idle.
 	 */
 	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+}
 static int gen6_ring_flush(struct intel_ring_buffer *ring,
 			   u32 invalidate, u32 flush)
+{
 	uint32_t cmd;
 	int ret;
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	cmd = MI_FLUSH_DW;
 	/*
 	 * Bspec vol 1c.5 - video engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
 	 * operation is complete. This bit is only valid when the
 	 * Post-Sync Operation field is a value of 1h or 3h."
 	 */
 	if (invalidate & I915_GEM_GPU_DOMAINS)
 		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
 			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			      u32 offset, u32 len,
 			      unsigned flags)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 2);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring,
 			MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int
 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			      u32 offset, u32 len,
 			      unsigned flags)
+{
 	int ret;
 	ret = intel_ring_begin(ring, 2);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring,
 			MI_BATCH_BUFFER_START |
 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
 	intel_ring_advance(ring);
 	return 0;
+}
 /* Blitter support (SandyBridge+) */
 static int blt_ring_flush(struct intel_ring_buffer *ring,
 			  u32 invalidate, u32 flush)
+{
 	uint32_t cmd;
 	int ret;
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 	cmd = MI_FLUSH_DW;
 	/*
 	 * Bspec vol 1c.3 - blitter engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
 	 * operation is complete. This bit is only valid when the
 	 * Post-Sync Operation field is a value of 1h or 3h."
 	 */
 	if (invalidate & I915_GEM_DOMAIN_RENDER)
 		cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
 			MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
+}
 int intel_init_render_ring_buffer(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 	ring->name = "render ring";
 	ring->id = RCS;
 	ring->mmio_base = RENDER_RING_BASE;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		ring->add_request = gen6_add_request;
 		ring->flush = gen7_render_ring_flush;
 		if (INTEL_INFO(dev)->gen == 6)
 			ring->flush = gen6_render_ring_flush;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
 		ring->irq_enable_mask = GT_USER_INTERRUPT;
 		ring->get_seqno = gen6_ring_get_seqno;
 		ring->sync_to = gen6_ring_sync;
 		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
 		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
 		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
 		ring->signal_mbox[0] = GEN6_VRSYNC;
 		ring->signal_mbox[1] = GEN6_BRSYNC;
 	} else if (IS_GEN5(dev)) {
 		ring->add_request = pc_render_add_request;
 		ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = pc_render_get_seqno;
 		ring->irq_get = gen5_ring_get_irq;
 		ring->irq_put = gen5_ring_put_irq;
 		ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
 	} else {
 		ring->add_request = i9xx_add_request;
 		if (INTEL_INFO(dev)->gen < 4)
 			ring->flush = gen2_render_ring_flush;
 		else
 			ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = ring_get_seqno;
 		if (IS_GEN2(dev)) {
 			ring->irq_get = i8xx_ring_get_irq;
 			ring->irq_put = i8xx_ring_put_irq;
 		} else {
 			ring->irq_get = i9xx_ring_get_irq;
 			ring->irq_put = i9xx_ring_put_irq;
+		}
 		ring->irq_enable_mask = I915_USER_INTERRUPT;
+	}
 	ring->write_tail = ring_write_tail;
 	if (IS_HASWELL(dev))
 		ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
 	else if (INTEL_INFO(dev)->gen >= 6)
 		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	else if (INTEL_INFO(dev)->gen >= 4)
 		ring->dispatch_execbuffer = i965_dispatch_execbuffer;
 	else if (IS_I830(dev) || IS_845G(dev))
 		ring->dispatch_execbuffer = i830_dispatch_execbuffer;
 	else
 		ring->dispatch_execbuffer = i915_dispatch_execbuffer;
 	ring->init = init_render_ring;
 	ring->cleanup = render_ring_cleanup;
 	/* Workaround batchbuffer to combat CS tlb bug. */
 	if (HAS_BROKEN_CS_TLB(dev)) {
 		struct drm_i915_gem_object *obj;
 		int ret;
 		obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
 		if (obj == NULL) {
 			DRM_ERROR("Failed to allocate batch bo\n");
 			return -ENOMEM;
+		}
 		ret = i915_gem_object_pin(obj, 0, true, false);
 		if (ret != 0) {
 			drm_gem_object_unreference(&obj->base);
 			DRM_ERROR("Failed to ping batch bo\n");
 			return ret;
+		}
 		ring->private = obj;
+	}
 	return intel_init_ring_buffer(dev, ring);
+}
 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 	int ret;
 	ring->name = "render ring";
 	ring->id = RCS;
 	ring->mmio_base = RENDER_RING_BASE;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		/* non-kms not supported on gen6+ */
 		return -ENODEV;
+	}
 	/* Note: gem is not supported on gen5/ilk without kms (the corresponding
 	 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
 	 * the special gen5 functions. */
 	ring->add_request = i9xx_add_request;
 	if (INTEL_INFO(dev)->gen < 4)
 		ring->flush = gen2_render_ring_flush;
 	else
 		ring->flush = gen4_render_ring_flush;
 	ring->get_seqno = ring_get_seqno;
 	if (IS_GEN2(dev)) {
 		ring->irq_get = i8xx_ring_get_irq;
 		ring->irq_put = i8xx_ring_put_irq;
 	} else {
 		ring->irq_get = i9xx_ring_get_irq;
 		ring->irq_put = i9xx_ring_put_irq;
+	}
 	ring->irq_enable_mask = I915_USER_INTERRUPT;
 	ring->write_tail = ring_write_tail;
 	if (INTEL_INFO(dev)->gen >= 4)
 		ring->dispatch_execbuffer = i965_dispatch_execbuffer;
 	else if (IS_I830(dev) || IS_845G(dev))
 		ring->dispatch_execbuffer = i830_dispatch_execbuffer;
 	else
 		ring->dispatch_execbuffer = i915_dispatch_execbuffer;
 	ring->init = init_render_ring;
 	ring->cleanup = render_ring_cleanup;
 	ring->dev = dev;
 	INIT_LIST_HEAD(&ring->active_list);
 	INIT_LIST_HEAD(&ring->request_list);
 	ring->size = size;
 	ring->effective_size = ring->size;
 	if (IS_I830(ring->dev) || IS_845G(ring->dev))
 		ring->effective_size -= 128;
 #ifdef __NetBSD__
 	ring->virtual_start_map.offset = start;
 	ring->virtual_start_map.size = size;
 	ring->virtual_start_map.type = _DRM_REGISTERS;
 	ring->virtual_start_map.flags = 0;
 	ring->virtual_start_map.flags |= _DRM_RESTRICTED;
 	ring->virtual_start_map.flags |= _DRM_KERNEL;
 	ring->virtual_start_map.flags |= _DRM_WRITE_COMBINING;
 	ring->virtual_start_map.flags |= _DRM_DRIVER;
 	ret = drm_ioremap(dev, &ring->virtual_start_map);
 	if (ret) {
 		DRM_ERROR("cannot ioremap virtual address for ring buffer\n");
 		return ret;
+	}
 	ring->virtual_start_mapped = true;
 #else
 	ring->virtual_start = ioremap_wc(start, size);
 	if (ring->virtual_start == NULL) {
 		DRM_ERROR("can not ioremap virtual address for"
 			  " ring buffer\n");
 		return -ENOMEM;
+	}
 #endif
 	if (!I915_NEED_GFX_HWS(dev)) {
 		ret = init_phys_hws_pga(ring);
 		if (ret)
 			return ret;
+	}
 	return 0;
+}
 int intel_init_bsd_ring_buffer(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
 	ring->name = "bsd ring";
 	ring->id = VCS;
 	ring->write_tail = ring_write_tail;
 	if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		ring->mmio_base = GEN6_BSD_RING_BASE;
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev))
 			ring->write_tail = gen6_bsd_ring_write_tail;
 		ring->flush = gen6_ring_flush;
 		ring->add_request = gen6_add_request;
 		ring->get_seqno = gen6_ring_get_seqno;
 		ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
 		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 		ring->sync_to = gen6_ring_sync;
 		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
 		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
 		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
 		ring->signal_mbox[0] = GEN6_RVSYNC;
 		ring->signal_mbox[1] = GEN6_BVSYNC;
 	} else {
 		ring->mmio_base = BSD_RING_BASE;
 		ring->flush = bsd_ring_flush;
 		ring->add_request = i9xx_add_request;
 		ring->get_seqno = ring_get_seqno;
 		if (IS_GEN5(dev)) {
 			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
 			ring->irq_get = gen5_ring_get_irq;
 			ring->irq_put = gen5_ring_put_irq;
 		} else {
 			ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
 			ring->irq_get = i9xx_ring_get_irq;
 			ring->irq_put = i9xx_ring_put_irq;
+		}
 		ring->dispatch_execbuffer = i965_dispatch_execbuffer;
+	}
 	ring->init = init_ring_common;
 	return intel_init_ring_buffer(dev, ring);
+}
 int intel_init_blt_ring_buffer(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
 	ring->name = "blitter ring";
 	ring->id = BCS;
 	ring->mmio_base = BLT_RING_BASE;
 	ring->write_tail = ring_write_tail;
 	ring->flush = blt_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
 	ring->irq_get = gen6_ring_get_irq;
 	ring->irq_put = gen6_ring_put_irq;
 	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	ring->sync_to = gen6_ring_sync;
 	ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
 	ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
 	ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
 	ring->signal_mbox[0] = GEN6_RBSYNC;
 	ring->signal_mbox[1] = GEN6_VBSYNC;
 	ring->init = init_ring_common;
 	return intel_init_ring_buffer(dev, ring);
+}
 int
 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
+{
 	int ret;
 	if (!ring->gpu_caches_dirty)
 		return 0;
 	ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 	trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
 	ring->gpu_caches_dirty = false;
 	return 0;
+}
 int
 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
+{
 	uint32_t flush_domains;
 	int ret;
 	flush_domains = 0;
 	if (ring->gpu_caches_dirty)
 		flush_domains = I915_GEM_GPU_DOMAINS;
 	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
 	if (ret)
 		return ret;
 	trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
 	ring->gpu_caches_dirty = false;
 	return 0;
+}

 @@ -1,253 +1,257 @@
 #ifndef _INTEL_RINGBUFFER_H_
 #define _INTEL_RINGBUFFER_H_
 #include <asm/bug.h>
 /*
  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
+ *
  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  * cacheline, the Head Pointer must not be greater than the Tail
  * Pointer."
  */
 #define I915_RING_FREE_SPACE 64
 struct  intel_hw_status_page {
 	u32		*page_addr;
 	unsigned int	gfx_addr;
 	struct		drm_i915_gem_object *obj;
 };
 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
 struct  intel_ring_buffer {
 	const char	*name;
 	enum intel_ring_id {
 		RCS = 0x0,
 		VCS,
 		BCS,
 	} id;
 #define I915_NUM_RINGS 3
 	u32		mmio_base;
 #ifdef __NetBSD__
 	struct drm_local_map	virtual_start_map;
 	bool			virtual_start_mapped;
 #else
 	void		__iomem *virtual_start;
 #endif
 	struct		drm_device *dev;
 	struct		drm_i915_gem_object *obj;
 	u32		head;
 	u32		tail;
 	int		space;
 	int		size;
 	int		effective_size;
 	struct intel_hw_status_page status_page;
 	/** We track the position of the requests in the ring buffer, and
 	 * when each is retired we increment last_retired_head as the GPU
 	 * must have finished processing the request and so we know we
 	 * can advance the ringbuffer up to that position.
+	 *
 	 * last_retired_head is set to -1 after the value is consumed so
 	 * we can detect new retirements.
 	 */
 	u32		last_retired_head;
 	u32		irq_refcount;		/* protected by dev_priv->irq_lock */
 	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
 	u32		trace_irq_seqno;
 	u32		sync_seqno[I915_NUM_RINGS-1];
 	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
 	void		(*irq_put)(struct intel_ring_buffer *ring);
 	int		(*init)(struct intel_ring_buffer *ring);
 	void		(*write_tail)(struct intel_ring_buffer *ring,
 				      u32 value);
 	int __must_check (*flush)(struct intel_ring_buffer *ring,
 				  u32	invalidate_domains,
 				  u32	flush_domains);
 	int		(*add_request)(struct intel_ring_buffer *ring);
 	/* Some chipsets are not quite as coherent as advertised and need
 	 * an expensive kick to force a true read of the up-to-date seqno.
 	 * However, the up-to-date seqno is not always required and the last
 	 * seen value is good enough. Note that the seqno will always be
 	 * monotonic, even if not coherent.
 	 */
 	u32		(*get_seqno)(struct intel_ring_buffer *ring,
 				     bool lazy_coherency);
 	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
 					       u32 offset, u32 length,
 					       unsigned flags);
 #define I915_DISPATCH_SECURE 0x1
 #define I915_DISPATCH_PINNED 0x2
 	void		(*cleanup)(struct intel_ring_buffer *ring);
 	int		(*sync_to)(struct intel_ring_buffer *ring,
 				   struct intel_ring_buffer *to,
 				   u32 seqno);
 	u32		semaphore_register[3]; /*our mbox written by others */
 	u32		signal_mbox[2]; /* mboxes this ring signals to */
 	/**
 	 * List of objects currently involved in rendering from the
 	 * ringbuffer.
+	 *
 	 * Includes buffers having the contents of their GPU caches
 	 * flushed, not necessarily primitives.  last_rendering_seqno
 	 * represents when the rendering involved will be completed.
+	 *
 	 * A reference is held on the buffer while on this list.
 	 */
 	struct list_head active_list;
 	/**
 	 * List of breadcrumbs associated with GPU requests currently
 	 * outstanding.
 	 */
 	struct list_head request_list;
 	/**
 	 * Do we have some not yet emitted requests outstanding?
 	 */
 	u32 outstanding_lazy_request;
 	bool gpu_caches_dirty;
 #ifdef __NetBSD__
 	drm_waitqueue_t irq_queue;
 #else
 	wait_queue_head_t irq_queue;
 #endif
 	/**
 	 * Do an explicit TLB flush before MI_SET_CONTEXT
 	 */
 	bool itlb_before_ctx_switch;
 	struct i915_hw_context *default_context;
 	struct drm_i915_gem_object *last_context_obj;
 	void *private;
 };
 static inline bool
 intel_ring_initialized(struct intel_ring_buffer *ring)
+{
 	return ring->obj != NULL;
+}
 static inline unsigned
 intel_ring_flag(struct intel_ring_buffer *ring)
+{
 	return 1 << ring->id;
+}
 static inline u32
 intel_ring_sync_index(struct intel_ring_buffer *ring,
 		      struct intel_ring_buffer *other)
+{
 	int idx;
 	/*
 	 * cs -> 0 = vcs, 1 = bcs
 	 * vcs -> 0 = bcs, 1 = cs,
 	 * bcs -> 0 = cs, 1 = vcs.
 	 */
 	idx = (other - ring) - 1;
 	if (idx < 0)
 		idx += I915_NUM_RINGS;
 	return idx;
+}
 static inline u32
 intel_read_status_page(struct intel_ring_buffer *ring,
 		       int reg)
+{
 	/* Ensure that the compiler doesn't optimize away the load. */
 	barrier();
 	return ring->status_page.page_addr[reg];
+}
 /**
  * Reads a dword out of the status page, which is written to from the command
  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
  * MI_STORE_DATA_IMM.
+ *
  * The following dwords have a reserved meaning:
  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
  * 0x04: ring 0 head pointer
  * 0x05: ring 1 head pointer (915-class)
  * 0x06: ring 2 head pointer (915-class)
  * 0x10-0x1b: Context status DWords (GM45)
  * 0x1f: Last written status offset. (GM45)
+ *
  * The area from dword 0x20 to 0x3ff is available for driver usage.
  */
 #define I915_GEM_HWS_INDEX		0x20
 #define I915_GEM_HWS_SCRATCH_INDEX	0x30
 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 				   u32 data)
+{
 #ifdef __NetBSD__
 	DRM_WRITE32(&ring->virtual_start_map, ring->tail, data);
 #else
 	iowrite32(data, ring->virtual_start + ring->tail);
 #endif
 	ring->tail += 4;
+}
 void intel_ring_advance(struct intel_ring_buffer *ring);
 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 int intel_init_render_ring_buffer(struct drm_device *dev);
 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 int intel_init_blt_ring_buffer(struct drm_device *dev);
 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
+{
 	return ring->tail;
+}
 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
+{
 	BUG_ON(ring->outstanding_lazy_request == 0);
 	return ring->outstanding_lazy_request;
+}
 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
+{
 	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 		ring->trace_irq_seqno = seqno;
+}
 /* DRI warts */
 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 #endif /* _INTEL_RINGBUFFER_H_ */