| @@ -1560,38 +1560,54 @@ int i915_driver_load(struct drm_device * | | | @@ -1560,38 +1560,54 @@ int i915_driver_load(struct drm_device * |
| 1560 | ret = i915_gem_gtt_init(dev); | | 1560 | ret = i915_gem_gtt_init(dev); |
| 1561 | if (ret) | | 1561 | if (ret) |
| 1562 | goto put_bridge; | | 1562 | goto put_bridge; |
| 1563 | | | 1563 | |
| 1564 | #ifndef __NetBSD__ /* XXX fb */ | | 1564 | #ifndef __NetBSD__ /* XXX fb */ |
| 1565 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | | 1565 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1566 | i915_kick_out_firmware_fb(dev_priv); | | 1566 | i915_kick_out_firmware_fb(dev_priv); |
| 1567 | #endif | | 1567 | #endif |
| 1568 | | | 1568 | |
| 1569 | pci_set_master(dev->pdev); | | 1569 | pci_set_master(dev->pdev); |
| 1570 | | | 1570 | |
| 1571 | /* overlay on gen2 is broken and can't address above 1G */ | | 1571 | /* overlay on gen2 is broken and can't address above 1G */ |
| 1572 | if (IS_GEN2(dev)) | | 1572 | if (IS_GEN2(dev)) |
| | | 1573 | #ifdef __NetBSD__ |
| | | 1574 | { |
| | | 1575 | ret = drm_limit_dma_space(dev, 0, 0x3fffffffUL); |
| | | 1576 | if (ret) |
| | | 1577 | goto put_gmch; |
| | | 1578 | } |
| | | 1579 | #else |
| 1573 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | | 1580 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
| | | 1581 | #endif |
| 1574 | | | 1582 | |
| 1575 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) | | 1583 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| 1576 | * using 32bit addressing, overwriting memory if HWS is located | | 1584 | * using 32bit addressing, overwriting memory if HWS is located |
| 1577 | * above 4GB. | | 1585 | * above 4GB. |
| 1578 | * | | 1586 | * |
| 1579 | * The documentation also mentions an issue with undefined | | 1587 | * The documentation also mentions an issue with undefined |
| 1580 | * behaviour if any general state is accessed within a page above 4GB, | | 1588 | * behaviour if any general state is accessed within a page above 4GB, |
| 1581 | * which also needs to be handled carefully. | | 1589 | * which also needs to be handled carefully. |
| 1582 | */ | | 1590 | */ |
| 1583 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | | 1591 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| | | 1592 | #ifdef __NetBSD__ |
| | | 1593 | { |
| | | 1594 | ret = drm_limit_dma_space(dev, 0, 0xffffffffUL); |
| | | 1595 | if (ret) |
| | | 1596 | goto put_gmch; |
| | | 1597 | } |
| | | 1598 | #else |
| 1584 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | | 1599 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
| | | 1600 | #endif |
| 1585 | | | 1601 | |
| 1586 | mmio_bar = IS_GEN2(dev) ? 1 : 0; | | 1602 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
| 1587 | /* Before gen4, the registers and the GTT are behind different BARs. | | 1603 | /* Before gen4, the registers and the GTT are behind different BARs. |
| 1588 | * However, from gen4 onwards, the registers and the GTT are shared | | 1604 | * However, from gen4 onwards, the registers and the GTT are shared |
| 1589 | * in the same BAR, so we want to restrict this ioremap from | | 1605 | * in the same BAR, so we want to restrict this ioremap from |
| 1590 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | | 1606 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
| 1591 | * the register BAR remains the same size for all the earlier | | 1607 | * the register BAR remains the same size for all the earlier |
| 1592 | * generations up to Ironlake. | | 1608 | * generations up to Ironlake. |
| 1593 | */ | | 1609 | */ |
| 1594 | if (info->gen < 5) | | 1610 | if (info->gen < 5) |
| 1595 | mmio_size = 512*1024; | | 1611 | mmio_size = 512*1024; |
| 1596 | else | | 1612 | else |
| 1597 | mmio_size = 2*1024*1024; | | 1613 | mmio_size = 2*1024*1024; |