| @@ -1,1383 +1,1387 @@ | | | @@ -1,1383 +1,1387 @@ |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- | | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | | 2 | */ |
3 | /* | | 3 | /* |
4 | * | | 4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | | 6 | * All Rights Reserved. |
7 | * | | 7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the | | 9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including | | 10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, | | 11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to | | 12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to | | 13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: | | 14 | * the following conditions: |
15 | * | | 15 | * |
16 | * The above copyright notice and this permission notice (including the | | 16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions | | 17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. | | 18 | * of the Software. |
19 | * | | 19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | | 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | | 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | | 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | | 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | | 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | | 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | | 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * | | 27 | * |
28 | */ | | 28 | */ |
29 | | | 29 | |
30 | #include <linux/device.h> | | 30 | #include <linux/device.h> |
31 | #include <linux/moduleparam.h> | | 31 | #include <linux/moduleparam.h> |
32 | #include <linux/time.h> | | 32 | #include <linux/time.h> |
33 | #include <drm/drmP.h> | | 33 | #include <drm/drmP.h> |
34 | #include <drm/i915_drm.h> | | 34 | #include <drm/i915_drm.h> |
35 | #include "i915_drv.h" | | 35 | #include "i915_drv.h" |
36 | #include "i915_trace.h" | | 36 | #include "i915_trace.h" |
37 | #include "intel_drv.h" | | 37 | #include "intel_drv.h" |
38 | | | 38 | |
39 | #include <linux/console.h> | | 39 | #include <linux/console.h> |
40 | #include <linux/module.h> | | 40 | #include <linux/module.h> |
41 | #include <drm/drm_crtc_helper.h> | | 41 | #include <drm/drm_crtc_helper.h> |
42 | | | 42 | |
43 | static int i915_modeset __read_mostly = -1; | | 43 | static int i915_modeset __read_mostly = -1; |
44 | module_param_named(modeset, i915_modeset, int, 0400); | | 44 | module_param_named(modeset, i915_modeset, int, 0400); |
45 | MODULE_PARM_DESC(modeset, | | 45 | MODULE_PARM_DESC(modeset, |
46 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | | 46 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
47 | "1=on, -1=force vga console preference [default])"); | | 47 | "1=on, -1=force vga console preference [default])"); |
48 | | | 48 | |
49 | unsigned int i915_fbpercrtc __always_unused = 0; | | 49 | unsigned int i915_fbpercrtc __always_unused = 0; |
50 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | | 50 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
51 | | | 51 | |
52 | int i915_panel_ignore_lid __read_mostly = 1; | | 52 | int i915_panel_ignore_lid __read_mostly = 1; |
53 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); | | 53 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
54 | MODULE_PARM_DESC(panel_ignore_lid, | | 54 | MODULE_PARM_DESC(panel_ignore_lid, |
55 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " | | 55 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
56 | "-1=force lid closed, -2=force lid open)"); | | 56 | "-1=force lid closed, -2=force lid open)"); |
57 | | | 57 | |
58 | unsigned int i915_powersave __read_mostly = 1; | | 58 | unsigned int i915_powersave __read_mostly = 1; |
59 | module_param_named(powersave, i915_powersave, int, 0600); | | 59 | module_param_named(powersave, i915_powersave, int, 0600); |
60 | MODULE_PARM_DESC(powersave, | | 60 | MODULE_PARM_DESC(powersave, |
61 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | | 61 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
62 | | | 62 | |
63 | int i915_semaphores __read_mostly = -1; | | 63 | int i915_semaphores __read_mostly = -1; |
64 | module_param_named(semaphores, i915_semaphores, int, 0600); | | 64 | module_param_named(semaphores, i915_semaphores, int, 0600); |
65 | MODULE_PARM_DESC(semaphores, | | 65 | MODULE_PARM_DESC(semaphores, |
66 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); | | 66 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
67 | | | 67 | |
68 | int i915_enable_rc6 __read_mostly = -1; | | 68 | int i915_enable_rc6 __read_mostly = -1; |
69 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); | | 69 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
70 | MODULE_PARM_DESC(i915_enable_rc6, | | 70 | MODULE_PARM_DESC(i915_enable_rc6, |
71 | "Enable power-saving render C-state 6. " | | 71 | "Enable power-saving render C-state 6. " |
72 | "Different stages can be selected via bitmask values " | | 72 | "Different stages can be selected via bitmask values " |
73 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | | 73 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " |
74 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | | 74 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " |
75 | "default: -1 (use per-chip default)"); | | 75 | "default: -1 (use per-chip default)"); |
76 | | | 76 | |
77 | int i915_enable_fbc __read_mostly = -1; | | 77 | int i915_enable_fbc __read_mostly = -1; |
78 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); | | 78 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
79 | MODULE_PARM_DESC(i915_enable_fbc, | | 79 | MODULE_PARM_DESC(i915_enable_fbc, |
80 | "Enable frame buffer compression for power savings " | | 80 | "Enable frame buffer compression for power savings " |
81 | "(default: -1 (use per-chip default))"); | | 81 | "(default: -1 (use per-chip default))"); |
82 | | | 82 | |
83 | unsigned int i915_lvds_downclock __read_mostly = 0; | | 83 | unsigned int i915_lvds_downclock __read_mostly = 0; |
84 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | | 84 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
85 | MODULE_PARM_DESC(lvds_downclock, | | 85 | MODULE_PARM_DESC(lvds_downclock, |
86 | "Use panel (LVDS/eDP) downclocking for power savings " | | 86 | "Use panel (LVDS/eDP) downclocking for power savings " |
87 | "(default: false)"); | | 87 | "(default: false)"); |
88 | | | 88 | |
89 | int i915_lvds_channel_mode __read_mostly; | | 89 | int i915_lvds_channel_mode __read_mostly; |
90 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | | 90 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); |
91 | MODULE_PARM_DESC(lvds_channel_mode, | | 91 | MODULE_PARM_DESC(lvds_channel_mode, |
92 | "Specify LVDS channel mode " | | 92 | "Specify LVDS channel mode " |
93 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | | 93 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
94 | | | 94 | |
95 | int i915_panel_use_ssc __read_mostly = -1; | | 95 | int i915_panel_use_ssc __read_mostly = -1; |
96 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); | | 96 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
97 | MODULE_PARM_DESC(lvds_use_ssc, | | 97 | MODULE_PARM_DESC(lvds_use_ssc, |
98 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | | 98 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
99 | "(default: auto from VBT)"); | | 99 | "(default: auto from VBT)"); |
100 | | | 100 | |
101 | int i915_vbt_sdvo_panel_type __read_mostly = -1; | | 101 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
102 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); | | 102 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
103 | MODULE_PARM_DESC(vbt_sdvo_panel_type, | | 103 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
104 | "Override/Ignore selection of SDVO panel mode in the VBT " | | 104 | "Override/Ignore selection of SDVO panel mode in the VBT " |
105 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | | 105 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
106 | | | 106 | |
107 | static bool i915_try_reset __read_mostly = true; | | 107 | static bool i915_try_reset __read_mostly = true; |
108 | module_param_named(reset, i915_try_reset, bool, 0600); | | 108 | module_param_named(reset, i915_try_reset, bool, 0600); |
109 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); | | 109 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
110 | | | 110 | |
111 | bool i915_enable_hangcheck __read_mostly = true; | | 111 | bool i915_enable_hangcheck __read_mostly = true; |
112 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); | | 112 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
113 | MODULE_PARM_DESC(enable_hangcheck, | | 113 | MODULE_PARM_DESC(enable_hangcheck, |
114 | "Periodically check GPU activity for detecting hangs. " | | 114 | "Periodically check GPU activity for detecting hangs. " |
115 | "WARNING: Disabling this can cause system wide hangs. " | | 115 | "WARNING: Disabling this can cause system wide hangs. " |
116 | "(default: true)"); | | 116 | "(default: true)"); |
117 | | | 117 | |
118 | int i915_enable_ppgtt __read_mostly = -1; | | 118 | int i915_enable_ppgtt __read_mostly = -1; |
119 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | | 119 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
120 | MODULE_PARM_DESC(i915_enable_ppgtt, | | 120 | MODULE_PARM_DESC(i915_enable_ppgtt, |
121 | "Enable PPGTT (default: true)"); | | 121 | "Enable PPGTT (default: true)"); |
122 | | | 122 | |
123 | unsigned int i915_preliminary_hw_support __read_mostly = 0; | | 123 | unsigned int i915_preliminary_hw_support __read_mostly = 0; |
124 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); | | 124 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
125 | MODULE_PARM_DESC(preliminary_hw_support, | | 125 | MODULE_PARM_DESC(preliminary_hw_support, |
126 | "Enable preliminary hardware support. " | | 126 | "Enable preliminary hardware support. " |
127 | "Enable Haswell and ValleyView Support. " | | 127 | "Enable Haswell and ValleyView Support. " |
128 | "(default: false)"); | | 128 | "(default: false)"); |
129 | | | 129 | |
130 | static struct drm_driver driver; | | 130 | static struct drm_driver driver; |
131 | extern int intel_agp_enabled; | | 131 | extern int intel_agp_enabled; |
132 | | | 132 | |
133 | #define INTEL_VGA_DEVICE(id, info) { \ | | 133 | #define INTEL_VGA_DEVICE(id, info) { \ |
134 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ | | 134 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
135 | .class_mask = 0xff0000, \ | | 135 | .class_mask = 0xff0000, \ |
136 | .vendor = 0x8086, \ | | 136 | .vendor = 0x8086, \ |
137 | .device = id, \ | | 137 | .device = id, \ |
138 | .subvendor = PCI_ANY_ID, \ | | 138 | .subvendor = PCI_ANY_ID, \ |
139 | .subdevice = PCI_ANY_ID, \ | | 139 | .subdevice = PCI_ANY_ID, \ |
140 | .driver_data = (unsigned long) info } | | 140 | .driver_data = (unsigned long) info } |
141 | | | 141 | |
142 | static const struct intel_device_info intel_i830_info = { | | 142 | static const struct intel_device_info intel_i830_info = { |
143 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, | | 143 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
144 | .has_overlay = 1, .overlay_needs_physical = 1, | | 144 | .has_overlay = 1, .overlay_needs_physical = 1, |
145 | }; | | 145 | }; |
146 | | | 146 | |
147 | static const struct intel_device_info intel_845g_info = { | | 147 | static const struct intel_device_info intel_845g_info = { |
148 | .gen = 2, | | 148 | .gen = 2, |
149 | .has_overlay = 1, .overlay_needs_physical = 1, | | 149 | .has_overlay = 1, .overlay_needs_physical = 1, |
150 | }; | | 150 | }; |
151 | | | 151 | |
152 | static const struct intel_device_info intel_i85x_info = { | | 152 | static const struct intel_device_info intel_i85x_info = { |
153 | .gen = 2, .is_i85x = 1, .is_mobile = 1, | | 153 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
154 | .cursor_needs_physical = 1, | | 154 | .cursor_needs_physical = 1, |
155 | .has_overlay = 1, .overlay_needs_physical = 1, | | 155 | .has_overlay = 1, .overlay_needs_physical = 1, |
156 | }; | | 156 | }; |
157 | | | 157 | |
158 | static const struct intel_device_info intel_i865g_info = { | | 158 | static const struct intel_device_info intel_i865g_info = { |
159 | .gen = 2, | | 159 | .gen = 2, |
160 | .has_overlay = 1, .overlay_needs_physical = 1, | | 160 | .has_overlay = 1, .overlay_needs_physical = 1, |
161 | }; | | 161 | }; |
162 | | | 162 | |
163 | static const struct intel_device_info intel_i915g_info = { | | 163 | static const struct intel_device_info intel_i915g_info = { |
164 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, | | 164 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
165 | .has_overlay = 1, .overlay_needs_physical = 1, | | 165 | .has_overlay = 1, .overlay_needs_physical = 1, |
166 | }; | | 166 | }; |
167 | static const struct intel_device_info intel_i915gm_info = { | | 167 | static const struct intel_device_info intel_i915gm_info = { |
168 | .gen = 3, .is_mobile = 1, | | 168 | .gen = 3, .is_mobile = 1, |
169 | .cursor_needs_physical = 1, | | 169 | .cursor_needs_physical = 1, |
170 | .has_overlay = 1, .overlay_needs_physical = 1, | | 170 | .has_overlay = 1, .overlay_needs_physical = 1, |
171 | .supports_tv = 1, | | 171 | .supports_tv = 1, |
172 | }; | | 172 | }; |
173 | static const struct intel_device_info intel_i945g_info = { | | 173 | static const struct intel_device_info intel_i945g_info = { |
174 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, | | 174 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
175 | .has_overlay = 1, .overlay_needs_physical = 1, | | 175 | .has_overlay = 1, .overlay_needs_physical = 1, |
176 | }; | | 176 | }; |
177 | static const struct intel_device_info intel_i945gm_info = { | | 177 | static const struct intel_device_info intel_i945gm_info = { |
178 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, | | 178 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
179 | .has_hotplug = 1, .cursor_needs_physical = 1, | | 179 | .has_hotplug = 1, .cursor_needs_physical = 1, |
180 | .has_overlay = 1, .overlay_needs_physical = 1, | | 180 | .has_overlay = 1, .overlay_needs_physical = 1, |
181 | .supports_tv = 1, | | 181 | .supports_tv = 1, |
182 | }; | | 182 | }; |
183 | | | 183 | |
184 | static const struct intel_device_info intel_i965g_info = { | | 184 | static const struct intel_device_info intel_i965g_info = { |
185 | .gen = 4, .is_broadwater = 1, | | 185 | .gen = 4, .is_broadwater = 1, |
186 | .has_hotplug = 1, | | 186 | .has_hotplug = 1, |
187 | .has_overlay = 1, | | 187 | .has_overlay = 1, |
188 | }; | | 188 | }; |
189 | | | 189 | |
190 | static const struct intel_device_info intel_i965gm_info = { | | 190 | static const struct intel_device_info intel_i965gm_info = { |
191 | .gen = 4, .is_crestline = 1, | | 191 | .gen = 4, .is_crestline = 1, |
192 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, | | 192 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
193 | .has_overlay = 1, | | 193 | .has_overlay = 1, |
194 | .supports_tv = 1, | | 194 | .supports_tv = 1, |
195 | }; | | 195 | }; |
196 | | | 196 | |
197 | static const struct intel_device_info intel_g33_info = { | | 197 | static const struct intel_device_info intel_g33_info = { |
198 | .gen = 3, .is_g33 = 1, | | 198 | .gen = 3, .is_g33 = 1, |
199 | .need_gfx_hws = 1, .has_hotplug = 1, | | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
200 | .has_overlay = 1, | | 200 | .has_overlay = 1, |
201 | }; | | 201 | }; |
202 | | | 202 | |
203 | static const struct intel_device_info intel_g45_info = { | | 203 | static const struct intel_device_info intel_g45_info = { |
204 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, | | 204 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
205 | .has_pipe_cxsr = 1, .has_hotplug = 1, | | 205 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
206 | .has_bsd_ring = 1, | | 206 | .has_bsd_ring = 1, |
207 | }; | | 207 | }; |
208 | | | 208 | |
209 | static const struct intel_device_info intel_gm45_info = { | | 209 | static const struct intel_device_info intel_gm45_info = { |
210 | .gen = 4, .is_g4x = 1, | | 210 | .gen = 4, .is_g4x = 1, |
211 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, | | 211 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
212 | .has_pipe_cxsr = 1, .has_hotplug = 1, | | 212 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
213 | .supports_tv = 1, | | 213 | .supports_tv = 1, |
214 | .has_bsd_ring = 1, | | 214 | .has_bsd_ring = 1, |
215 | }; | | 215 | }; |
216 | | | 216 | |
217 | static const struct intel_device_info intel_pineview_info = { | | 217 | static const struct intel_device_info intel_pineview_info = { |
218 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, | | 218 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
219 | .need_gfx_hws = 1, .has_hotplug = 1, | | 219 | .need_gfx_hws = 1, .has_hotplug = 1, |
220 | .has_overlay = 1, | | 220 | .has_overlay = 1, |
221 | }; | | 221 | }; |
222 | | | 222 | |
223 | static const struct intel_device_info intel_ironlake_d_info = { | | 223 | static const struct intel_device_info intel_ironlake_d_info = { |
224 | .gen = 5, | | 224 | .gen = 5, |
225 | .need_gfx_hws = 1, .has_hotplug = 1, | | 225 | .need_gfx_hws = 1, .has_hotplug = 1, |
226 | .has_bsd_ring = 1, | | 226 | .has_bsd_ring = 1, |
227 | }; | | 227 | }; |
228 | | | 228 | |
229 | static const struct intel_device_info intel_ironlake_m_info = { | | 229 | static const struct intel_device_info intel_ironlake_m_info = { |
230 | .gen = 5, .is_mobile = 1, | | 230 | .gen = 5, .is_mobile = 1, |
231 | .need_gfx_hws = 1, .has_hotplug = 1, | | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
232 | .has_fbc = 1, | | 232 | .has_fbc = 1, |
233 | .has_bsd_ring = 1, | | 233 | .has_bsd_ring = 1, |
234 | }; | | 234 | }; |
235 | | | 235 | |
236 | static const struct intel_device_info intel_sandybridge_d_info = { | | 236 | static const struct intel_device_info intel_sandybridge_d_info = { |
237 | .gen = 6, | | 237 | .gen = 6, |
238 | .need_gfx_hws = 1, .has_hotplug = 1, | | 238 | .need_gfx_hws = 1, .has_hotplug = 1, |
239 | .has_bsd_ring = 1, | | 239 | .has_bsd_ring = 1, |
240 | .has_blt_ring = 1, | | 240 | .has_blt_ring = 1, |
241 | .has_llc = 1, | | 241 | .has_llc = 1, |
242 | .has_force_wake = 1, | | 242 | .has_force_wake = 1, |
243 | }; | | 243 | }; |
244 | | | 244 | |
245 | static const struct intel_device_info intel_sandybridge_m_info = { | | 245 | static const struct intel_device_info intel_sandybridge_m_info = { |
246 | .gen = 6, .is_mobile = 1, | | 246 | .gen = 6, .is_mobile = 1, |
247 | .need_gfx_hws = 1, .has_hotplug = 1, | | 247 | .need_gfx_hws = 1, .has_hotplug = 1, |
248 | .has_fbc = 1, | | 248 | .has_fbc = 1, |
249 | .has_bsd_ring = 1, | | 249 | .has_bsd_ring = 1, |
250 | .has_blt_ring = 1, | | 250 | .has_blt_ring = 1, |
251 | .has_llc = 1, | | 251 | .has_llc = 1, |
252 | .has_force_wake = 1, | | 252 | .has_force_wake = 1, |
253 | }; | | 253 | }; |
254 | | | 254 | |
255 | static const struct intel_device_info intel_ivybridge_d_info = { | | 255 | static const struct intel_device_info intel_ivybridge_d_info = { |
256 | .is_ivybridge = 1, .gen = 7, | | 256 | .is_ivybridge = 1, .gen = 7, |
257 | .need_gfx_hws = 1, .has_hotplug = 1, | | 257 | .need_gfx_hws = 1, .has_hotplug = 1, |
258 | .has_bsd_ring = 1, | | 258 | .has_bsd_ring = 1, |
259 | .has_blt_ring = 1, | | 259 | .has_blt_ring = 1, |
260 | .has_llc = 1, | | 260 | .has_llc = 1, |
261 | .has_force_wake = 1, | | 261 | .has_force_wake = 1, |
262 | }; | | 262 | }; |
263 | | | 263 | |
264 | static const struct intel_device_info intel_ivybridge_m_info = { | | 264 | static const struct intel_device_info intel_ivybridge_m_info = { |
265 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | | 265 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
266 | .need_gfx_hws = 1, .has_hotplug = 1, | | 266 | .need_gfx_hws = 1, .has_hotplug = 1, |
267 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | | 267 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
268 | .has_bsd_ring = 1, | | 268 | .has_bsd_ring = 1, |
269 | .has_blt_ring = 1, | | 269 | .has_blt_ring = 1, |
270 | .has_llc = 1, | | 270 | .has_llc = 1, |
271 | .has_force_wake = 1, | | 271 | .has_force_wake = 1, |
272 | }; | | 272 | }; |
273 | | | 273 | |
274 | static const struct intel_device_info intel_valleyview_m_info = { | | 274 | static const struct intel_device_info intel_valleyview_m_info = { |
275 | .gen = 7, .is_mobile = 1, | | 275 | .gen = 7, .is_mobile = 1, |
276 | .need_gfx_hws = 1, .has_hotplug = 1, | | 276 | .need_gfx_hws = 1, .has_hotplug = 1, |
277 | .has_fbc = 0, | | 277 | .has_fbc = 0, |
278 | .has_bsd_ring = 1, | | 278 | .has_bsd_ring = 1, |
279 | .has_blt_ring = 1, | | 279 | .has_blt_ring = 1, |
280 | .is_valleyview = 1, | | 280 | .is_valleyview = 1, |
281 | }; | | 281 | }; |
282 | | | 282 | |
283 | static const struct intel_device_info intel_valleyview_d_info = { | | 283 | static const struct intel_device_info intel_valleyview_d_info = { |
284 | .gen = 7, | | 284 | .gen = 7, |
285 | .need_gfx_hws = 1, .has_hotplug = 1, | | 285 | .need_gfx_hws = 1, .has_hotplug = 1, |
286 | .has_fbc = 0, | | 286 | .has_fbc = 0, |
287 | .has_bsd_ring = 1, | | 287 | .has_bsd_ring = 1, |
288 | .has_blt_ring = 1, | | 288 | .has_blt_ring = 1, |
289 | .is_valleyview = 1, | | 289 | .is_valleyview = 1, |
290 | }; | | 290 | }; |
291 | | | 291 | |
292 | static const struct intel_device_info intel_haswell_d_info = { | | 292 | static const struct intel_device_info intel_haswell_d_info = { |
293 | .is_haswell = 1, .gen = 7, | | 293 | .is_haswell = 1, .gen = 7, |
294 | .need_gfx_hws = 1, .has_hotplug = 1, | | 294 | .need_gfx_hws = 1, .has_hotplug = 1, |
295 | .has_bsd_ring = 1, | | 295 | .has_bsd_ring = 1, |
296 | .has_blt_ring = 1, | | 296 | .has_blt_ring = 1, |
297 | .has_llc = 1, | | 297 | .has_llc = 1, |
298 | .has_force_wake = 1, | | 298 | .has_force_wake = 1, |
299 | }; | | 299 | }; |
300 | | | 300 | |
301 | static const struct intel_device_info intel_haswell_m_info = { | | 301 | static const struct intel_device_info intel_haswell_m_info = { |
302 | .is_haswell = 1, .gen = 7, .is_mobile = 1, | | 302 | .is_haswell = 1, .gen = 7, .is_mobile = 1, |
303 | .need_gfx_hws = 1, .has_hotplug = 1, | | 303 | .need_gfx_hws = 1, .has_hotplug = 1, |
304 | .has_bsd_ring = 1, | | 304 | .has_bsd_ring = 1, |
305 | .has_blt_ring = 1, | | 305 | .has_blt_ring = 1, |
306 | .has_llc = 1, | | 306 | .has_llc = 1, |
307 | .has_force_wake = 1, | | 307 | .has_force_wake = 1, |
308 | }; | | 308 | }; |
309 | | | 309 | |
310 | static const struct pci_device_id pciidlist[] = { /* aka */ | | 310 | static const struct pci_device_id pciidlist[] = { /* aka */ |
311 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | | 311 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ |
312 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | | 312 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ |
313 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | | 313 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ |
314 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), | | 314 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
315 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ | | 315 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
316 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | | 316 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
317 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | | 317 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
318 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | | 318 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
319 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | | 319 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
320 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | | 320 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
321 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | | 321 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
322 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | | 322 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
323 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | | 323 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
324 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | | 324 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
325 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | | 325 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
326 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | | 326 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
327 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | | 327 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
328 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | | 328 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
329 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | | 329 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
330 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | | 330 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
331 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | | 331 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
332 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | | 332 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
333 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | | 333 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
334 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | | 334 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
335 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | | 335 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
336 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | | 336 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
337 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ | | 337 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
338 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), | | 338 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
339 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | | 339 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
340 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | | 340 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
341 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | | 341 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
342 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), | | 342 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
343 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), | | 343 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
344 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | | 344 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
345 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), | | 345 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
346 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), | | 346 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
347 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), | | 347 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
348 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), | | 348 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
349 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ | | 349 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
350 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | | 350 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
351 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | | 351 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
352 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | | 352 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
353 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | | 353 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
354 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ | | 354 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
355 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ | | 355 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
356 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | | 356 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
357 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ | | 357 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
358 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ | | 358 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
359 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | | 359 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
360 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ | | 360 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
361 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ | | 361 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
362 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | | 362 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
363 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ | | 363 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
364 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ | | 364 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
365 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ | | 365 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
366 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ | | 366 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
367 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ | | 367 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
368 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ | | 368 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
369 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ | | 369 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
370 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ | | 370 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
371 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ | | 371 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
372 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ | | 372 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
373 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ | | 373 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
374 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ | | 374 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
375 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ | | 375 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
376 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ | | 376 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
377 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ | | 377 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
378 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ | | 378 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
379 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ | | 379 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
380 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ | | 380 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
381 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ | | 381 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
382 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ | | 382 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ |
383 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ | | 383 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
384 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ | | 384 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ |
385 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ | | 385 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ |
386 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ | | 386 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
387 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ | | 387 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ |
388 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ | | 388 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ |
389 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ | | 389 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
390 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ | | 390 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ |
391 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), | | 391 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
392 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), | | 392 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
393 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | | 393 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
| | | 394 | #ifdef __NetBSD__ |
| | | 395 | {0, 0, 0, 0, 0, 0, 0} |
| | | 396 | #else |
394 | {0, 0, 0} | | 397 | {0, 0, 0} |
| | | 398 | #endif |
395 | }; | | 399 | }; |
396 | | | 400 | |
397 | #if defined(CONFIG_DRM_I915_KMS) | | 401 | #if defined(CONFIG_DRM_I915_KMS) |
398 | MODULE_DEVICE_TABLE(pci, pciidlist); | | 402 | MODULE_DEVICE_TABLE(pci, pciidlist); |
399 | #endif | | 403 | #endif |
400 | | | 404 | |
401 | void intel_detect_pch(struct drm_device *dev) | | 405 | void intel_detect_pch(struct drm_device *dev) |
402 | { | | 406 | { |
403 | struct drm_i915_private *dev_priv = dev->dev_private; | | 407 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | struct pci_dev *pch; | | 408 | struct pci_dev *pch; |
405 | | | 409 | |
406 | /* | | 410 | /* |
407 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | | 411 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
408 | * make graphics device passthrough work easy for VMM, that only | | 412 | * make graphics device passthrough work easy for VMM, that only |
409 | * need to expose ISA bridge to let driver know the real hardware | | 413 | * need to expose ISA bridge to let driver know the real hardware |
410 | * underneath. This is a requirement from virtualization team. | | 414 | * underneath. This is a requirement from virtualization team. |
411 | */ | | 415 | */ |
412 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | | 416 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
413 | if (pch) { | | 417 | if (pch) { |
414 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | | 418 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
415 | unsigned short id; | | 419 | unsigned short id; |
416 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | | 420 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
417 | dev_priv->pch_id = id; | | 421 | dev_priv->pch_id = id; |
418 | | | 422 | |
419 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { | | 423 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
420 | dev_priv->pch_type = PCH_IBX; | | 424 | dev_priv->pch_type = PCH_IBX; |
421 | dev_priv->num_pch_pll = 2; | | 425 | dev_priv->num_pch_pll = 2; |
422 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | | 426 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
423 | WARN_ON(!IS_GEN5(dev)); | | 427 | WARN_ON(!IS_GEN5(dev)); |
424 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | | 428 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
425 | dev_priv->pch_type = PCH_CPT; | | 429 | dev_priv->pch_type = PCH_CPT; |
426 | dev_priv->num_pch_pll = 2; | | 430 | dev_priv->num_pch_pll = 2; |
427 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | | 431 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
428 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); | | 432 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
429 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { | | 433 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
430 | /* PantherPoint is CPT compatible */ | | 434 | /* PantherPoint is CPT compatible */ |
431 | dev_priv->pch_type = PCH_CPT; | | 435 | dev_priv->pch_type = PCH_CPT; |
432 | dev_priv->num_pch_pll = 2; | | 436 | dev_priv->num_pch_pll = 2; |
433 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | | 437 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
434 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); | | 438 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
435 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { | | 439 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
436 | dev_priv->pch_type = PCH_LPT; | | 440 | dev_priv->pch_type = PCH_LPT; |
437 | dev_priv->num_pch_pll = 0; | | 441 | dev_priv->num_pch_pll = 0; |
438 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | | 442 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
439 | WARN_ON(!IS_HASWELL(dev)); | | 443 | WARN_ON(!IS_HASWELL(dev)); |
440 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | | 444 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
441 | dev_priv->pch_type = PCH_LPT; | | 445 | dev_priv->pch_type = PCH_LPT; |
442 | dev_priv->num_pch_pll = 0; | | 446 | dev_priv->num_pch_pll = 0; |
443 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | | 447 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
444 | WARN_ON(!IS_HASWELL(dev)); | | 448 | WARN_ON(!IS_HASWELL(dev)); |
445 | } | | 449 | } |
446 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); | | 450 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
447 | } | | 451 | } |
448 | pci_dev_put(pch); | | 452 | pci_dev_put(pch); |
449 | } | | 453 | } |
450 | } | | 454 | } |
451 | | | 455 | |
452 | bool i915_semaphore_is_enabled(struct drm_device *dev) | | 456 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
453 | { | | 457 | { |
454 | if (INTEL_INFO(dev)->gen < 6) | | 458 | if (INTEL_INFO(dev)->gen < 6) |
455 | return 0; | | 459 | return 0; |
456 | | | 460 | |
457 | if (i915_semaphores >= 0) | | 461 | if (i915_semaphores >= 0) |
458 | return i915_semaphores; | | 462 | return i915_semaphores; |
459 | | | 463 | |
460 | #ifdef CONFIG_INTEL_IOMMU | | 464 | #ifdef CONFIG_INTEL_IOMMU |
461 | /* Enable semaphores on SNB when IO remapping is off */ | | 465 | /* Enable semaphores on SNB when IO remapping is off */ |
462 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | | 466 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
463 | return false; | | 467 | return false; |
464 | #endif | | 468 | #endif |
465 | | | 469 | |
466 | return 1; | | 470 | return 1; |
467 | } | | 471 | } |
468 | | | 472 | |
469 | static int i915_drm_freeze(struct drm_device *dev) | | 473 | static int i915_drm_freeze(struct drm_device *dev) |
470 | { | | 474 | { |
471 | struct drm_i915_private *dev_priv = dev->dev_private; | | 475 | struct drm_i915_private *dev_priv = dev->dev_private; |
472 | | | 476 | |
473 | drm_kms_helper_poll_disable(dev); | | 477 | drm_kms_helper_poll_disable(dev); |
474 | | | 478 | |
475 | pci_save_state(dev->pdev); | | 479 | pci_save_state(dev->pdev); |
476 | | | 480 | |
477 | /* If KMS is active, we do the leavevt stuff here */ | | 481 | /* If KMS is active, we do the leavevt stuff here */ |
478 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | | 482 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
479 | int error = i915_gem_idle(dev); | | 483 | int error = i915_gem_idle(dev); |
480 | if (error) { | | 484 | if (error) { |
481 | dev_err(&dev->pdev->dev, | | 485 | dev_err(&dev->pdev->dev, |
482 | "GEM idle failed, resume might fail\n"); | | 486 | "GEM idle failed, resume might fail\n"); |
483 | return error; | | 487 | return error; |
484 | } | | 488 | } |
485 | | | 489 | |
486 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); | | 490 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
487 | | | 491 | |
488 | intel_modeset_disable(dev); | | 492 | intel_modeset_disable(dev); |
489 | | | 493 | |
490 | drm_irq_uninstall(dev); | | 494 | drm_irq_uninstall(dev); |
491 | } | | 495 | } |
492 | | | 496 | |
493 | i915_save_state(dev); | | 497 | i915_save_state(dev); |
494 | | | 498 | |
495 | intel_opregion_fini(dev); | | 499 | intel_opregion_fini(dev); |
496 | | | 500 | |
497 | /* Modeset on resume, not lid events */ | | 501 | /* Modeset on resume, not lid events */ |
498 | dev_priv->modeset_on_lid = 0; | | 502 | dev_priv->modeset_on_lid = 0; |
499 | | | 503 | |
500 | console_lock(); | | 504 | console_lock(); |
501 | intel_fbdev_set_suspend(dev, 1); | | 505 | intel_fbdev_set_suspend(dev, 1); |
502 | console_unlock(); | | 506 | console_unlock(); |
503 | | | 507 | |
504 | return 0; | | 508 | return 0; |
505 | } | | 509 | } |
506 | | | 510 | |
507 | int i915_suspend(struct drm_device *dev, pm_message_t state) | | 511 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
508 | { | | 512 | { |
509 | int error; | | 513 | int error; |
510 | | | 514 | |
511 | if (!dev || !dev->dev_private) { | | 515 | if (!dev || !dev->dev_private) { |
512 | DRM_ERROR("dev: %p\n", dev); | | 516 | DRM_ERROR("dev: %p\n", dev); |
513 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | | 517 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
514 | return -ENODEV; | | 518 | return -ENODEV; |
515 | } | | 519 | } |
516 | | | 520 | |
517 | if (state.event == PM_EVENT_PRETHAW) | | 521 | if (state.event == PM_EVENT_PRETHAW) |
518 | return 0; | | 522 | return 0; |
519 | | | 523 | |
520 | | | 524 | |
521 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | | 525 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
522 | return 0; | | 526 | return 0; |
523 | | | 527 | |
524 | error = i915_drm_freeze(dev); | | 528 | error = i915_drm_freeze(dev); |
525 | if (error) | | 529 | if (error) |
526 | return error; | | 530 | return error; |
527 | | | 531 | |
528 | if (state.event == PM_EVENT_SUSPEND) { | | 532 | if (state.event == PM_EVENT_SUSPEND) { |
529 | /* Shut down the device */ | | 533 | /* Shut down the device */ |
530 | pci_disable_device(dev->pdev); | | 534 | pci_disable_device(dev->pdev); |
531 | pci_set_power_state(dev->pdev, PCI_D3hot); | | 535 | pci_set_power_state(dev->pdev, PCI_D3hot); |
532 | } | | 536 | } |
533 | | | 537 | |
534 | return 0; | | 538 | return 0; |
535 | } | | 539 | } |
536 | | | 540 | |
537 | void intel_console_resume(struct work_struct *work) | | 541 | void intel_console_resume(struct work_struct *work) |
538 | { | | 542 | { |
539 | struct drm_i915_private *dev_priv = | | 543 | struct drm_i915_private *dev_priv = |
540 | container_of(work, struct drm_i915_private, | | 544 | container_of(work, struct drm_i915_private, |
541 | console_resume_work); | | 545 | console_resume_work); |
542 | struct drm_device *dev = dev_priv->dev; | | 546 | struct drm_device *dev = dev_priv->dev; |
543 | | | 547 | |
544 | console_lock(); | | 548 | console_lock(); |
545 | intel_fbdev_set_suspend(dev, 0); | | 549 | intel_fbdev_set_suspend(dev, 0); |
546 | console_unlock(); | | 550 | console_unlock(); |
547 | } | | 551 | } |
548 | | | 552 | |
549 | static int __i915_drm_thaw(struct drm_device *dev) | | 553 | static int __i915_drm_thaw(struct drm_device *dev) |
550 | { | | 554 | { |
551 | struct drm_i915_private *dev_priv = dev->dev_private; | | 555 | struct drm_i915_private *dev_priv = dev->dev_private; |
552 | int error = 0; | | 556 | int error = 0; |
553 | | | 557 | |
554 | i915_restore_state(dev); | | 558 | i915_restore_state(dev); |
555 | intel_opregion_setup(dev); | | 559 | intel_opregion_setup(dev); |
556 | | | 560 | |
557 | /* KMS EnterVT equivalent */ | | 561 | /* KMS EnterVT equivalent */ |
558 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | | 562 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
559 | intel_init_pch_refclk(dev); | | 563 | intel_init_pch_refclk(dev); |
560 | | | 564 | |
561 | mutex_lock(&dev->struct_mutex); | | 565 | mutex_lock(&dev->struct_mutex); |
562 | dev_priv->mm.suspended = 0; | | 566 | dev_priv->mm.suspended = 0; |
563 | | | 567 | |
564 | error = i915_gem_init_hw(dev); | | 568 | error = i915_gem_init_hw(dev); |
565 | mutex_unlock(&dev->struct_mutex); | | 569 | mutex_unlock(&dev->struct_mutex); |
566 | | | 570 | |
567 | intel_modeset_init_hw(dev); | | 571 | intel_modeset_init_hw(dev); |
568 | intel_modeset_setup_hw_state(dev, false); | | 572 | intel_modeset_setup_hw_state(dev, false); |
569 | drm_irq_install(dev); | | 573 | drm_irq_install(dev); |
570 | } | | 574 | } |
571 | | | 575 | |
572 | intel_opregion_init(dev); | | 576 | intel_opregion_init(dev); |
573 | | | 577 | |
574 | dev_priv->modeset_on_lid = 0; | | 578 | dev_priv->modeset_on_lid = 0; |
575 | | | 579 | |
576 | /* | | 580 | /* |
577 | * The console lock can be pretty contented on resume due | | 581 | * The console lock can be pretty contented on resume due |
578 | * to all the printk activity. Try to keep it out of the hot | | 582 | * to all the printk activity. Try to keep it out of the hot |
579 | * path of resume if possible. | | 583 | * path of resume if possible. |
580 | */ | | 584 | */ |
581 | if (console_trylock()) { | | 585 | if (console_trylock()) { |
582 | intel_fbdev_set_suspend(dev, 0); | | 586 | intel_fbdev_set_suspend(dev, 0); |
583 | console_unlock(); | | 587 | console_unlock(); |
584 | } else { | | 588 | } else { |
585 | schedule_work(&dev_priv->console_resume_work); | | 589 | schedule_work(&dev_priv->console_resume_work); |
586 | } | | 590 | } |
587 | | | 591 | |
588 | return error; | | 592 | return error; |
589 | } | | 593 | } |
590 | | | 594 | |
591 | static int i915_drm_thaw(struct drm_device *dev) | | 595 | static int i915_drm_thaw(struct drm_device *dev) |
592 | { | | 596 | { |
593 | int error = 0; | | 597 | int error = 0; |
594 | | | 598 | |
595 | intel_gt_reset(dev); | | 599 | intel_gt_reset(dev); |
596 | | | 600 | |
597 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | | 601 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
598 | mutex_lock(&dev->struct_mutex); | | 602 | mutex_lock(&dev->struct_mutex); |
599 | i915_gem_restore_gtt_mappings(dev); | | 603 | i915_gem_restore_gtt_mappings(dev); |
600 | mutex_unlock(&dev->struct_mutex); | | 604 | mutex_unlock(&dev->struct_mutex); |
601 | } | | 605 | } |
602 | | | 606 | |
603 | __i915_drm_thaw(dev); | | 607 | __i915_drm_thaw(dev); |
604 | | | 608 | |
605 | return error; | | 609 | return error; |
606 | } | | 610 | } |
607 | | | 611 | |
608 | int i915_resume(struct drm_device *dev) | | 612 | int i915_resume(struct drm_device *dev) |
609 | { | | 613 | { |
610 | struct drm_i915_private *dev_priv = dev->dev_private; | | 614 | struct drm_i915_private *dev_priv = dev->dev_private; |
611 | int ret; | | 615 | int ret; |
612 | | | 616 | |
613 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | | 617 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
614 | return 0; | | 618 | return 0; |
615 | | | 619 | |
616 | if (pci_enable_device(dev->pdev)) | | 620 | if (pci_enable_device(dev->pdev)) |
617 | return -EIO; | | 621 | return -EIO; |
618 | | | 622 | |
619 | pci_set_master(dev->pdev); | | 623 | pci_set_master(dev->pdev); |
620 | | | 624 | |
621 | intel_gt_reset(dev); | | 625 | intel_gt_reset(dev); |
622 | | | 626 | |
623 | /* | | 627 | /* |
624 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | | 628 | * Platforms with opregion should have sane BIOS, older ones (gen3 and |
625 | * earlier) need this since the BIOS might clear all our scratch PTEs. | | 629 | * earlier) need this since the BIOS might clear all our scratch PTEs. |
626 | */ | | 630 | */ |
627 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | | 631 | if (drm_core_check_feature(dev, DRIVER_MODESET) && |
628 | !dev_priv->opregion.header) { | | 632 | !dev_priv->opregion.header) { |
629 | mutex_lock(&dev->struct_mutex); | | 633 | mutex_lock(&dev->struct_mutex); |
630 | i915_gem_restore_gtt_mappings(dev); | | 634 | i915_gem_restore_gtt_mappings(dev); |
631 | mutex_unlock(&dev->struct_mutex); | | 635 | mutex_unlock(&dev->struct_mutex); |
632 | } | | 636 | } |
633 | | | 637 | |
634 | ret = __i915_drm_thaw(dev); | | 638 | ret = __i915_drm_thaw(dev); |
635 | if (ret) | | 639 | if (ret) |
636 | return ret; | | 640 | return ret; |
637 | | | 641 | |
638 | drm_kms_helper_poll_enable(dev); | | 642 | drm_kms_helper_poll_enable(dev); |
639 | return 0; | | 643 | return 0; |
640 | } | | 644 | } |
641 | | | 645 | |
642 | static int i8xx_do_reset(struct drm_device *dev) | | 646 | static int i8xx_do_reset(struct drm_device *dev) |
643 | { | | 647 | { |
644 | struct drm_i915_private *dev_priv = dev->dev_private; | | 648 | struct drm_i915_private *dev_priv = dev->dev_private; |
645 | | | 649 | |
646 | if (IS_I85X(dev)) | | 650 | if (IS_I85X(dev)) |
647 | return -ENODEV; | | 651 | return -ENODEV; |
648 | | | 652 | |
649 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | | 653 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
650 | POSTING_READ(D_STATE); | | 654 | POSTING_READ(D_STATE); |
651 | | | 655 | |
652 | if (IS_I830(dev) || IS_845G(dev)) { | | 656 | if (IS_I830(dev) || IS_845G(dev)) { |
653 | I915_WRITE(DEBUG_RESET_I830, | | 657 | I915_WRITE(DEBUG_RESET_I830, |
654 | DEBUG_RESET_DISPLAY | | | 658 | DEBUG_RESET_DISPLAY | |
655 | DEBUG_RESET_RENDER | | | 659 | DEBUG_RESET_RENDER | |
656 | DEBUG_RESET_FULL); | | 660 | DEBUG_RESET_FULL); |
657 | POSTING_READ(DEBUG_RESET_I830); | | 661 | POSTING_READ(DEBUG_RESET_I830); |
658 | msleep(1); | | 662 | msleep(1); |
659 | | | 663 | |
660 | I915_WRITE(DEBUG_RESET_I830, 0); | | 664 | I915_WRITE(DEBUG_RESET_I830, 0); |
661 | POSTING_READ(DEBUG_RESET_I830); | | 665 | POSTING_READ(DEBUG_RESET_I830); |
662 | } | | 666 | } |
663 | | | 667 | |
664 | msleep(1); | | 668 | msleep(1); |
665 | | | 669 | |
666 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | | 670 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
667 | POSTING_READ(D_STATE); | | 671 | POSTING_READ(D_STATE); |
668 | | | 672 | |
669 | return 0; | | 673 | return 0; |
670 | } | | 674 | } |
671 | | | 675 | |
672 | static int i965_reset_complete(struct drm_device *dev) | | 676 | static int i965_reset_complete(struct drm_device *dev) |
673 | { | | 677 | { |
674 | u8 gdrst; | | 678 | u8 gdrst; |
675 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | | 679 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
676 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | | 680 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
677 | } | | 681 | } |
678 | | | 682 | |
679 | static int i965_do_reset(struct drm_device *dev) | | 683 | static int i965_do_reset(struct drm_device *dev) |
680 | { | | 684 | { |
681 | int ret; | | 685 | int ret; |
682 | u8 gdrst; | | 686 | u8 gdrst; |
683 | | | 687 | |
684 | /* | | 688 | /* |
685 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | | 689 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
686 | * well as the reset bit (GR/bit 0). Setting the GR bit | | 690 | * well as the reset bit (GR/bit 0). Setting the GR bit |
687 | * triggers the reset; when done, the hardware will clear it. | | 691 | * triggers the reset; when done, the hardware will clear it. |
688 | */ | | 692 | */ |
689 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | | 693 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
690 | pci_write_config_byte(dev->pdev, I965_GDRST, | | 694 | pci_write_config_byte(dev->pdev, I965_GDRST, |
691 | gdrst | GRDOM_RENDER | | | 695 | gdrst | GRDOM_RENDER | |
692 | GRDOM_RESET_ENABLE); | | 696 | GRDOM_RESET_ENABLE); |
693 | ret = wait_for(i965_reset_complete(dev), 500); | | 697 | ret = wait_for(i965_reset_complete(dev), 500); |
694 | if (ret) | | 698 | if (ret) |
695 | return ret; | | 699 | return ret; |
696 | | | 700 | |
697 | /* We can't reset render&media without also resetting display ... */ | | 701 | /* We can't reset render&media without also resetting display ... */ |
698 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | | 702 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
699 | pci_write_config_byte(dev->pdev, I965_GDRST, | | 703 | pci_write_config_byte(dev->pdev, I965_GDRST, |
700 | gdrst | GRDOM_MEDIA | | | 704 | gdrst | GRDOM_MEDIA | |
701 | GRDOM_RESET_ENABLE); | | 705 | GRDOM_RESET_ENABLE); |
702 | | | 706 | |
703 | return wait_for(i965_reset_complete(dev), 500); | | 707 | return wait_for(i965_reset_complete(dev), 500); |
704 | } | | 708 | } |
705 | | | 709 | |
706 | static int ironlake_do_reset(struct drm_device *dev) | | 710 | static int ironlake_do_reset(struct drm_device *dev) |
707 | { | | 711 | { |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | | 712 | struct drm_i915_private *dev_priv = dev->dev_private; |
709 | u32 gdrst; | | 713 | u32 gdrst; |
710 | int ret; | | 714 | int ret; |
711 | | | 715 | |
712 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | | 716 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
713 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | | 717 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
714 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | | 718 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
715 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | | 719 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
716 | if (ret) | | 720 | if (ret) |
717 | return ret; | | 721 | return ret; |
718 | | | 722 | |
719 | /* We can't reset render&media without also resetting display ... */ | | 723 | /* We can't reset render&media without also resetting display ... */ |
720 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | | 724 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
721 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | | 725 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
722 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | | 726 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
723 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | | 727 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
724 | } | | 728 | } |
725 | | | 729 | |
726 | static int gen6_do_reset(struct drm_device *dev) | | 730 | static int gen6_do_reset(struct drm_device *dev) |
727 | { | | 731 | { |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
729 | int ret; | | 733 | int ret; |
730 | unsigned long irqflags; | | 734 | unsigned long irqflags; |
731 | | | 735 | |
732 | /* Hold gt_lock across reset to prevent any register access | | 736 | /* Hold gt_lock across reset to prevent any register access |
733 | * with forcewake not set correctly | | 737 | * with forcewake not set correctly |
734 | */ | | 738 | */ |
735 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); | | 739 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
736 | | | 740 | |
737 | /* Reset the chip */ | | 741 | /* Reset the chip */ |
738 | | | 742 | |
739 | /* GEN6_GDRST is not in the gt power well, no need to check | | 743 | /* GEN6_GDRST is not in the gt power well, no need to check |
740 | * for fifo space for the write or forcewake the chip for | | 744 | * for fifo space for the write or forcewake the chip for |
741 | * the read | | 745 | * the read |
742 | */ | | 746 | */ |
743 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | | 747 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); |
744 | | | 748 | |
745 | /* Spin waiting for the device to ack the reset request */ | | 749 | /* Spin waiting for the device to ack the reset request */ |
746 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | | 750 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
747 | | | 751 | |
748 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | | 752 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
749 | if (dev_priv->forcewake_count) | | 753 | if (dev_priv->forcewake_count) |
750 | dev_priv->gt.force_wake_get(dev_priv); | | 754 | dev_priv->gt.force_wake_get(dev_priv); |
751 | else | | 755 | else |
752 | dev_priv->gt.force_wake_put(dev_priv); | | 756 | dev_priv->gt.force_wake_put(dev_priv); |
753 | | | 757 | |
754 | /* Restore fifo count */ | | 758 | /* Restore fifo count */ |
755 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | | 759 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
756 | | | 760 | |
757 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); | | 761 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
758 | return ret; | | 762 | return ret; |
759 | } | | 763 | } |
760 | | | 764 | |
761 | int intel_gpu_reset(struct drm_device *dev) | | 765 | int intel_gpu_reset(struct drm_device *dev) |
762 | { | | 766 | { |
763 | struct drm_i915_private *dev_priv = dev->dev_private; | | 767 | struct drm_i915_private *dev_priv = dev->dev_private; |
764 | int ret = -ENODEV; | | 768 | int ret = -ENODEV; |
765 | | | 769 | |
766 | switch (INTEL_INFO(dev)->gen) { | | 770 | switch (INTEL_INFO(dev)->gen) { |
767 | case 7: | | 771 | case 7: |
768 | case 6: | | 772 | case 6: |
769 | ret = gen6_do_reset(dev); | | 773 | ret = gen6_do_reset(dev); |
770 | break; | | 774 | break; |
771 | case 5: | | 775 | case 5: |
772 | ret = ironlake_do_reset(dev); | | 776 | ret = ironlake_do_reset(dev); |
773 | break; | | 777 | break; |
774 | case 4: | | 778 | case 4: |
775 | ret = i965_do_reset(dev); | | 779 | ret = i965_do_reset(dev); |
776 | break; | | 780 | break; |
777 | case 2: | | 781 | case 2: |
778 | ret = i8xx_do_reset(dev); | | 782 | ret = i8xx_do_reset(dev); |
779 | break; | | 783 | break; |
780 | } | | 784 | } |
781 | | | 785 | |
782 | /* Also reset the gpu hangman. */ | | 786 | /* Also reset the gpu hangman. */ |
783 | if (dev_priv->stop_rings) { | | 787 | if (dev_priv->stop_rings) { |
784 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); | | 788 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); |
785 | dev_priv->stop_rings = 0; | | 789 | dev_priv->stop_rings = 0; |
786 | if (ret == -ENODEV) { | | 790 | if (ret == -ENODEV) { |
787 | DRM_ERROR("Reset not implemented, but ignoring " | | 791 | DRM_ERROR("Reset not implemented, but ignoring " |
788 | "error for simulated gpu hangs\n"); | | 792 | "error for simulated gpu hangs\n"); |
789 | ret = 0; | | 793 | ret = 0; |
790 | } | | 794 | } |
791 | } | | 795 | } |
792 | | | 796 | |
793 | return ret; | | 797 | return ret; |
794 | } | | 798 | } |
795 | | | 799 | |
796 | /** | | 800 | /** |
797 | * i915_reset - reset chip after a hang | | 801 | * i915_reset - reset chip after a hang |
798 | * @dev: drm device to reset | | 802 | * @dev: drm device to reset |
799 | * | | 803 | * |
800 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | | 804 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
801 | * reset or otherwise an error code. | | 805 | * reset or otherwise an error code. |
802 | * | | 806 | * |
803 | * Procedure is fairly simple: | | 807 | * Procedure is fairly simple: |
804 | * - reset the chip using the reset reg | | 808 | * - reset the chip using the reset reg |
805 | * - re-init context state | | 809 | * - re-init context state |
806 | * - re-init hardware status page | | 810 | * - re-init hardware status page |
807 | * - re-init ring buffer | | 811 | * - re-init ring buffer |
808 | * - re-init interrupt state | | 812 | * - re-init interrupt state |
809 | * - re-init display | | 813 | * - re-init display |
810 | */ | | 814 | */ |
811 | int i915_reset(struct drm_device *dev) | | 815 | int i915_reset(struct drm_device *dev) |
812 | { | | 816 | { |
813 | drm_i915_private_t *dev_priv = dev->dev_private; | | 817 | drm_i915_private_t *dev_priv = dev->dev_private; |
814 | int ret; | | 818 | int ret; |
815 | | | 819 | |
816 | if (!i915_try_reset) | | 820 | if (!i915_try_reset) |
817 | return 0; | | 821 | return 0; |
818 | | | 822 | |
819 | mutex_lock(&dev->struct_mutex); | | 823 | mutex_lock(&dev->struct_mutex); |
820 | | | 824 | |
821 | i915_gem_reset(dev); | | 825 | i915_gem_reset(dev); |
822 | | | 826 | |
823 | ret = -ENODEV; | | 827 | ret = -ENODEV; |
824 | if (get_seconds() - dev_priv->last_gpu_reset < 5) | | 828 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
825 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | | 829 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
826 | else | | 830 | else |
827 | ret = intel_gpu_reset(dev); | | 831 | ret = intel_gpu_reset(dev); |
828 | | | 832 | |
829 | dev_priv->last_gpu_reset = get_seconds(); | | 833 | dev_priv->last_gpu_reset = get_seconds(); |
830 | if (ret) { | | 834 | if (ret) { |
831 | DRM_ERROR("Failed to reset chip.\n"); | | 835 | DRM_ERROR("Failed to reset chip.\n"); |
832 | mutex_unlock(&dev->struct_mutex); | | 836 | mutex_unlock(&dev->struct_mutex); |
833 | return ret; | | 837 | return ret; |
834 | } | | 838 | } |
835 | | | 839 | |
836 | /* Ok, now get things going again... */ | | 840 | /* Ok, now get things going again... */ |
837 | | | 841 | |
838 | /* | | 842 | /* |
839 | * Everything depends on having the GTT running, so we need to start | | 843 | * Everything depends on having the GTT running, so we need to start |
840 | * there. Fortunately we don't need to do this unless we reset the | | 844 | * there. Fortunately we don't need to do this unless we reset the |
841 | * chip at a PCI level. | | 845 | * chip at a PCI level. |
842 | * | | 846 | * |
843 | * Next we need to restore the context, but we don't use those | | 847 | * Next we need to restore the context, but we don't use those |
844 | * yet either... | | 848 | * yet either... |
845 | * | | 849 | * |
846 | * Ring buffer needs to be re-initialized in the KMS case, or if X | | 850 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
847 | * was running at the time of the reset (i.e. we weren't VT | | 851 | * was running at the time of the reset (i.e. we weren't VT |
848 | * switched away). | | 852 | * switched away). |
849 | */ | | 853 | */ |
850 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | | 854 | if (drm_core_check_feature(dev, DRIVER_MODESET) || |
851 | !dev_priv->mm.suspended) { | | 855 | !dev_priv->mm.suspended) { |
852 | struct intel_ring_buffer *ring; | | 856 | struct intel_ring_buffer *ring; |
853 | int i; | | 857 | int i; |
854 | | | 858 | |
855 | dev_priv->mm.suspended = 0; | | 859 | dev_priv->mm.suspended = 0; |
856 | | | 860 | |
857 | i915_gem_init_swizzling(dev); | | 861 | i915_gem_init_swizzling(dev); |
858 | | | 862 | |
859 | for_each_ring(ring, dev_priv, i) | | 863 | for_each_ring(ring, dev_priv, i) |
860 | ring->init(ring); | | 864 | ring->init(ring); |
861 | | | 865 | |
862 | i915_gem_context_init(dev); | | 866 | i915_gem_context_init(dev); |
863 | i915_gem_init_ppgtt(dev); | | 867 | i915_gem_init_ppgtt(dev); |
864 | | | 868 | |
865 | /* | | 869 | /* |
866 | * It would make sense to re-init all the other hw state, at | | 870 | * It would make sense to re-init all the other hw state, at |
867 | * least the rps/rc6/emon init done within modeset_init_hw. For | | 871 | * least the rps/rc6/emon init done within modeset_init_hw. For |
868 | * some unknown reason, this blows up my ilk, so don't. | | 872 | * some unknown reason, this blows up my ilk, so don't. |
869 | */ | | 873 | */ |
870 | | | 874 | |
871 | mutex_unlock(&dev->struct_mutex); | | 875 | mutex_unlock(&dev->struct_mutex); |
872 | | | 876 | |
873 | drm_irq_uninstall(dev); | | 877 | drm_irq_uninstall(dev); |
874 | drm_irq_install(dev); | | 878 | drm_irq_install(dev); |
875 | } else { | | 879 | } else { |
876 | mutex_unlock(&dev->struct_mutex); | | 880 | mutex_unlock(&dev->struct_mutex); |
877 | } | | 881 | } |
878 | | | 882 | |
879 | return 0; | | 883 | return 0; |
880 | } | | 884 | } |
881 | | | 885 | |
882 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | | 886 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
883 | { | | 887 | { |
884 | struct intel_device_info *intel_info = | | 888 | struct intel_device_info *intel_info = |
885 | (struct intel_device_info *) ent->driver_data; | | 889 | (struct intel_device_info *) ent->driver_data; |
886 | | | 890 | |
887 | if (intel_info->is_valleyview) | | 891 | if (intel_info->is_valleyview) |
888 | if(!i915_preliminary_hw_support) { | | 892 | if(!i915_preliminary_hw_support) { |
889 | DRM_ERROR("Preliminary hardware support disabled\n"); | | 893 | DRM_ERROR("Preliminary hardware support disabled\n"); |
890 | return -ENODEV; | | 894 | return -ENODEV; |
891 | } | | 895 | } |
892 | | | 896 | |
893 | /* Only bind to function 0 of the device. Early generations | | 897 | /* Only bind to function 0 of the device. Early generations |
894 | * used function 1 as a placeholder for multi-head. This causes | | 898 | * used function 1 as a placeholder for multi-head. This causes |
895 | * us confusion instead, especially on the systems where both | | 899 | * us confusion instead, especially on the systems where both |
896 | * functions have the same PCI-ID! | | 900 | * functions have the same PCI-ID! |
897 | */ | | 901 | */ |
898 | if (PCI_FUNC(pdev->devfn)) | | 902 | if (PCI_FUNC(pdev->devfn)) |
899 | return -ENODEV; | | 903 | return -ENODEV; |
900 | | | 904 | |
901 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC | | 905 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
902 | * implementation for gen3 (and only gen3) that used legacy drm maps | | 906 | * implementation for gen3 (and only gen3) that used legacy drm maps |
903 | * (gasp!) to share buffers between X and the client. Hence we need to | | 907 | * (gasp!) to share buffers between X and the client. Hence we need to |
904 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | | 908 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ |
905 | if (intel_info->gen != 3) { | | 909 | if (intel_info->gen != 3) { |
906 | driver.driver_features &= | | 910 | driver.driver_features &= |
907 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | | 911 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); |
908 | } else if (!intel_agp_enabled) { | | 912 | } else if (!intel_agp_enabled) { |
909 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | | 913 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
910 | return -ENODEV; | | 914 | return -ENODEV; |
911 | } | | 915 | } |
912 | | | 916 | |
913 | return drm_get_pci_dev(pdev, ent, &driver); | | 917 | return drm_get_pci_dev(pdev, ent, &driver); |
914 | } | | 918 | } |
915 | | | 919 | |
916 | static void | | 920 | static void |
917 | i915_pci_remove(struct pci_dev *pdev) | | 921 | i915_pci_remove(struct pci_dev *pdev) |
918 | { | | 922 | { |
919 | struct drm_device *dev = pci_get_drvdata(pdev); | | 923 | struct drm_device *dev = pci_get_drvdata(pdev); |
920 | | | 924 | |
921 | drm_put_dev(dev); | | 925 | drm_put_dev(dev); |
922 | } | | 926 | } |
923 | | | 927 | |
924 | static int i915_pm_suspend(struct device *dev) | | 928 | static int i915_pm_suspend(struct device *dev) |
925 | { | | 929 | { |
926 | struct pci_dev *pdev = to_pci_dev(dev); | | 930 | struct pci_dev *pdev = to_pci_dev(dev); |
927 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | | 931 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
928 | int error; | | 932 | int error; |
929 | | | 933 | |
930 | if (!drm_dev || !drm_dev->dev_private) { | | 934 | if (!drm_dev || !drm_dev->dev_private) { |
931 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | | 935 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
932 | return -ENODEV; | | 936 | return -ENODEV; |
933 | } | | 937 | } |
934 | | | 938 | |
935 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | | 939 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
936 | return 0; | | 940 | return 0; |
937 | | | 941 | |
938 | error = i915_drm_freeze(drm_dev); | | 942 | error = i915_drm_freeze(drm_dev); |
939 | if (error) | | 943 | if (error) |
940 | return error; | | 944 | return error; |
941 | | | 945 | |
942 | pci_disable_device(pdev); | | 946 | pci_disable_device(pdev); |
943 | pci_set_power_state(pdev, PCI_D3hot); | | 947 | pci_set_power_state(pdev, PCI_D3hot); |
944 | | | 948 | |
945 | return 0; | | 949 | return 0; |
946 | } | | 950 | } |
947 | | | 951 | |
948 | static int i915_pm_resume(struct device *dev) | | 952 | static int i915_pm_resume(struct device *dev) |
949 | { | | 953 | { |
950 | struct pci_dev *pdev = to_pci_dev(dev); | | 954 | struct pci_dev *pdev = to_pci_dev(dev); |
951 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | | 955 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
952 | | | 956 | |
953 | return i915_resume(drm_dev); | | 957 | return i915_resume(drm_dev); |
954 | } | | 958 | } |
955 | | | 959 | |
956 | static int i915_pm_freeze(struct device *dev) | | 960 | static int i915_pm_freeze(struct device *dev) |
957 | { | | 961 | { |
958 | struct pci_dev *pdev = to_pci_dev(dev); | | 962 | struct pci_dev *pdev = to_pci_dev(dev); |
959 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | | 963 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
960 | | | 964 | |
961 | if (!drm_dev || !drm_dev->dev_private) { | | 965 | if (!drm_dev || !drm_dev->dev_private) { |
962 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | | 966 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
963 | return -ENODEV; | | 967 | return -ENODEV; |
964 | } | | 968 | } |
965 | | | 969 | |
966 | return i915_drm_freeze(drm_dev); | | 970 | return i915_drm_freeze(drm_dev); |
967 | } | | 971 | } |
968 | | | 972 | |
969 | static int i915_pm_thaw(struct device *dev) | | 973 | static int i915_pm_thaw(struct device *dev) |
970 | { | | 974 | { |
971 | struct pci_dev *pdev = to_pci_dev(dev); | | 975 | struct pci_dev *pdev = to_pci_dev(dev); |
972 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | | 976 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
973 | | | 977 | |
974 | return i915_drm_thaw(drm_dev); | | 978 | return i915_drm_thaw(drm_dev); |
975 | } | | 979 | } |
976 | | | 980 | |
977 | static int i915_pm_poweroff(struct device *dev) | | 981 | static int i915_pm_poweroff(struct device *dev) |
978 | { | | 982 | { |
979 | struct pci_dev *pdev = to_pci_dev(dev); | | 983 | struct pci_dev *pdev = to_pci_dev(dev); |
980 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | | 984 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
981 | | | 985 | |
982 | return i915_drm_freeze(drm_dev); | | 986 | return i915_drm_freeze(drm_dev); |
983 | } | | 987 | } |
984 | | | 988 | |
985 | static const struct dev_pm_ops i915_pm_ops = { | | 989 | static const struct dev_pm_ops i915_pm_ops = { |
986 | .suspend = i915_pm_suspend, | | 990 | .suspend = i915_pm_suspend, |
987 | .resume = i915_pm_resume, | | 991 | .resume = i915_pm_resume, |
988 | .freeze = i915_pm_freeze, | | 992 | .freeze = i915_pm_freeze, |
989 | .thaw = i915_pm_thaw, | | 993 | .thaw = i915_pm_thaw, |
990 | .poweroff = i915_pm_poweroff, | | 994 | .poweroff = i915_pm_poweroff, |
991 | .restore = i915_pm_resume, | | 995 | .restore = i915_pm_resume, |
992 | }; | | 996 | }; |
993 | | | 997 | |
994 | static const struct vm_operations_struct i915_gem_vm_ops = { | | 998 | static const struct vm_operations_struct i915_gem_vm_ops = { |
995 | .fault = i915_gem_fault, | | 999 | .fault = i915_gem_fault, |
996 | .open = drm_gem_vm_open, | | 1000 | .open = drm_gem_vm_open, |
997 | .close = drm_gem_vm_close, | | 1001 | .close = drm_gem_vm_close, |
998 | }; | | 1002 | }; |
999 | | | 1003 | |
1000 | static const struct file_operations i915_driver_fops = { | | 1004 | static const struct file_operations i915_driver_fops = { |
1001 | .owner = THIS_MODULE, | | 1005 | .owner = THIS_MODULE, |
1002 | .open = drm_open, | | 1006 | .open = drm_open, |
1003 | .release = drm_release, | | 1007 | .release = drm_release, |
1004 | .unlocked_ioctl = drm_ioctl, | | 1008 | .unlocked_ioctl = drm_ioctl, |
1005 | .mmap = drm_gem_mmap, | | 1009 | .mmap = drm_gem_mmap, |
1006 | .poll = drm_poll, | | 1010 | .poll = drm_poll, |
1007 | .fasync = drm_fasync, | | 1011 | .fasync = drm_fasync, |
1008 | .read = drm_read, | | 1012 | .read = drm_read, |
1009 | #ifdef CONFIG_COMPAT | | 1013 | #ifdef CONFIG_COMPAT |
1010 | .compat_ioctl = i915_compat_ioctl, | | 1014 | .compat_ioctl = i915_compat_ioctl, |
1011 | #endif | | 1015 | #endif |
1012 | .llseek = noop_llseek, | | 1016 | .llseek = noop_llseek, |
1013 | }; | | 1017 | }; |
1014 | | | 1018 | |
1015 | static struct drm_driver driver = { | | 1019 | static struct drm_driver driver = { |
1016 | /* Don't use MTRRs here; the Xserver or userspace app should | | 1020 | /* Don't use MTRRs here; the Xserver or userspace app should |
1017 | * deal with them for Intel hardware. | | 1021 | * deal with them for Intel hardware. |
1018 | */ | | 1022 | */ |
1019 | .driver_features = | | 1023 | .driver_features = |
1020 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | | 1024 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ |
1021 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, | | 1025 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
1022 | .load = i915_driver_load, | | 1026 | .load = i915_driver_load, |
1023 | .unload = i915_driver_unload, | | 1027 | .unload = i915_driver_unload, |
1024 | .open = i915_driver_open, | | 1028 | .open = i915_driver_open, |
1025 | .lastclose = i915_driver_lastclose, | | 1029 | .lastclose = i915_driver_lastclose, |
1026 | .preclose = i915_driver_preclose, | | 1030 | .preclose = i915_driver_preclose, |
1027 | .postclose = i915_driver_postclose, | | 1031 | .postclose = i915_driver_postclose, |
1028 | | | 1032 | |
1029 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | | 1033 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
1030 | .suspend = i915_suspend, | | 1034 | .suspend = i915_suspend, |
1031 | .resume = i915_resume, | | 1035 | .resume = i915_resume, |
1032 | | | 1036 | |
1033 | .device_is_agp = i915_driver_device_is_agp, | | 1037 | .device_is_agp = i915_driver_device_is_agp, |
1034 | .master_create = i915_master_create, | | 1038 | .master_create = i915_master_create, |
1035 | .master_destroy = i915_master_destroy, | | 1039 | .master_destroy = i915_master_destroy, |
1036 | #if defined(CONFIG_DEBUG_FS) | | 1040 | #if defined(CONFIG_DEBUG_FS) |
1037 | .debugfs_init = i915_debugfs_init, | | 1041 | .debugfs_init = i915_debugfs_init, |
1038 | .debugfs_cleanup = i915_debugfs_cleanup, | | 1042 | .debugfs_cleanup = i915_debugfs_cleanup, |
1039 | #endif | | 1043 | #endif |
1040 | .gem_init_object = i915_gem_init_object, | | 1044 | .gem_init_object = i915_gem_init_object, |
1041 | .gem_free_object = i915_gem_free_object, | | 1045 | .gem_free_object = i915_gem_free_object, |
1042 | .gem_vm_ops = &i915_gem_vm_ops, | | 1046 | .gem_vm_ops = &i915_gem_vm_ops, |
1043 | | | 1047 | |
1044 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | | 1048 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
1045 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | | 1049 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
1046 | .gem_prime_export = i915_gem_prime_export, | | 1050 | .gem_prime_export = i915_gem_prime_export, |
1047 | .gem_prime_import = i915_gem_prime_import, | | 1051 | .gem_prime_import = i915_gem_prime_import, |
1048 | | | 1052 | |
1049 | .dumb_create = i915_gem_dumb_create, | | 1053 | .dumb_create = i915_gem_dumb_create, |
1050 | .dumb_map_offset = i915_gem_mmap_gtt, | | 1054 | .dumb_map_offset = i915_gem_mmap_gtt, |
1051 | .dumb_destroy = i915_gem_dumb_destroy, | | 1055 | .dumb_destroy = i915_gem_dumb_destroy, |
1052 | .ioctls = i915_ioctls, | | 1056 | .ioctls = i915_ioctls, |
1053 | .fops = &i915_driver_fops, | | 1057 | .fops = &i915_driver_fops, |
1054 | .name = DRIVER_NAME, | | 1058 | .name = DRIVER_NAME, |
1055 | .desc = DRIVER_DESC, | | 1059 | .desc = DRIVER_DESC, |
1056 | .date = DRIVER_DATE, | | 1060 | .date = DRIVER_DATE, |
1057 | .major = DRIVER_MAJOR, | | 1061 | .major = DRIVER_MAJOR, |
1058 | .minor = DRIVER_MINOR, | | 1062 | .minor = DRIVER_MINOR, |
1059 | .patchlevel = DRIVER_PATCHLEVEL, | | 1063 | .patchlevel = DRIVER_PATCHLEVEL, |
1060 | }; | | 1064 | }; |
1061 | | | 1065 | |
1062 | static struct pci_driver i915_pci_driver = { | | 1066 | static struct pci_driver i915_pci_driver = { |
1063 | .name = DRIVER_NAME, | | 1067 | .name = DRIVER_NAME, |
1064 | .id_table = pciidlist, | | 1068 | .id_table = pciidlist, |
1065 | .probe = i915_pci_probe, | | 1069 | .probe = i915_pci_probe, |
1066 | .remove = i915_pci_remove, | | 1070 | .remove = i915_pci_remove, |
1067 | .driver.pm = &i915_pm_ops, | | 1071 | .driver.pm = &i915_pm_ops, |
1068 | }; | | 1072 | }; |
1069 | | | 1073 | |
1070 | static int __init i915_init(void) | | 1074 | static int __init i915_init(void) |
1071 | { | | 1075 | { |
1072 | driver.num_ioctls = i915_max_ioctl; | | 1076 | driver.num_ioctls = i915_max_ioctl; |
1073 | | | 1077 | |
1074 | /* | | 1078 | /* |
1075 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | | 1079 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless |
1076 | * explicitly disabled with the module pararmeter. | | 1080 | * explicitly disabled with the module pararmeter. |
1077 | * | | 1081 | * |
1078 | * Otherwise, just follow the parameter (defaulting to off). | | 1082 | * Otherwise, just follow the parameter (defaulting to off). |
1079 | * | | 1083 | * |
1080 | * Allow optional vga_text_mode_force boot option to override | | 1084 | * Allow optional vga_text_mode_force boot option to override |
1081 | * the default behavior. | | 1085 | * the default behavior. |
1082 | */ | | 1086 | */ |
1083 | #if defined(CONFIG_DRM_I915_KMS) | | 1087 | #if defined(CONFIG_DRM_I915_KMS) |
1084 | if (i915_modeset != 0) | | 1088 | if (i915_modeset != 0) |
1085 | driver.driver_features |= DRIVER_MODESET; | | 1089 | driver.driver_features |= DRIVER_MODESET; |
1086 | #endif | | 1090 | #endif |
1087 | if (i915_modeset == 1) | | 1091 | if (i915_modeset == 1) |
1088 | driver.driver_features |= DRIVER_MODESET; | | 1092 | driver.driver_features |= DRIVER_MODESET; |
1089 | | | 1093 | |
1090 | #ifdef CONFIG_VGA_CONSOLE | | 1094 | #ifdef CONFIG_VGA_CONSOLE |
1091 | if (vgacon_text_force() && i915_modeset == -1) | | 1095 | if (vgacon_text_force() && i915_modeset == -1) |
1092 | driver.driver_features &= ~DRIVER_MODESET; | | 1096 | driver.driver_features &= ~DRIVER_MODESET; |
1093 | #endif | | 1097 | #endif |
1094 | | | 1098 | |
1095 | if (!(driver.driver_features & DRIVER_MODESET)) | | 1099 | if (!(driver.driver_features & DRIVER_MODESET)) |
1096 | driver.get_vblank_timestamp = NULL; | | 1100 | driver.get_vblank_timestamp = NULL; |
1097 | | | 1101 | |
1098 | return drm_pci_init(&driver, &i915_pci_driver); | | 1102 | return drm_pci_init(&driver, &i915_pci_driver); |
1099 | } | | 1103 | } |
1100 | | | 1104 | |
1101 | static void __exit i915_exit(void) | | 1105 | static void __exit i915_exit(void) |
1102 | { | | 1106 | { |
1103 | drm_pci_exit(&driver, &i915_pci_driver); | | 1107 | drm_pci_exit(&driver, &i915_pci_driver); |
1104 | } | | 1108 | } |
1105 | | | 1109 | |
1106 | module_init(i915_init); | | 1110 | module_init(i915_init); |
1107 | module_exit(i915_exit); | | 1111 | module_exit(i915_exit); |
1108 | | | 1112 | |
1109 | MODULE_AUTHOR(DRIVER_AUTHOR); | | 1113 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1110 | MODULE_DESCRIPTION(DRIVER_DESC); | | 1114 | MODULE_DESCRIPTION(DRIVER_DESC); |
1111 | MODULE_LICENSE("GPL and additional rights"); | | 1115 | MODULE_LICENSE("GPL and additional rights"); |
1112 | | | 1116 | |
1113 | /* We give fast paths for the really cool registers */ | | 1117 | /* We give fast paths for the really cool registers */ |
1114 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | | 1118 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
1115 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ | | 1119 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
1116 | ((reg) < 0x40000) && \ | | 1120 | ((reg) < 0x40000) && \ |
1117 | ((reg) != FORCEWAKE)) | | 1121 | ((reg) != FORCEWAKE)) |
1118 | | | 1122 | |
1119 | static bool IS_DISPLAYREG(u32 reg) | | 1123 | static bool IS_DISPLAYREG(u32 reg) |
1120 | { | | 1124 | { |
1121 | /* | | 1125 | /* |
1122 | * This should make it easier to transition modules over to the | | 1126 | * This should make it easier to transition modules over to the |
1123 | * new register block scheme, since we can do it incrementally. | | 1127 | * new register block scheme, since we can do it incrementally. |
1124 | */ | | 1128 | */ |
1125 | if (reg >= VLV_DISPLAY_BASE) | | 1129 | if (reg >= VLV_DISPLAY_BASE) |
1126 | return false; | | 1130 | return false; |
1127 | | | 1131 | |
1128 | if (reg >= RENDER_RING_BASE && | | 1132 | if (reg >= RENDER_RING_BASE && |
1129 | reg < RENDER_RING_BASE + 0xff) | | 1133 | reg < RENDER_RING_BASE + 0xff) |
1130 | return false; | | 1134 | return false; |
1131 | if (reg >= GEN6_BSD_RING_BASE && | | 1135 | if (reg >= GEN6_BSD_RING_BASE && |
1132 | reg < GEN6_BSD_RING_BASE + 0xff) | | 1136 | reg < GEN6_BSD_RING_BASE + 0xff) |
1133 | return false; | | 1137 | return false; |
1134 | if (reg >= BLT_RING_BASE && | | 1138 | if (reg >= BLT_RING_BASE && |
1135 | reg < BLT_RING_BASE + 0xff) | | 1139 | reg < BLT_RING_BASE + 0xff) |
1136 | return false; | | 1140 | return false; |
1137 | | | 1141 | |
1138 | if (reg == PGTBL_ER) | | 1142 | if (reg == PGTBL_ER) |
1139 | return false; | | 1143 | return false; |
1140 | | | 1144 | |
1141 | if (reg >= IPEIR_I965 && | | 1145 | if (reg >= IPEIR_I965 && |
1142 | reg < HWSTAM) | | 1146 | reg < HWSTAM) |
1143 | return false; | | 1147 | return false; |
1144 | | | 1148 | |
1145 | if (reg == MI_MODE) | | 1149 | if (reg == MI_MODE) |
1146 | return false; | | 1150 | return false; |
1147 | | | 1151 | |
1148 | if (reg == GFX_MODE_GEN7) | | 1152 | if (reg == GFX_MODE_GEN7) |
1149 | return false; | | 1153 | return false; |
1150 | | | 1154 | |
1151 | if (reg == RENDER_HWS_PGA_GEN7 || | | 1155 | if (reg == RENDER_HWS_PGA_GEN7 || |
1152 | reg == BSD_HWS_PGA_GEN7 || | | 1156 | reg == BSD_HWS_PGA_GEN7 || |
1153 | reg == BLT_HWS_PGA_GEN7) | | 1157 | reg == BLT_HWS_PGA_GEN7) |
1154 | return false; | | 1158 | return false; |
1155 | | | 1159 | |
1156 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || | | 1160 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
1157 | reg == GEN6_BSD_RNCID) | | 1161 | reg == GEN6_BSD_RNCID) |
1158 | return false; | | 1162 | return false; |
1159 | | | 1163 | |
1160 | if (reg == GEN6_BLITTER_ECOSKPD) | | 1164 | if (reg == GEN6_BLITTER_ECOSKPD) |
1161 | return false; | | 1165 | return false; |
1162 | | | 1166 | |
1163 | if (reg >= 0x4000c && | | 1167 | if (reg >= 0x4000c && |
1164 | reg <= 0x4002c) | | 1168 | reg <= 0x4002c) |
1165 | return false; | | 1169 | return false; |
1166 | | | 1170 | |
1167 | if (reg >= 0x4f000 && | | 1171 | if (reg >= 0x4f000 && |
1168 | reg <= 0x4f08f) | | 1172 | reg <= 0x4f08f) |
1169 | return false; | | 1173 | return false; |
1170 | | | 1174 | |
1171 | if (reg >= 0x4f100 && | | 1175 | if (reg >= 0x4f100 && |
1172 | reg <= 0x4f11f) | | 1176 | reg <= 0x4f11f) |
1173 | return false; | | 1177 | return false; |
1174 | | | 1178 | |
1175 | if (reg >= VLV_MASTER_IER && | | 1179 | if (reg >= VLV_MASTER_IER && |
1176 | reg <= GEN6_PMIER) | | 1180 | reg <= GEN6_PMIER) |
1177 | return false; | | 1181 | return false; |
1178 | | | 1182 | |
1179 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && | | 1183 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
1180 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) | | 1184 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
1181 | return false; | | 1185 | return false; |
1182 | | | 1186 | |
1183 | if (reg >= VLV_IIR_RW && | | 1187 | if (reg >= VLV_IIR_RW && |
1184 | reg <= VLV_ISR) | | 1188 | reg <= VLV_ISR) |
1185 | return false; | | 1189 | return false; |
1186 | | | 1190 | |
1187 | if (reg == FORCEWAKE_VLV || | | 1191 | if (reg == FORCEWAKE_VLV || |
1188 | reg == FORCEWAKE_ACK_VLV) | | 1192 | reg == FORCEWAKE_ACK_VLV) |
1189 | return false; | | 1193 | return false; |
1190 | | | 1194 | |
1191 | if (reg == GEN6_GDRST) | | 1195 | if (reg == GEN6_GDRST) |
1192 | return false; | | 1196 | return false; |
1193 | | | 1197 | |
1194 | switch (reg) { | | 1198 | switch (reg) { |
1195 | case _3D_CHICKEN3: | | 1199 | case _3D_CHICKEN3: |
1196 | case IVB_CHICKEN3: | | 1200 | case IVB_CHICKEN3: |
1197 | case GEN7_COMMON_SLICE_CHICKEN1: | | 1201 | case GEN7_COMMON_SLICE_CHICKEN1: |
1198 | case GEN7_L3CNTLREG1: | | 1202 | case GEN7_L3CNTLREG1: |
1199 | case GEN7_L3_CHICKEN_MODE_REGISTER: | | 1203 | case GEN7_L3_CHICKEN_MODE_REGISTER: |
1200 | case GEN7_ROW_CHICKEN2: | | 1204 | case GEN7_ROW_CHICKEN2: |
1201 | case GEN7_L3SQCREG4: | | 1205 | case GEN7_L3SQCREG4: |
1202 | case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: | | 1206 | case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: |
1203 | case GEN7_HALF_SLICE_CHICKEN1: | | 1207 | case GEN7_HALF_SLICE_CHICKEN1: |
1204 | case GEN6_MBCTL: | | 1208 | case GEN6_MBCTL: |
1205 | case GEN6_UCGCTL2: | | 1209 | case GEN6_UCGCTL2: |
1206 | return false; | | 1210 | return false; |
1207 | default: | | 1211 | default: |
1208 | break; | | 1212 | break; |
1209 | } | | 1213 | } |
1210 | | | 1214 | |
1211 | return true; | | 1215 | return true; |
1212 | } | | 1216 | } |
1213 | | | 1217 | |
1214 | static void | | 1218 | static void |
1215 | ilk_dummy_write(struct drm_i915_private *dev_priv) | | 1219 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
1216 | { | | 1220 | { |
1217 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the | | 1221 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the |
1218 | * chip from rc6 before touching it for real. MI_MODE is masked, hence | | 1222 | * chip from rc6 before touching it for real. MI_MODE is masked, hence |
1219 | * harmless to write 0 into. */ | | 1223 | * harmless to write 0 into. */ |
1220 | I915_WRITE_NOTRACE(MI_MODE, 0); | | 1224 | I915_WRITE_NOTRACE(MI_MODE, 0); |
1221 | } | | 1225 | } |
1222 | | | 1226 | |
1223 | #ifdef __NetBSD__ | | 1227 | #ifdef __NetBSD__ |
1224 | #define __i915_read(x, y) \ | | 1228 | #define __i915_read(x, y) \ |
1225 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | | 1229 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1226 | u##x val = 0; \ | | 1230 | u##x val = 0; \ |
1227 | if (IS_GEN5(dev_priv->dev)) \ | | 1231 | if (IS_GEN5(dev_priv->dev)) \ |
1228 | ilk_dummy_write(dev_priv); \ | | 1232 | ilk_dummy_write(dev_priv); \ |
1229 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | | 1233 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1230 | unsigned long irqflags; \ | | 1234 | unsigned long irqflags; \ |
1231 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | | 1235 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
1232 | if (dev_priv->forcewake_count == 0) \ | | 1236 | if (dev_priv->forcewake_count == 0) \ |
1233 | dev_priv->gt.force_wake_get(dev_priv); \ | | 1237 | dev_priv->gt.force_wake_get(dev_priv); \ |
1234 | val = DRM_READ##x(dev_priv->regs_map, reg); \ | | 1238 | val = DRM_READ##x(dev_priv->regs_map, reg); \ |
1235 | if (dev_priv->forcewake_count == 0) \ | | 1239 | if (dev_priv->forcewake_count == 0) \ |
1236 | dev_priv->gt.force_wake_put(dev_priv); \ | | 1240 | dev_priv->gt.force_wake_put(dev_priv); \ |
1237 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | | 1241 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
1238 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ | | 1242 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1239 | val = DRM_READ##x(dev_priv->regs_map, reg + 0x180000); \ | | 1243 | val = DRM_READ##x(dev_priv->regs_map, reg + 0x180000); \ |
1240 | } else { \ | | 1244 | } else { \ |
1241 | val = DRM_READ##x(dev_priv->regs_map, reg); \ | | 1245 | val = DRM_READ##x(dev_priv->regs_map, reg); \ |
1242 | } \ | | 1246 | } \ |
1243 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | | 1247 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1244 | return val; \ | | 1248 | return val; \ |
1245 | } | | 1249 | } |
1246 | #else | | 1250 | #else |
1247 | #define __i915_read(x, y) \ | | 1251 | #define __i915_read(x, y) \ |
1248 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | | 1252 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1249 | u##x val = 0; \ | | 1253 | u##x val = 0; \ |
1250 | if (IS_GEN5(dev_priv->dev)) \ | | 1254 | if (IS_GEN5(dev_priv->dev)) \ |
1251 | ilk_dummy_write(dev_priv); \ | | 1255 | ilk_dummy_write(dev_priv); \ |
1252 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | | 1256 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1253 | unsigned long irqflags; \ | | 1257 | unsigned long irqflags; \ |
1254 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | | 1258 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
1255 | if (dev_priv->forcewake_count == 0) \ | | 1259 | if (dev_priv->forcewake_count == 0) \ |
1256 | dev_priv->gt.force_wake_get(dev_priv); \ | | 1260 | dev_priv->gt.force_wake_get(dev_priv); \ |
1257 | val = read##y(dev_priv->regs + reg); \ | | 1261 | val = read##y(dev_priv->regs + reg); \ |
1258 | if (dev_priv->forcewake_count == 0) \ | | 1262 | if (dev_priv->forcewake_count == 0) \ |
1259 | dev_priv->gt.force_wake_put(dev_priv); \ | | 1263 | dev_priv->gt.force_wake_put(dev_priv); \ |
1260 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | | 1264 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
1261 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ | | 1265 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1262 | val = read##y(dev_priv->regs + reg + 0x180000); \ | | 1266 | val = read##y(dev_priv->regs + reg + 0x180000); \ |
1263 | } else { \ | | 1267 | } else { \ |
1264 | val = read##y(dev_priv->regs + reg); \ | | 1268 | val = read##y(dev_priv->regs + reg); \ |
1265 | } \ | | 1269 | } \ |
1266 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | | 1270 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1267 | return val; \ | | 1271 | return val; \ |
1268 | } | | 1272 | } |
1269 | #endif | | 1273 | #endif |
1270 | | | 1274 | |
1271 | __i915_read(8, b) | | 1275 | __i915_read(8, b) |
1272 | __i915_read(16, w) | | 1276 | __i915_read(16, w) |
1273 | __i915_read(32, l) | | 1277 | __i915_read(32, l) |
1274 | __i915_read(64, q) | | 1278 | __i915_read(64, q) |
1275 | #undef __i915_read | | 1279 | #undef __i915_read |
1276 | | | 1280 | |
1277 | #ifdef __NetBSD__ | | 1281 | #ifdef __NetBSD__ |
1278 | #define __i915_write(x, y) \ | | 1282 | #define __i915_write(x, y) \ |
1279 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | | 1283 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1280 | u32 __fifo_ret = 0; \ | | 1284 | u32 __fifo_ret = 0; \ |
1281 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | | 1285 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1282 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | | 1286 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1283 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | | 1287 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1284 | } \ | | 1288 | } \ |
1285 | if (IS_GEN5(dev_priv->dev)) \ | | 1289 | if (IS_GEN5(dev_priv->dev)) \ |
1286 | ilk_dummy_write(dev_priv); \ | | 1290 | ilk_dummy_write(dev_priv); \ |
1287 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ | | 1291 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1288 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ | | 1292 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ |
1289 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ | | 1293 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ |
1290 | } \ | | 1294 | } \ |
1291 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ | | 1295 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1292 | DRM_WRITE##x(dev_priv->regs_map, reg + 0x180000, val); \ | | 1296 | DRM_WRITE##x(dev_priv->regs_map, reg + 0x180000, val); \ |
1293 | } else { \ | | 1297 | } else { \ |
1294 | DRM_WRITE##x(dev_priv->regs_map, reg, val); \ | | 1298 | DRM_WRITE##x(dev_priv->regs_map, reg, val); \ |
1295 | } \ | | 1299 | } \ |
1296 | if (unlikely(__fifo_ret)) { \ | | 1300 | if (unlikely(__fifo_ret)) { \ |
1297 | gen6_gt_check_fifodbg(dev_priv); \ | | 1301 | gen6_gt_check_fifodbg(dev_priv); \ |
1298 | } \ | | 1302 | } \ |
1299 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ | | 1303 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1300 | DRM_ERROR("Unclaimed write to %x\n", reg); \ | | 1304 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
1301 | DRM_WRITE32(dev_priv->regs_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ | | 1305 | DRM_WRITE32(dev_priv->regs_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ |
1302 | } \ | | 1306 | } \ |
1303 | } | | 1307 | } |
1304 | #else | | 1308 | #else |
1305 | #define __i915_write(x, y) \ | | 1309 | #define __i915_write(x, y) \ |
1306 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | | 1310 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1307 | u32 __fifo_ret = 0; \ | | 1311 | u32 __fifo_ret = 0; \ |
1308 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | | 1312 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1309 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | | 1313 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1310 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | | 1314 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1311 | } \ | | 1315 | } \ |
1312 | if (IS_GEN5(dev_priv->dev)) \ | | 1316 | if (IS_GEN5(dev_priv->dev)) \ |
1313 | ilk_dummy_write(dev_priv); \ | | 1317 | ilk_dummy_write(dev_priv); \ |
1314 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ | | 1318 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1315 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ | | 1319 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ |
1316 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ | | 1320 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ |
1317 | } \ | | 1321 | } \ |
1318 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ | | 1322 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1319 | write##y(val, dev_priv->regs + reg + 0x180000); \ | | 1323 | write##y(val, dev_priv->regs + reg + 0x180000); \ |
1320 | } else { \ | | 1324 | } else { \ |
1321 | write##y(val, dev_priv->regs + reg); \ | | 1325 | write##y(val, dev_priv->regs + reg); \ |
1322 | } \ | | 1326 | } \ |
1323 | if (unlikely(__fifo_ret)) { \ | | 1327 | if (unlikely(__fifo_ret)) { \ |
1324 | gen6_gt_check_fifodbg(dev_priv); \ | | 1328 | gen6_gt_check_fifodbg(dev_priv); \ |
1325 | } \ | | 1329 | } \ |
1326 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ | | 1330 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1327 | DRM_ERROR("Unclaimed write to %x\n", reg); \ | | 1331 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
1328 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ | | 1332 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
1329 | } \ | | 1333 | } \ |
1330 | } | | 1334 | } |
1331 | #endif | | 1335 | #endif |
1332 | | | 1336 | |
1333 | __i915_write(8, b) | | 1337 | __i915_write(8, b) |
1334 | __i915_write(16, w) | | 1338 | __i915_write(16, w) |
1335 | __i915_write(32, l) | | 1339 | __i915_write(32, l) |
1336 | __i915_write(64, q) | | 1340 | __i915_write(64, q) |
1337 | #undef __i915_write | | 1341 | #undef __i915_write |
1338 | | | 1342 | |
1339 | static const struct register_whitelist { | | 1343 | static const struct register_whitelist { |
1340 | uint64_t offset; | | 1344 | uint64_t offset; |
1341 | uint32_t size; | | 1345 | uint32_t size; |
1342 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | | 1346 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1343 | } whitelist[] = { | | 1347 | } whitelist[] = { |
1344 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | | 1348 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
1345 | }; | | 1349 | }; |
1346 | | | 1350 | |
1347 | int i915_reg_read_ioctl(struct drm_device *dev, | | 1351 | int i915_reg_read_ioctl(struct drm_device *dev, |
1348 | void *data, struct drm_file *file) | | 1352 | void *data, struct drm_file *file) |
1349 | { | | 1353 | { |
1350 | struct drm_i915_private *dev_priv = dev->dev_private; | | 1354 | struct drm_i915_private *dev_priv = dev->dev_private; |
1351 | struct drm_i915_reg_read *reg = data; | | 1355 | struct drm_i915_reg_read *reg = data; |
1352 | struct register_whitelist const *entry = whitelist; | | 1356 | struct register_whitelist const *entry = whitelist; |
1353 | int i; | | 1357 | int i; |
1354 | | | 1358 | |
1355 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | | 1359 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
1356 | if (entry->offset == reg->offset && | | 1360 | if (entry->offset == reg->offset && |
1357 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | | 1361 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
1358 | break; | | 1362 | break; |
1359 | } | | 1363 | } |
1360 | | | 1364 | |
1361 | if (i == ARRAY_SIZE(whitelist)) | | 1365 | if (i == ARRAY_SIZE(whitelist)) |
1362 | return -EINVAL; | | 1366 | return -EINVAL; |
1363 | | | 1367 | |
1364 | switch (entry->size) { | | 1368 | switch (entry->size) { |
1365 | case 8: | | 1369 | case 8: |
1366 | reg->val = I915_READ64(reg->offset); | | 1370 | reg->val = I915_READ64(reg->offset); |
1367 | break; | | 1371 | break; |
1368 | case 4: | | 1372 | case 4: |
1369 | reg->val = I915_READ(reg->offset); | | 1373 | reg->val = I915_READ(reg->offset); |
1370 | break; | | 1374 | break; |
1371 | case 2: | | 1375 | case 2: |
1372 | reg->val = I915_READ16(reg->offset); | | 1376 | reg->val = I915_READ16(reg->offset); |
1373 | break; | | 1377 | break; |
1374 | case 1: | | 1378 | case 1: |
1375 | reg->val = I915_READ8(reg->offset); | | 1379 | reg->val = I915_READ8(reg->offset); |
1376 | break; | | 1380 | break; |
1377 | default: | | 1381 | default: |
1378 | WARN_ON(1); | | 1382 | WARN_ON(1); |
1379 | return -EINVAL; | | 1383 | return -EINVAL; |
1380 | } | | 1384 | } |
1381 | | | 1385 | |
1382 | return 0; | | 1386 | return 0; |
1383 | } | | 1387 | } |