 @@ -1,1502 +1,1506 @@
 /*
  * Copyright © 2006-2007 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
+ *
  * Authors:
  *	Eric Anholt <eric@anholt.net>
  */
 #include <linux/dmi.h>
 #include <linux/module.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/vgaarb.h>
 #include <drm/drm_edid.h>
 #include <drm/drmP.h>
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <drm/drm_dp_helper.h>
 #include <drm/drm_crtc_helper.h>
 #include <linux/dma_remapping.h>
 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 static void intel_increase_pllclock(struct drm_crtc *crtc);
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 typedef struct {
 	/* given values */
 	int n;
 	int m1, m2;
 	int p1, p2;
 	/* derived values */
 	int	dot;
 	int	vco;
 	int	m;
 	int	p;
 } intel_clock_t;
 typedef struct {
 	int	min, max;
 } intel_range_t;
 typedef struct {
 	int	dot_limit;
 	int	p2_slow, p2_fast;
 } intel_p2_t;
 #define INTEL_P2_NUM		      2
 typedef struct intel_limit intel_limit_t;
 struct intel_limit {
 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 	intel_p2_t	    p2;
 	bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
 			int, int, intel_clock_t *, intel_clock_t *);
 };
 /* FDI */
 #define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */
 int
 intel_pch_rawclk(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	WARN_ON(!HAS_PCH_SPLIT(dev));
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+}
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *match_clock,
 		    intel_clock_t *best_clock);
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *match_clock,
 			intel_clock_t *best_clock);
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 		      int target, int refclk, intel_clock_t *match_clock,
 		      intel_clock_t *best_clock);
 static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *match_clock,
 			   intel_clock_t *best_clock);
 static bool
 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *match_clock,
 			intel_clock_t *best_clock);
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
+{
 	if (IS_GEN5(dev)) {
 		struct drm_i915_private *dev_priv = dev->dev_private;
 		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 	} else
 		return 27;
+}
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
 	.n = { .min = 3, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 2, .max = 33 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 4, .p2_fast = 2 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
 	.n = { .min = 3, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 1, .max = 6 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 14, .p2_fast = 7 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i9xx_sdvo = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 10, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i9xx_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 10, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 7, .max = 98 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 7 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_sdvo = {
 	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 1, .max = 3},
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 10,
 		.p2_fast = 10
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_hdmi = {
 	.dot = { .min = 22000, .max = 400000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 16, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8},
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 	.dot = { .min = 20000, .max = 115000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 14, .p2_fast = 14
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 	.dot = { .min = 80000, .max = 224000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 7, .p2_fast = 7
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_display_port = {
 	.dot = { .min = 161670, .max = 227000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 97, .max = 108 },
 	.m1 = { .min = 0x10, .max = 0x12 },
 	.m2 = { .min = 0x05, .max = 0x06 },
 	.p = { .min = 10, .max = 20 },
 	.p1 = { .min = 1, .max = 2},
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 10, .p2_fast = 10 },
 	.find_pll = intel_find_pll_g4x_dp,
 };
 static const intel_limit_t intel_limits_pineview_sdvo = {
 	.dot = { .min = 20000, .max = 400000},
 	.vco = { .min = 1700000, .max = 3500000 },
 	/* Pineview's Ncounter is a ring counter */
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	/* Pineview only has one combined m divider, which we treat as m2. */
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_pineview_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1700000, .max = 3500000 },
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 7, .max = 112 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_find_best_PLL,
 };
 /* Ironlake / Sandybridge
+ *
  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  * the range value for them is (actual_value - 2).
  */
 static const intel_limit_t intel_limits_ironlake_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 5 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 118 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 56 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 /* LVDS 100mhz refclk limits. */
 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_display_port = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000},
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 81, .max = 90 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 10, .max = 20 },
 	.p1 = { .min = 1, .max = 2},
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 10, .p2_fast = 10 },
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 static const intel_limit_t intel_limits_vlv_dac = {
 	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
 	.m = { .min = 22, .max = 450 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 2, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
 };
 static const intel_limit_t intel_limits_vlv_hdmi = {
 	.dot = { .min = 20000, .max = 165000 },
 	.vco = { .min = 4000000, .max = 5994000},
 	.n = { .min = 1, .max = 7 },
 	.m = { .min = 60, .max = 300 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 2, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
 };
 static const intel_limit_t intel_limits_vlv_dp = {
 	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
 	.m = { .min = 22, .max = 450 },
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 2, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
 };
 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
+{
 	unsigned long flags;
 	u32 val = 0;
 	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 		DRM_ERROR("DPIO idle wait timed out\n");
 		goto out_unlock;
+	}
 	I915_WRITE(DPIO_REG, reg);
 	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 		   DPIO_BYTE);
 	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 		DRM_ERROR("DPIO read wait timed out\n");
 		goto out_unlock;
+	}
 	val = I915_READ(DPIO_DATA);
 out_unlock:
 	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 	return val;
+}
 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 			     u32 val)
+{
 	unsigned long flags;
 	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 		DRM_ERROR("DPIO idle wait timed out\n");
 		goto out_unlock;
+	}
 	I915_WRITE(DPIO_DATA, val);
 	I915_WRITE(DPIO_REG, reg);
 	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 		   DPIO_BYTE);
 	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 		DRM_ERROR("DPIO write wait timed out\n");
 out_unlock:
        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+}
 static void vlv_init_dpio(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* Reset the DPIO config */
 	I915_WRITE(DPIO_CTL, 0);
 	POSTING_READ(DPIO_CTL);
 	I915_WRITE(DPIO_CTL, 1);
 	POSTING_READ(DPIO_CTL);
+}
 #ifndef __NetBSD__		/* XXX dmi hack */
 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
+{
 	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 	return 1;
+}
 static const struct dmi_system_id intel_dual_link_lvds[] = {
+	{
 		.callback = intel_dual_link_lvds_callback,
 		.ident = "Apple MacBook Pro (Core i5/i7 Series)",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 		},
 	},
 	{ }	/* terminating entry */
 };
 #endif
 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 			      unsigned int reg)
+{
 	unsigned int val;
 	/* use the module option value if specified */
 	if (i915_lvds_channel_mode > 0)
 		return i915_lvds_channel_mode == 2;
 #ifndef __NetBSD__		/* XXX dmi hack */
 	if (dmi_check_system(intel_dual_link_lvds))
 		return true;
 #endif
 	if (dev_priv->lvds_val)
 		val = dev_priv->lvds_val;
 	else {
 		/* BIOS should set the proper LVDS register value at boot, but
 		 * in reality, it doesn't set the value when the lid is closed;
 		 * we need to check "the value to be set" in VBT when LVDS
 		 * register is uninitialized.
 		 */
 		val = I915_READ(reg);
 		if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 			val = dev_priv->bios_lvds_val;
 		dev_priv->lvds_val = val;
+	}
 	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
+}
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 						int refclk)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const intel_limit_t *limit;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 			/* LVDS dual channel */
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_dual_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_dual_lvds;
 		} else {
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_single_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_single_lvds;
+		}
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 		   intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 		limit = &intel_limits_ironlake_display_port;
 	else
 		limit = &intel_limits_ironlake_dac;
 	return limit;
+}
 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const intel_limit_t *limit;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		if (is_dual_link_lvds(dev_priv, LVDS))
 			/* LVDS with dual channel */
 			limit = &intel_limits_g4x_dual_channel_lvds;
 		else
 			/* LVDS with dual channel */
 			limit = &intel_limits_g4x_single_channel_lvds;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 		limit = &intel_limits_g4x_hdmi;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 		limit = &intel_limits_g4x_sdvo;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 		limit = &intel_limits_g4x_display_port;
 	} else /* The option is for other outputs */
 		limit = &intel_limits_i9xx_sdvo;
 	return limit;
+}
 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
+{
 	struct drm_device *dev = crtc->dev;
 	const intel_limit_t *limit;
 	if (HAS_PCH_SPLIT(dev))
 		limit = intel_ironlake_limit(crtc, refclk);
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc);
 	} else if (IS_PINEVIEW(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
 	} else if (IS_VALLEYVIEW(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 			limit = &intel_limits_vlv_dac;
 		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 			limit = &intel_limits_vlv_hdmi;
 		else
 			limit = &intel_limits_vlv_dp;
 	} else if (!IS_GEN2(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i9xx_lvds;
 		else
 			limit = &intel_limits_i9xx_sdvo;
 	} else {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i8xx_lvds;
 		else
 			limit = &intel_limits_i8xx_dvo;
+	}
 	return limit;
+}
 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 static void pineview_clock(int refclk, intel_clock_t *clock)
+{
 	clock->m = clock->m2 + 2;
 	clock->p = clock->p1 * clock->p2;
 	clock->vco = refclk * clock->m / clock->n;
 	clock->dot = clock->vco / clock->p;
+}
 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
+{
 	if (IS_PINEVIEW(dev)) {
 		pineview_clock(refclk, clock);
 		return;
+	}
 	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 	clock->p = clock->p1 * clock->p2;
 	clock->vco = refclk * clock->m / (clock->n + 2);
 	clock->dot = clock->vco / clock->p;
+}
 /**
  * Returns whether any output on the specified pipe is of the specified type
  */
 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
+{
 	struct drm_device *dev = crtc->dev;
 	struct intel_encoder *encoder;
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->type == type)
 			return true;
 	return false;
+}
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
  * the given connectors.
  */
 static bool intel_PLL_is_valid(struct drm_device *dev,
 			       const intel_limit_t *limit,
 			       const intel_clock_t *clock)
+{
 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 		INTELPllInvalid("p1 out of range\n");
 	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 		INTELPllInvalid("p out of range\n");
 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 		INTELPllInvalid("m2 out of range\n");
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 		INTELPllInvalid("m1 <= m2\n");
 	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 		INTELPllInvalid("m out of range\n");
 	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 		INTELPllInvalid("n out of range\n");
 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 		INTELPllInvalid("vco out of range\n");
 	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 	 * connector, etc., rather than just a single range.
 	 */
 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 		INTELPllInvalid("dot out of range\n");
 	return true;
+}
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *match_clock,
 		    intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	intel_clock_t clock;
 	int err = target;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    (I915_READ(LVDS)) != 0) {
 		/*
 		 * For LVDS, if the panel is on, just rely on its current
 		 * settings for dual-channel.  We haven't figured out how to
 		 * reliably set up different single/dual channel state, if we
 		 * even can.
 		 */
 		if (is_dual_link_lvds(dev_priv, LVDS))
 			clock.p2 = limit->p2.p2_fast;
 		else
 			clock.p2 = limit->p2.p2_slow;
 	} else {
 		if (target < limit->p2.dot_limit)
 			clock.p2 = limit->p2.p2_slow;
 		else
 			clock.p2 = limit->p2.p2_fast;
+	}
 	memset(best_clock, 0, sizeof(*best_clock));
 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 	     clock.m1++) {
 		for (clock.m2 = limit->m2.min;
 		     clock.m2 <= limit->m2.max; clock.m2++) {
 			/* m1 is always 0 in Pineview */
 			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 				break;
 			for (clock.n = limit->n.min;
 			     clock.n <= limit->n.max; clock.n++) {
 				for (clock.p1 = limit->p1.min;
 					clock.p1 <= limit->p1.max; clock.p1++) {
 					int this_err;
 					intel_clock(dev, refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					if (match_clock &&
 					    clock.p != match_clock->p)
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err) {
 						*best_clock = clock;
 						err = this_err;
+					}
+				}
+			}
+		}
+	}
 	return (err != target);
+}
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *match_clock,
 			intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	intel_clock_t clock;
 	int max_n;
 	bool found;
 	/* approximately equals target * 0.00585 */
 	int err_most = (target >> 8) + (target >> 9);
 	found = false;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		int lvds_reg;
 		if (HAS_PCH_SPLIT(dev))
 			lvds_reg = PCH_LVDS;
 		else
 			lvds_reg = LVDS;
 		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP)
 			clock.p2 = limit->p2.p2_fast;
 		else
 			clock.p2 = limit->p2.p2_slow;
 	} else {
 		if (target < limit->p2.dot_limit)
 			clock.p2 = limit->p2.p2_slow;
 		else
 			clock.p2 = limit->p2.p2_fast;
+	}
 	memset(best_clock, 0, sizeof(*best_clock));
 	max_n = limit->n.max;
 	/* based on hardware requirement, prefer smaller n to precision */
 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 		/* based on hardware requirement, prefere larger m1,m2 */
 		for (clock.m1 = limit->m1.max;
 		     clock.m1 >= limit->m1.min; clock.m1--) {
 			for (clock.m2 = limit->m2.max;
 			     clock.m2 >= limit->m2.min; clock.m2--) {
 				for (clock.p1 = limit->p1.max;
 				     clock.p1 >= limit->p1.min; clock.p1--) {
 					int this_err;
 					intel_clock(dev, refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					if (match_clock &&
 					    clock.p != match_clock->p)
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err_most) {
 						*best_clock = clock;
 						err_most = this_err;
 						max_n = clock.n;
 						found = true;
+					}
+				}
+			}
+		}
+	}
 	return found;
+}
 static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *match_clock,
 			   intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc->dev;
 	intel_clock_t clock;
 	if (target < 200000) {
 		clock.n = 1;
 		clock.p1 = 2;
 		clock.p2 = 10;
 		clock.m1 = 12;
 		clock.m2 = 9;
 	} else {
 		clock.n = 2;
 		clock.p1 = 1;
 		clock.p2 = 10;
 		clock.m1 = 14;
 		clock.m2 = 8;
+	}
 	intel_clock(dev, refclk, &clock);
 	memcpy(best_clock, &clock, sizeof(intel_clock_t));
 	return true;
+}
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 		      int target, int refclk, intel_clock_t *match_clock,
 		      intel_clock_t *best_clock)
+{
 	intel_clock_t clock;
 	if (target < 200000) {
 		clock.p1 = 2;
 		clock.p2 = 10;
 		clock.n = 2;
 		clock.m1 = 23;
 		clock.m2 = 8;
 	} else {
 		clock.p1 = 1;
 		clock.p2 = 10;
 		clock.n = 1;
 		clock.m1 = 14;
 		clock.m2 = 2;
+	}
 	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 	clock.p = (clock.p1 * clock.p2);
 	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 	clock.vco = 0;
 	memcpy(best_clock, &clock, sizeof(intel_clock_t));
 	return true;
+}
 static bool
 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *match_clock,
 			intel_clock_t *best_clock)
+{
 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 	u32 m, n, fastclk;
 	u32 updrate, minupdate, fracbits, p;
 	unsigned long bestppm, ppm, absppm;
 	int dotclk, flag;
 	flag = 0;
 	dotclk = target * 1000;
 	bestppm = 1000000;
 	ppm = absppm = 0;
 	fastclk = dotclk / (2*100);
 	updrate = 0;
 	minupdate = 19200;
 	fracbits = 1;
 	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 	bestm1 = bestm2 = bestp1 = bestp2 = 0;
 	/* based on hardware requirement, prefer smaller n to precision */
 	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 		updrate = refclk / n;
 		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 				if (p2 > 10)
 					p2 = p2 - 1;
 				p = p1 * p2;
 				/* based on hardware requirement, prefer bigger m1,m2 values */
 				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 					m2 = (((2*(fastclk * p * n / m1 )) +
 					       refclk) / (2*refclk));
 					m = m1 * m2;
 					vco = updrate * m;
 					if (vco >= limit->vco.min && vco < limit->vco.max) {
 						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 						absppm = (ppm > 0) ? ppm : (-ppm);
 						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 							bestppm = 0;
 							flag = 1;
+						}
 						if (absppm < bestppm - 10) {
 							bestppm = absppm;
 							flag = 1;
+						}
 						if (flag) {
 							bestn = n;
 							bestm1 = m1;
 							bestm2 = m2;
 							bestp1 = p1;
 							bestp2 = p2;
 							flag = 0;
+						}
+					}
+				}
+			}
+		}
+	}
 	best_clock->n = bestn;
 	best_clock->m1 = bestm1;
 	best_clock->m2 = bestm2;
 	best_clock->p1 = bestp1;
 	best_clock->p2 = bestp2;
 	return true;
+}
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 					     enum pipe pipe)
+{
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	return intel_crtc->cpu_transcoder;
+}
 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 frame, frame_reg = PIPEFRAME(pipe);
 	frame = I915_READ(frame_reg);
 	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 		DRM_DEBUG_KMS("vblank wait timed out\n");
+}
 /**
  * intel_wait_for_vblank - wait for vblank on a given pipe
  * @dev: drm device
  * @pipe: pipe to wait for
+ *
  * Wait for vblank to occur on a given pipe.  Needed for various bits of
  * mode setting code.
  */
 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipestat_reg = PIPESTAT(pipe);
 	if (INTEL_INFO(dev)->gen >= 5) {
 		ironlake_wait_for_vblank(dev, pipe);
 		return;
+	}
 	/* Clear existing vblank status. Note this will clear any other
 	 * sticky status fields as well.
+	 *
 	 * This races with i915_driver_irq_handler() with the result
 	 * that either function could miss a vblank event.  Here it is not
 	 * fatal, as we will either wait upon the next vblank interrupt or
 	 * timeout.  Generally speaking intel_wait_for_vblank() is only
 	 * called during modeset at which time the GPU should be idle and
 	 * should *not* be performing page flips and thus not waiting on
 	 * vblanks...
 	 * Currently, the result of us stealing a vblank from the irq
 	 * handler is that a single frame will be skipped during swapbuffers.
 	 */
 	I915_WRITE(pipestat_reg,
 		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 	/* Wait for vblank interrupt bit to set */
 	if (wait_for(I915_READ(pipestat_reg) &
 		     PIPE_VBLANK_INTERRUPT_STATUS,
 ))
 		DRM_DEBUG_KMS("vblank wait timed out\n");
+}
 /*
  * intel_wait_for_pipe_off - wait for pipe to turn off
  * @dev: drm device
  * @pipe: pipe to wait for
+ *
  * After disabling a pipe, we can't wait for vblank in the usual way,
  * spinning on the vblank interrupt status bit, since we won't actually
  * see an interrupt when the pipe is disabled.
+ *
  * On Gen4 and above:
  *   wait for the pipe register state bit to turn off
+ *
  * Otherwise:
  *   wait for the display line value to settle (it usually
  *   ends up stopping at the start of the next frame).
+ *
  */
 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		int reg = PIPECONF(cpu_transcoder);
 		/* Wait for the Pipe State to go off */
 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 ))
 			WARN(1, "pipe_off wait timed out\n");
 	} else {
 		u32 last_line, line_mask;
 		int reg = PIPEDSL(pipe);
 		unsigned long timeout = jiffies + msecs_to_jiffies(100);
 		if (IS_GEN2(dev))
 			line_mask = DSL_LINEMASK_GEN2;
 		else
 			line_mask = DSL_LINEMASK_GEN3;
 		/* Wait for the display line to settle */
 		do {
 			last_line = I915_READ(reg) & line_mask;
 			mdelay(5);
 		} while (((I915_READ(reg) & line_mask) != last_line) &&
 			 time_after(timeout, jiffies));
 		if (time_after(jiffies, timeout))
 			WARN(1, "pipe_off wait timed out\n");
+	}
+}
 static const char *state_string(bool enabled)
+{
 	return enabled ? "on" : "off";
+}
 /* Only for pre-ILK configs */
 static void assert_pll(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, bool state)
+{
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
+}
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 /* For ILK+ */
 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 			   struct intel_pch_pll *pll,
 			   struct intel_crtc *crtc,
 			   bool state)
+{
 	u32 val;
 	bool cur_state;
 	if (HAS_PCH_LPT(dev_priv->dev)) {
 		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 		return;
+	}
 	if (WARN (!pll,
 		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
 		return;
 	val = I915_READ(pll->pll_reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
 	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 	     pll->pll_reg, state_string(state), state_string(cur_state), val);
 	/* Make sure the selected PLL is correctly attached to the transcoder */
 	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 		u32 pch_dpll;
 		pch_dpll = I915_READ(PCH_DPLL_SEL);
 		cur_state = pll->pll_reg == _PCH_DPLL_B;
 		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 			  "PLL[%d] not attached to this transcoder %d: %08x\n",
 			  cur_state, crtc->pipe, pch_dpll)) {
 			cur_state = !!(val >> (4*crtc->pipe + 3));
 			WARN(cur_state != state,
 			     "PLL[%d] not %s on this transcoder %d: %08x\n",
 			     pll->pll_reg == _PCH_DPLL_B,
 			     state_string(state),
 			     crtc->pipe,
 			     val);
+		}
+	}
+}
 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
+{
 	int reg;
 	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	if (IS_HASWELL(dev_priv->dev)) {
 		/* On Haswell, DDI is used instead of FDI_TX_CTL */
 		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 		val = I915_READ(reg);
 		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
 		reg = FDI_TX_CTL(pipe);
 		val = I915_READ(reg);
 		cur_state = !!(val & FDI_TX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
+}
 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
+{
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & FDI_RX_ENABLE);
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
+}
 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	/* ILK FDI PLL is always enabled */
 	if (dev_priv->info->gen == 5)
 		return;
 	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
 	if (IS_HASWELL(dev_priv->dev))
 		return;
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
+}
 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
+}
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 				  enum pipe pipe)
+{
 	int pp_reg, lvds_reg;
 	u32 val;
 	enum pipe panel_pipe = PIPE_A;
 	bool locked = true;
 	if (HAS_PCH_SPLIT(dev_priv->dev)) {
 		pp_reg = PCH_PP_CONTROL;
 		lvds_reg = PCH_LVDS;
 	} else {
 		pp_reg = PP_CONTROL;
 		lvds_reg = LVDS;
+	}
 	val = I915_READ(pp_reg);
 	if (!(val & PANEL_POWER_ON) ||
 	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 		locked = false;
 	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 		panel_pipe = PIPE_B;
 	WARN(panel_pipe == pipe && locked,
 	     "panel assertion failure, pipe %c regs locked\n",
 	     pipe_name(pipe));
+}
 void assert_pipe(struct drm_i915_private *dev_priv,
 		 enum pipe pipe, bool state)
+{
 	int reg;
 	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	/* if we need the pipe A quirk it must be always on */
 	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 		state = true;
 	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	cur_state = !!(val & PIPECONF_ENABLE);
 	WARN(cur_state != state,
 	     "pipe %c assertion failure (expected %s, current %s)\n",
 	     pipe_name(pipe), state_string(state), state_string(cur_state));
+}
 static void assert_plane(struct drm_i915_private *dev_priv,
 			 enum plane plane, bool state)
+{
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = DSPCNTR(plane);
 	val = I915_READ(reg);
 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	WARN(cur_state != state,
 	     "plane %c assertion failure (expected %s, current %s)\n",
 	     plane_name(plane), state_string(state), state_string(cur_state));
+}
 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe)
+{
 	int reg, i;
 	u32 val;
 	int cur_pipe;
 	/* Planes are fixed to pipes on ILK+ */
 	if (HAS_PCH_SPLIT(dev_priv->dev)) {
 		reg = DSPCNTR(pipe);
 		val = I915_READ(reg);
 		WARN((val & DISPLAY_PLANE_ENABLE),
 		     "plane %c assertion failure, should be disabled but not\n",
 		     plane_name(pipe));
 		return;
+	}
 	/* Need to check both planes against the pipe */
 	for (i = 0; i < 2; i++) {
 		reg = DSPCNTR(i);
 		val = I915_READ(reg);
 		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 			DISPPLANE_SEL_PIPE_SHIFT;
 		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(i), pipe_name(pipe));
+	}
+}
 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
+{
 	u32 val;
 	bool enabled;
 	if (HAS_PCH_LPT(dev_priv->dev)) {
 		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
 		return;
+	}
 	val = I915_READ(PCH_DREF_CONTROL);
 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 			    DREF_SUPERSPREAD_SOURCE_MASK));
 	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
+}
 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 				       enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	bool enabled;
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	enabled = !!(val & TRANS_ENABLE);
 	WARN(enabled,
 	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
 	     pipe_name(pipe));
+}
 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 			    enum pipe pipe, u32 port_sel, u32 val)
+{
 	if ((val & DP_PORT_EN) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 			return false;
 	} else {
 		if ((val & DP_PIPE_MASK) != (pipe << 30))
 			return false;
+	}
 	return true;
+}
 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
+{
 	if ((val & PORT_ENABLE) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
 			return false;
+	}
 	return true;
+}
 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
+{
 	if ((val & LVDS_PORT_EN) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
 			return false;
+	}
 	return true;
+}
 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
+{
 	if ((val & ADPA_DAC_ENABLE) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
 			return false;
+	}
 	return true;
+}
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe, int reg, u32 port_sel)
+{
 	u32 val = I915_READ(reg);
 	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
 	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 	     reg, pipe_name(pipe));
 	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
 	     && (val & DP_PIPEB_SELECT),
 	     "IBX PCH dp port still using transcoder B\n");
+}
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 				     enum pipe pipe, int reg)
+{
 	u32 val = I915_READ(reg);
 	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
 	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
 	     reg, pipe_name(pipe));
 	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
 	     && (val & SDVO_PIPE_B_SELECT),
 	     "IBX PCH hdmi port still using transcoder B\n");
+}
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 	reg = PCH_ADPA;
 	val = I915_READ(reg);
 	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
 	     "PCH VGA enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 	reg = PCH_LVDS;
 	val = I915_READ(reg);
 	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
 	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
+}
 /**
  * intel_enable_pll - enable a PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
+ *
  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
  * make sure the PLL reg is writable first though, since the panel write
  * protect mechanism may be enabled.
+ *
  * Note!  This is for pre-ILK only.
+ *
  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
  */
 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	/* No really, not for ILK+ */
 	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
 		assert_panel_unlocked(dev_priv, pipe);
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	val |= DPLL_VCO_ENABLE;
 	/* We do this three times for luck */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
+}
 /**
  * intel_disable_pll - disable a PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to disable
+ *
  * Disable the PLL for @pipe, making sure the pipe is off first.
+ *
  * Note!  This is for pre-ILK only.
  */
 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
 	int reg;
 	u32 val;
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
 	/* Make sure the pipe isn't still relying on us */
 	assert_pipe_disabled(dev_priv, pipe);
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	val &= ~DPLL_VCO_ENABLE;
 @@ -7801,1718 +7805,1722 @@ intel_modeset_update_state(struct drm_de
+}
 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
 	list_for_each_entry((intel_crtc), \
 			    &(dev)->mode_config.crtc_list, \
 			    base.head) \
 		if (mask & (1 <<(intel_crtc)->pipe)) \
 void
 intel_modeset_check_state(struct drm_device *dev)
+{
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
 		/* This also checks the encoder/connector hw state with the
 		 * ->get_hw_state callbacks. */
 		intel_connector_check_state(connector);
 		WARN(&connector->new_encoder->base != connector->base.encoder,
 		     "connector's staged encoder doesn't match current encoder\n");
+	}
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		bool enabled = false;
 		bool active = false;
 		enum pipe pipe, tracked_pipe;
 		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
 			      encoder->base.base.id,
 			      drm_get_encoder_name(&encoder->base));
 		WARN(&encoder->new_crtc->base != encoder->base.crtc,
 		     "encoder's stage crtc doesn't match current crtc\n");
 		WARN(encoder->connectors_active && !encoder->base.crtc,
 		     "encoder's active_connectors set, but no crtc\n");
 		list_for_each_entry(connector, &dev->mode_config.connector_list,
 				    base.head) {
 			if (connector->base.encoder != &encoder->base)
 				continue;
 			enabled = true;
 			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
 				active = true;
+		}
 		WARN(!!encoder->base.crtc != enabled,
 		     "encoder's enabled state mismatch "
 		     "(expected %i, found %i)\n",
 		     !!encoder->base.crtc, enabled);
 		WARN(active && !encoder->base.crtc,
 		     "active encoder with no crtc\n");
 		WARN(encoder->connectors_active != active,
 		     "encoder's computed active state doesn't match tracked active state "
 		     "(expected %i, found %i)\n", active, encoder->connectors_active);
 		active = encoder->get_hw_state(encoder, &pipe);
 		WARN(active != encoder->connectors_active,
 		     "encoder's hw state doesn't match sw tracking "
 		     "(expected %i, found %i)\n",
 		     encoder->connectors_active, active);
 		if (!encoder->base.crtc)
 			continue;
 		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
 		WARN(active && pipe != tracked_pipe,
 		     "active encoder's pipe doesn't match"
 		     "(expected %i, found %i)\n",
 		     tracked_pipe, pipe);
+	}
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
 			    base.head) {
 		bool enabled = false;
 		bool active = false;
 		DRM_DEBUG_KMS("[CRTC:%d]\n",
 			      crtc->base.base.id);
 		WARN(crtc->active && !crtc->base.enabled,
 		     "active crtc, but not enabled in sw tracking\n");
 		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 				    base.head) {
 			if (encoder->base.crtc != &crtc->base)
 				continue;
 			enabled = true;
 			if (encoder->connectors_active)
 				active = true;
+		}
 		WARN(active != crtc->active,
 		     "crtc's computed active state doesn't match tracked active state "
 		     "(expected %i, found %i)\n", active, crtc->active);
 		WARN(enabled != crtc->base.enabled,
 		     "crtc's computed enabled state doesn't match tracked enabled state "
 		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);
 		assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
+	}
+}
 bool intel_set_mode(struct drm_crtc *crtc,
 		    struct drm_display_mode *mode,
 		    int x, int y, struct drm_framebuffer *fb)
+{
 	struct drm_device *dev = crtc->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
 	struct intel_crtc *intel_crtc;
 	unsigned disable_pipes, prepare_pipes, modeset_pipes;
 	bool ret = true;
 	intel_modeset_affected_pipes(crtc, &modeset_pipes,
 				     &prepare_pipes, &disable_pipes);
 	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
 		      modeset_pipes, prepare_pipes, disable_pipes);
 	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
 		intel_crtc_disable(&intel_crtc->base);
 	saved_hwmode = crtc->hwmode;
 	saved_mode = crtc->mode;
 	/* Hack: Because we don't (yet) support global modeset on multiple
 	 * crtcs, we don't keep track of the new mode for more than one crtc.
 	 * Hence simply check whether any bit is set in modeset_pipes in all the
 	 * pieces of code that are not yet converted to deal with mutliple crtcs
 	 * changing their mode at the same time. */
 	adjusted_mode = NULL;
 	if (modeset_pipes) {
 		adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
 		if (IS_ERR(adjusted_mode)) {
 			return false;
+		}
+	}
 	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
 		if (intel_crtc->base.enabled)
 			dev_priv->display.crtc_disable(&intel_crtc->base);
+	}
 	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
 	 * to set it here already despite that we pass it down the callchain.
 	 */
 	if (modeset_pipes)
 		crtc->mode = *mode;
 	/* Only after disabling all output pipelines that will be changed can we
 	 * update the the output configuration. */
 	intel_modeset_update_state(dev, prepare_pipes);
 	if (dev_priv->display.modeset_global_resources)
 		dev_priv->display.modeset_global_resources(dev);
 	/* Set up the DPLL and any encoders state that needs to adjust or depend
 	 * on the DPLL.
 	 */
 	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
 		ret = !intel_crtc_mode_set(&intel_crtc->base,
 					   mode, adjusted_mode,
 					   x, y, fb);
 		if (!ret)
 		    goto done;
+	}
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
 		dev_priv->display.crtc_enable(&intel_crtc->base);
 	if (modeset_pipes) {
 		/* Store real post-adjustment hardware mode. */
 		crtc->hwmode = *adjusted_mode;
 		/* Calculate and store various constants which
 		 * are later needed by vblank and swap-completion
 		 * timestamping. They are derived from true hwmode.
 		 */
 		drm_calc_timestamping_constants(crtc);
+	}
 	/* FIXME: add subpixel order */
 done:
 	drm_mode_destroy(dev, adjusted_mode);
 	if (!ret && crtc->enabled) {
 		crtc->hwmode = saved_hwmode;
 		crtc->mode = saved_mode;
 	} else {
 		intel_modeset_check_state(dev);
+	}
 	return ret;
+}
 #undef for_each_intel_crtc_masked
 static void intel_set_config_free(struct intel_set_config *config)
+{
 	if (!config)
 		return;
 	kfree(config->save_connector_encoders);
 	kfree(config->save_encoder_crtcs);
 	kfree(config);
+}
 static int intel_set_config_save_state(struct drm_device *dev,
 				       struct intel_set_config *config)
+{
 	struct drm_encoder *encoder;
 	struct drm_connector *connector;
 	int count;
 	config->save_encoder_crtcs =
 		kcalloc(dev->mode_config.num_encoder,
 			sizeof(struct drm_crtc *), GFP_KERNEL);
 	if (!config->save_encoder_crtcs)
 		return -ENOMEM;
 	config->save_connector_encoders =
 		kcalloc(dev->mode_config.num_connector,
 			sizeof(struct drm_encoder *), GFP_KERNEL);
 	if (!config->save_connector_encoders)
 		return -ENOMEM;
 	/* Copy data. Note that driver private data is not affected.
 	 * Should anything bad happen only the expected state is
 	 * restored, not the drivers personal bookkeeping.
 	 */
 	count = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		config->save_encoder_crtcs[count++] = encoder->crtc;
+	}
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		config->save_connector_encoders[count++] = connector->encoder;
+	}
 	return 0;
+}
 static void intel_set_config_restore_state(struct drm_device *dev,
 					   struct intel_set_config *config)
+{
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	int count;
 	count = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 		encoder->new_crtc =
 			to_intel_crtc(config->save_encoder_crtcs[count++]);
+	}
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
 		connector->new_encoder =
 			to_intel_encoder(config->save_connector_encoders[count++]);
+	}
+}
 static void
 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
 				      struct intel_set_config *config)
+{
 	/* We should be able to check here if the fb has the same properties
 	 * and then just flip_or_move it */
 	if (set->crtc->fb != set->fb) {
 		/* If we have no fb then treat it as a full mode set */
 		if (set->crtc->fb == NULL) {
 			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
 			config->mode_changed = true;
 		} else if (set->fb == NULL) {
 			config->mode_changed = true;
 		} else if (set->fb->depth != set->crtc->fb->depth) {
 			config->mode_changed = true;
 		} else if (set->fb->bits_per_pixel !=
 			   set->crtc->fb->bits_per_pixel) {
 			config->mode_changed = true;
 		} else
 			config->fb_changed = true;
+	}
 	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
 		config->fb_changed = true;
 	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
 		DRM_DEBUG_KMS("modes are different, full mode set\n");
 		drm_mode_debug_printmodeline(&set->crtc->mode);
 		drm_mode_debug_printmodeline(set->mode);
 		config->mode_changed = true;
+	}
+}
 static int
 intel_modeset_stage_output_state(struct drm_device *dev,
 				 struct drm_mode_set *set,
 				 struct intel_set_config *config)
+{
 	struct drm_crtc *new_crtc;
 	struct intel_connector *connector;
 	struct intel_encoder *encoder;
 	int count, ro;
 	/* The upper layers ensure that we either disabl a crtc or have a list
 	 * of connectors. For paranoia, double-check this. */
 	WARN_ON(!set->fb && (set->num_connectors != 0));
 	WARN_ON(set->fb && (set->num_connectors == 0));
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
 		/* Otherwise traverse passed in connector list and get encoders
 		 * for them. */
 		for (ro = 0; ro < set->num_connectors; ro++) {
 			if (set->connectors[ro] == &connector->base) {
 				connector->new_encoder = connector->encoder;
 				break;
+			}
+		}
 		/* If we disable the crtc, disable all its connectors. Also, if
 		 * the connector is on the changing crtc but not on the new
 		 * connector list, disable it. */
 		if ((!set->fb || ro == set->num_connectors) &&
 		    connector->base.encoder &&
 		    connector->base.encoder->crtc == set->crtc) {
 			connector->new_encoder = NULL;
 			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
 				connector->base.base.id,
 				drm_get_connector_name(&connector->base));
+		}
 		if (&connector->new_encoder->base != connector->base.encoder) {
 			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
 			config->mode_changed = true;
+		}
+	}
 	/* connector->new_encoder is now updated for all connectors. */
 	/* Update crtc of enabled connectors. */
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
 		if (!connector->new_encoder)
 			continue;
 		new_crtc = connector->new_encoder->base.crtc;
 		for (ro = 0; ro < set->num_connectors; ro++) {
 			if (set->connectors[ro] == &connector->base)
 				new_crtc = set->crtc;
+		}
 		/* Make sure the new CRTC will work with the encoder */
 		if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
 					   new_crtc)) {
 			return -EINVAL;
+		}
 		connector->encoder->new_crtc = to_intel_crtc(new_crtc);
 		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
 			connector->base.base.id,
 			drm_get_connector_name(&connector->base),
 			new_crtc->base.id);
+	}
 	/* Check for any encoders that needs to be disabled. */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		list_for_each_entry(connector,
 				    &dev->mode_config.connector_list,
 				    base.head) {
 			if (connector->new_encoder == encoder) {
 				WARN_ON(!connector->new_encoder->new_crtc);
 				goto next_encoder;
+			}
+		}
 		encoder->new_crtc = NULL;
 next_encoder:
 		/* Only now check for crtc changes so we don't miss encoders
 		 * that will be disabled. */
 		if (&encoder->new_crtc->base != encoder->base.crtc) {
 			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
 			config->mode_changed = true;
+		}
+	}
 	/* Now we've also updated encoder->new_crtc for all encoders. */
 	return 0;
+}
 static int intel_crtc_set_config(struct drm_mode_set *set)
+{
 	struct drm_device *dev;
 	struct drm_mode_set save_set;
 	struct intel_set_config *config;
 	int ret;
 	BUG_ON(!set);
 	BUG_ON(!set->crtc);
 	BUG_ON(!set->crtc->helper_private);
 	if (!set->mode)
 		set->fb = NULL;
 	/* The fb helper likes to play gross jokes with ->mode_set_config.
 	 * Unfortunately the crtc helper doesn't do much at all for this case,
 	 * so we have to cope with this madness until the fb helper is fixed up. */
 	if (set->fb && set->num_connectors == 0)
 		return 0;
 	if (set->fb) {
 		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
 				set->crtc->base.id, set->fb->base.id,
 				(int)set->num_connectors, set->x, set->y);
 	} else {
 		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
+	}
 	dev = set->crtc->dev;
 	ret = -ENOMEM;
 	config = kzalloc(sizeof(*config), GFP_KERNEL);
 	if (!config)
 		goto out_config;
 	ret = intel_set_config_save_state(dev, config);
 	if (ret)
 		goto out_config;
 	save_set.crtc = set->crtc;
 	save_set.mode = &set->crtc->mode;
 	save_set.x = set->crtc->x;
 	save_set.y = set->crtc->y;
 	save_set.fb = set->crtc->fb;
 	/* Compute whether we need a full modeset, only an fb base update or no
 	 * change at all. In the future we might also check whether only the
 	 * mode changed, e.g. for LVDS where we only change the panel fitter in
 	 * such cases. */
 	intel_set_config_compute_mode_changes(set, config);
 	ret = intel_modeset_stage_output_state(dev, set, config);
 	if (ret)
 		goto fail;
 	if (config->mode_changed) {
 		if (set->mode) {
 			DRM_DEBUG_KMS("attempting to set mode from"
 					" userspace\n");
 			drm_mode_debug_printmodeline(set->mode);
+		}
 		if (!intel_set_mode(set->crtc, set->mode,
 				    set->x, set->y, set->fb)) {
 			DRM_ERROR("failed to set mode on [CRTC:%d]\n",
 				  set->crtc->base.id);
 			ret = -EINVAL;
 			goto fail;
+		}
 	} else if (config->fb_changed) {
 		ret = intel_pipe_set_base(set->crtc,
 					  set->x, set->y, set->fb);
+	}
 	intel_set_config_free(config);
 	return 0;
 fail:
 	intel_set_config_restore_state(dev, config);
 	/* Try to restore the config */
 	if (config->mode_changed &&
 	    !intel_set_mode(save_set.crtc, save_set.mode,
 			    save_set.x, save_set.y, save_set.fb))
 		DRM_ERROR("failed to restore config after modeset failure\n");
 out_config:
 	intel_set_config_free(config);
 	return ret;
+}
 static const struct drm_crtc_funcs intel_crtc_funcs = {
 	.cursor_set = intel_crtc_cursor_set,
 	.cursor_move = intel_crtc_cursor_move,
 	.gamma_set = intel_crtc_gamma_set,
 	.set_config = intel_crtc_set_config,
 	.destroy = intel_crtc_destroy,
 	.page_flip = intel_crtc_page_flip,
 };
 static void intel_cpu_pll_init(struct drm_device *dev)
+{
 	if (IS_HASWELL(dev))
 		intel_ddi_pll_init(dev);
+}
 static void intel_pch_pll_init(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 	if (dev_priv->num_pch_pll == 0) {
 		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
 		return;
+	}
 	for (i = 0; i < dev_priv->num_pch_pll; i++) {
 		dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
 		dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
 		dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
+	}
+}
 static void intel_crtc_init(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc;
 	int i;
 	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 	if (intel_crtc == NULL)
 		return;
 	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
 	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
 	for (i = 0; i < 256; i++) {
 		intel_crtc->lut_r[i] = i;
 		intel_crtc->lut_g[i] = i;
 		intel_crtc->lut_b[i] = i;
+	}
 	/* Swap pipes & planes for FBC on pre-965 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
 	intel_crtc->cpu_transcoder = pipe;
 	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
+	}
 	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
 	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
 	intel_crtc->bpp = 24; /* default for pre-Ironlake */
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
+}
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file)
+{
 	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
 	struct drm_mode_object *drmmode_obj;
 	struct intel_crtc *crtc;
 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
 		return -ENODEV;
 	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
 			DRM_MODE_OBJECT_CRTC);
 	if (!drmmode_obj) {
 		DRM_ERROR("no such CRTC id\n");
 		return -EINVAL;
+	}
 	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
 	pipe_from_crtc_id->pipe = crtc->pipe;
 	return 0;
+}
 static int intel_encoder_clones(struct intel_encoder *encoder)
+{
 	struct drm_device *dev = encoder->base.dev;
 	struct intel_encoder *source_encoder;
 	int index_mask = 0;
 	int entry = 0;
 	list_for_each_entry(source_encoder,
 			    &dev->mode_config.encoder_list, base.head) {
 		if (encoder == source_encoder)
 			index_mask |= (1 << entry);
 		/* Intel hw has only one MUX where enocoders could be cloned. */
 		if (encoder->cloneable && source_encoder->cloneable)
 			index_mask |= (1 << entry);
 		entry++;
+	}
 	return index_mask;
+}
 static bool has_edp_a(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!IS_MOBILE(dev))
 		return false;
 	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
 		return false;
 	if (IS_GEN5(dev) &&
 	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
 		return false;
 	return true;
+}
 static void intel_setup_outputs(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *encoder;
 	bool dpd_is_edp = false;
 	bool has_lvds;
 	has_lvds = intel_lvds_init(dev);
 	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
 		/* disable the panel fitter on everything but LVDS */
 		I915_WRITE(PFIT_CONTROL, 0);
+	}
 	if (!(IS_HASWELL(dev) &&
 	      (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
 		intel_crt_init(dev);
 	if (IS_HASWELL(dev)) {
 		int found;
 		/* Haswell uses DDI functions to detect digital outputs */
 		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
 		/* DDI A only supports eDP */
 		if (found)
 			intel_ddi_init(dev, PORT_A);
 		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
 		 * register */
 		found = I915_READ(SFUSE_STRAP);
 		if (found & SFUSE_STRAP_DDIB_DETECTED)
 			intel_ddi_init(dev, PORT_B);
 		if (found & SFUSE_STRAP_DDIC_DETECTED)
 			intel_ddi_init(dev, PORT_C);
 		if (found & SFUSE_STRAP_DDID_DETECTED)
 			intel_ddi_init(dev, PORT_D);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		int found;
 		dpd_is_edp = intel_dpd_is_edp(dev);
 		if (has_edp_a(dev))
 			intel_dp_init(dev, DP_A, PORT_A);
 		if (I915_READ(HDMIB) & PORT_DETECTED) {
 			/* PCH SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev, PCH_SDVOB, true);
 			if (!found)
 				intel_hdmi_init(dev, HDMIB, PORT_B);
 			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
 				intel_dp_init(dev, PCH_DP_B, PORT_B);
+		}
 		if (I915_READ(HDMIC) & PORT_DETECTED)
 			intel_hdmi_init(dev, HDMIC, PORT_C);
 		if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
 			intel_hdmi_init(dev, HDMID, PORT_D);
 		if (I915_READ(PCH_DP_C) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_C, PORT_C);
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
 	} else if (IS_VALLEYVIEW(dev)) {
 		int found;
 		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
 		if (I915_READ(DP_C) & DP_DETECTED)
 			intel_dp_init(dev, DP_C, PORT_C);
 		if (I915_READ(SDVOB) & PORT_DETECTED) {
 			/* SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev, SDVOB, true);
 			if (!found)
 				intel_hdmi_init(dev, SDVOB, PORT_B);
 			if (!found && (I915_READ(DP_B) & DP_DETECTED))
 				intel_dp_init(dev, DP_B, PORT_B);
+		}
 		if (I915_READ(SDVOC) & PORT_DETECTED)
 			intel_hdmi_init(dev, SDVOC, PORT_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 		if (I915_READ(SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOB\n");
 			found = intel_sdvo_init(dev, SDVOB, true);
 			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
 				intel_hdmi_init(dev, SDVOB, PORT_B);
+			}
 			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
 				DRM_DEBUG_KMS("probing DP_B\n");
 				intel_dp_init(dev, DP_B, PORT_B);
+			}
+		}
 		/* Before G4X SDVOC doesn't have its own detect register */
 		if (I915_READ(SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOC\n");
 			found = intel_sdvo_init(dev, SDVOC, false);
+		}
 		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
 			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
 				intel_hdmi_init(dev, SDVOC, PORT_C);
+			}
 			if (SUPPORTS_INTEGRATED_DP(dev)) {
 				DRM_DEBUG_KMS("probing DP_C\n");
 				intel_dp_init(dev, DP_C, PORT_C);
+			}
+		}
 		if (SUPPORTS_INTEGRATED_DP(dev) &&
 		    (I915_READ(DP_D) & DP_DETECTED)) {
 			DRM_DEBUG_KMS("probing DP_D\n");
 			intel_dp_init(dev, DP_D, PORT_D);
+		}
 	} else if (IS_GEN2(dev))
 		intel_dvo_init(dev);
 	if (SUPPORTS_TV(dev))
 		intel_tv_init(dev);
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 		encoder->base.possible_crtcs = encoder->crtc_mask;
 		encoder->base.possible_clones =
 			intel_encoder_clones(encoder);
+	}
 	intel_init_pch_refclk(dev);
 	drm_helper_move_panel_connectors_to_head(dev);
+}
 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	drm_framebuffer_cleanup(fb);
 	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
 	kfree(intel_fb);
+}
 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 						struct drm_file *file,
 						unsigned int *handle)
+{
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	return drm_gem_handle_create(file, &obj->base, handle);
+}
 static const struct drm_framebuffer_funcs intel_fb_funcs = {
 	.destroy = intel_user_framebuffer_destroy,
 	.create_handle = intel_user_framebuffer_create_handle,
 };
 int intel_framebuffer_init(struct drm_device *dev,
 			   struct intel_framebuffer *intel_fb,
 			   struct drm_mode_fb_cmd2 *mode_cmd,
 			   struct drm_i915_gem_object *obj)
+{
 	int ret;
 	if (obj->tiling_mode == I915_TILING_Y) {
 		DRM_DEBUG("hardware does not support tiling Y\n");
 		return -EINVAL;
+	}
 	if (mode_cmd->pitches[0] & 63) {
 		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
 			  mode_cmd->pitches[0]);
 		return -EINVAL;
+	}
 	/* FIXME <= Gen4 stride limits are bit unclear */
 	if (mode_cmd->pitches[0] > 32768) {
 		DRM_DEBUG("pitch (%d) must be at less than 32768\n",
 			  mode_cmd->pitches[0]);
 		return -EINVAL;
+	}
 	if (obj->tiling_mode != I915_TILING_NONE &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
 		return -EINVAL;
+	}
 	/* Reject formats not supported by any plane early. */
 	switch (mode_cmd->pixel_format) {
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 		break;
 	case DRM_FORMAT_XRGB1555:
 	case DRM_FORMAT_ARGB1555:
 		if (INTEL_INFO(dev)->gen > 3) {
 			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_ARGB2101010:
 	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_ABGR2101010:
 		if (INTEL_INFO(dev)->gen < 4) {
 			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_VYUY:
 		if (INTEL_INFO(dev)->gen < 5) {
 			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
 			return -EINVAL;
+		}
 		break;
 	default:
 		DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
 		return -EINVAL;
+	}
 	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
 	if (mode_cmd->offsets[0] != 0)
 		return -EINVAL;
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
 		DRM_ERROR("framebuffer init failed %d\n", ret);
 		return ret;
+	}
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
 	intel_fb->obj = obj;
 	return 0;
+}
 static struct drm_framebuffer *
 intel_user_framebuffer_create(struct drm_device *dev,
 			      struct drm_file *filp,
 			      struct drm_mode_fb_cmd2 *mode_cmd)
+{
 	struct drm_i915_gem_object *obj;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
 						mode_cmd->handles[0]));
 	if (&obj->base == NULL)
 		return ERR_PTR(-ENOENT);
 	return intel_framebuffer_create(dev, mode_cmd, obj);
+}
 static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.fb_create = intel_user_framebuffer_create,
 	.output_poll_changed = intel_fb_output_poll_changed,
 };
 /* Set up chip specific display functions */
 static void intel_init_display(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* We always want a DPMS function */
 	if (IS_HASWELL(dev)) {
 		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
 		dev_priv->display.off = haswell_crtc_off;
 		dev_priv->display.update_plane = ironlake_update_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
 		dev_priv->display.off = ironlake_crtc_off;
 		dev_priv->display.update_plane = ironlake_update_plane;
 	} else {
 		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
 		dev_priv->display.crtc_enable = i9xx_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
 		dev_priv->display.off = i9xx_crtc_off;
 		dev_priv->display.update_plane = i9xx_update_plane;
+	}
 	/* Returns the core display clock speed */
 	if (IS_VALLEYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915_get_display_clock_speed;
 	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
 		dev_priv->display.get_display_clock_speed =
 			i9xx_misc_get_display_clock_speed;
 	else if (IS_I915GM(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915gm_get_display_clock_speed;
 	else if (IS_I865G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i865_get_display_clock_speed;
 	else if (IS_I85X(dev))
 		dev_priv->display.get_display_clock_speed =
 			i855_get_display_clock_speed;
 	else /* 852, 830 */
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 	if (HAS_PCH_SPLIT(dev)) {
 		if (IS_GEN5(dev)) {
 			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else if (IS_GEN6(dev)) {
 			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else if (IS_IVYBRIDGE(dev)) {
 			/* FIXME: detect B0+ stepping and use auto training */
 			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
 			dev_priv->display.write_eld = ironlake_write_eld;
 			dev_priv->display.modeset_global_resources =
 				ivb_modeset_global_resources;
 		} else if (IS_HASWELL(dev)) {
 			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 			dev_priv->display.write_eld = haswell_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_G4X(dev)) {
 		dev_priv->display.write_eld = g4x_write_eld;
+	}
 	/* Default just returns -ENODEV to indicate unsupported */
 	dev_priv->display.queue_flip = intel_default_queue_flip;
 	switch (INTEL_INFO(dev)->gen) {
 	case 2:
 		dev_priv->display.queue_flip = intel_gen2_queue_flip;
 		break;
 	case 3:
 		dev_priv->display.queue_flip = intel_gen3_queue_flip;
 		break;
 	case 4:
 	case 5:
 		dev_priv->display.queue_flip = intel_gen4_queue_flip;
 		break;
 	case 6:
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
 	case 7:
 		dev_priv->display.queue_flip = intel_gen7_queue_flip;
 		break;
+	}
+}
 #ifndef __NetBSD__		/* XXX dmi hack */
 /*
  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  * resume, or other times.  This quirk makes sure that's the case for
  * affected systems.
  */
 static void quirk_pipea_force(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
 	DRM_INFO("applying pipe a force quirk\n");
+}
 /*
  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  */
 static void quirk_ssc_force_disable(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
 	DRM_INFO("applying lvds SSC disable quirk\n");
+}
 /*
  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  * brightness value
  */
 static void quirk_invert_brightness(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
 	DRM_INFO("applying inverted panel brightness quirk\n");
+}
 struct intel_quirk {
 	int device;
 	int subsystem_vendor;
 	int subsystem_device;
 	void (*hook)(struct drm_device *dev);
 };
 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
 struct intel_dmi_quirk {
 	void (*hook)(struct drm_device *dev);
 	const struct dmi_system_id (*dmi_id_list)[];
 };
 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
+{
 	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
 	return 1;
+}
 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
+	{
 		.dmi_id_list = &(const struct dmi_system_id[]) {
+			{
 				.callback = intel_dmi_reverse_brightness,
 				.ident = "NCR Corporation",
 				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
 					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
 				},
 			},
 			{ }  /* terminating entry */
 		},
 		.hook = quirk_invert_brightness,
 	},
 };
 static struct intel_quirk intel_quirks[] = {
 	/* HP Mini needs pipe A force quirk (LP: #322104) */
 	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
 	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
 	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
 	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
 	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
 	/* 830/845 need to leave pipe A & dpll A up */
 	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 	/* Sony Vaio Y cannot use SSC on LVDS */
 	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 	/* Acer Aspire 5734Z must invert backlight brightness */
 	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
 };
 static void intel_init_quirks(struct drm_device *dev)
+{
 	struct pci_dev *d = dev->pdev;
 	int i;
 	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
 		struct intel_quirk *q = &intel_quirks[i];
 		if (d->device == q->device &&
 		    (d->subsystem_vendor == q->subsystem_vendor ||
 		     q->subsystem_vendor == PCI_ANY_ID) &&
 		    (d->subsystem_device == q->subsystem_device ||
 		     q->subsystem_device == PCI_ANY_ID))
 			q->hook(dev);
+	}
 	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
 		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
 			intel_dmi_quirks[i].hook(dev);
+	}
+}
 #endif
 /* Disable the VGA plane that we never use */
 static void i915_disable_vga(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u8 sr1;
 	u32 vga_reg;
 	if (HAS_PCH_SPLIT(dev))
 		vga_reg = CPU_VGACNTRL;
 	else
 		vga_reg = VGACNTRL;
 	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 	outb(SR01, VGA_SR_INDEX);
 	sr1 = inb(VGA_SR_DATA);
 	outb(sr1 | 1<<5, VGA_SR_DATA);
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 	udelay(300);
 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
 	POSTING_READ(vga_reg);
+}
 void intel_modeset_init_hw(struct drm_device *dev)
+{
 	/* We attempt to init the necessary power wells early in the initialization
 	 * time, so the subsystems that expect power to be enabled can work.
 	 */
 	intel_init_power_wells(dev);
 	intel_prepare_ddi(dev);
 	intel_init_clock_gating(dev);
 	mutex_lock(&dev->struct_mutex);
 	intel_enable_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
+}
 void intel_modeset_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i, ret;
 	drm_mode_config_init(dev);
 	dev->mode_config.min_width = 0;
 	dev->mode_config.min_height = 0;
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
 	dev->mode_config.funcs = &intel_mode_funcs;
 #ifndef __NetBSD__		/* XXX dmi hack */
 	intel_init_quirks(dev);
 #endif
 	intel_init_pm(dev);
 	intel_init_display(dev);
 	if (IS_GEN2(dev)) {
 		dev->mode_config.max_width = 2048;
 		dev->mode_config.max_height = 2048;
 	} else if (IS_GEN3(dev)) {
 		dev->mode_config.max_width = 4096;
 		dev->mode_config.max_height = 4096;
 	} else {
 		dev->mode_config.max_width = 8192;
 		dev->mode_config.max_height = 8192;
+	}
 	dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
 		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
 	for (i = 0; i < dev_priv->num_pipe; i++) {
 		intel_crtc_init(dev, i);
 		ret = intel_plane_init(dev, i);
 		if (ret)
 			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
+	}
 	intel_cpu_pll_init(dev);
 	intel_pch_pll_init(dev);
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
 	intel_setup_outputs(dev);
+}
 static void
 intel_connector_break_all_links(struct intel_connector *connector)
+{
 	connector->base.dpms = DRM_MODE_DPMS_OFF;
 	connector->base.encoder = NULL;
 	connector->encoder->connectors_active = false;
 	connector->encoder->base.crtc = NULL;
+}
 static void intel_enable_pipe_a(struct drm_device *dev)
+{
 	struct intel_connector *connector;
 	struct drm_connector *crt = NULL;
 	struct intel_load_detect_pipe load_detect_temp;
 	/* We can't just switch on the pipe A, we need to set things up with a
 	 * proper mode and output configuration. As a gross hack, enable pipe A
 	 * by enabling the load detect pipe once. */
 	list_for_each_entry(connector,
 			    &dev->mode_config.connector_list,
 			    base.head) {
 		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
 			crt = &connector->base;
 			break;
+		}
+	}
 	if (!crt)
 		return;
 	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
 		intel_release_load_detect_pipe(crt, &load_detect_temp);
+}
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
+{
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	u32 reg, val;
 	if (dev_priv->num_pipe == 1)
 		return true;
 	reg = DSPCNTR(!crtc->plane);
 	val = I915_READ(reg);
 	if ((val & DISPLAY_PLANE_ENABLE) &&
 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
 		return false;
 	return true;
+}
 static void intel_sanitize_crtc(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg;
 	/* Clear any frame start delays used for debugging left by the BIOS */
 	reg = PIPECONF(crtc->cpu_transcoder);
 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 	/* We need to sanitize the plane -> pipe mapping first because this will
 	 * disable the crtc (and hence change the state) if it is wrong. Note
 	 * that gen4+ has a fixed plane -> pipe mapping.  */
 	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
 		struct intel_connector *connector;
 		bool plane;
 		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
 			      crtc->base.base.id);
 		/* Pipe has the wrong plane attached and the plane is active.
 		 * Temporarily change the plane mapping and disable everything
 		 * ...  */
 		plane = crtc->plane;
 		crtc->plane = !plane;
 		dev_priv->display.crtc_disable(&crtc->base);
 		crtc->plane = plane;
 		/* ... and break all links. */
 		list_for_each_entry(connector, &dev->mode_config.connector_list,
 				    base.head) {
 			if (connector->encoder->base.crtc != &crtc->base)
 				continue;
 			intel_connector_break_all_links(connector);
+		}
 		WARN_ON(crtc->active);
 		crtc->base.enabled = false;
+	}
 	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
 	    crtc->pipe == PIPE_A && !crtc->active) {
 		/* BIOS forgot to enable pipe A, this mostly happens after
 		 * resume. Force-enable the pipe to fix this, the update_dpms
 		 * call below we restore the pipe to the right state, but leave
 		 * the required bits on. */
 		intel_enable_pipe_a(dev);
+	}
 	/* Adjust the state of the output pipe according to whether we
 	 * have active connectors/encoders. */
 	intel_crtc_update_dpms(&crtc->base);
 	if (crtc->active != crtc->base.enabled) {
 		struct intel_encoder *encoder;
 		/* This can happen either due to bugs in the get_hw_state
 		 * functions or because the pipe is force-enabled due to the
 		 * pipe A quirk. */
 		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
 			      crtc->base.base.id,
 			      crtc->base.enabled ? "enabled" : "disabled",
 			      crtc->active ? "enabled" : "disabled");
 		crtc->base.enabled = crtc->active;
 		/* Because we only establish the connector -> encoder ->
 		 * crtc links if something is active, this means the
 		 * crtc is now deactivated. Break the links. connector
 		 * -> encoder links are only establish when things are
 		 *  actually up, hence no need to break them. */
 		WARN_ON(crtc->active);
 		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 			WARN_ON(encoder->connectors_active);
 			encoder->base.crtc = NULL;
+		}
+	}
+}
 static void intel_sanitize_encoder(struct intel_encoder *encoder)
+{
 	struct intel_connector *connector;
 	struct drm_device *dev = encoder->base.dev;
 	/* We need to check both for a crtc link (meaning that the
 	 * encoder is active and trying to read from a pipe) and the
 	 * pipe itself being active. */
 	bool has_active_crtc = encoder->base.crtc &&
 		to_intel_crtc(encoder->base.crtc)->active;
 	if (encoder->connectors_active && !has_active_crtc) {
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 			      encoder->base.base.id,
 			      drm_get_encoder_name(&encoder->base));
 		/* Connector is active, but has no active pipe. This is
 		 * fallout from our resume register restoring. Disable
 		 * the encoder manually again. */
 		if (encoder->base.crtc) {
 			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
 				      encoder->base.base.id,
 				      drm_get_encoder_name(&encoder->base));
 			encoder->disable(encoder);
+		}
 		/* Inconsistent output/port/pipe state happens presumably due to
 		 * a bug in one of the get_hw_state functions. Or someplace else
 		 * in our code, like the register restore mess on resume. Clamp
 		 * things to off as a safer default. */
 		list_for_each_entry(connector,
 				    &dev->mode_config.connector_list,
 				    base.head) {
 			if (connector->encoder != encoder)
 				continue;
 			intel_connector_break_all_links(connector);
+		}
+	}
 	/* Enabled encoders without active connectors will be fixed in
 	 * the crtc fixup. */
+}
 static void i915_redisable_vga(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 vga_reg;
 	if (HAS_PCH_SPLIT(dev))
 		vga_reg = CPU_VGACNTRL;
 	else
 		vga_reg = VGACNTRL;
 	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
 		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
 		I915_WRITE(vga_reg, VGA_DISP_DISABLE);
 		POSTING_READ(vga_reg);
+	}
+}
 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  * and i915 state tracking structures. */
 void intel_modeset_setup_hw_state(struct drm_device *dev,
 				  bool force_restore)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe;
 	u32 tmp;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	if (IS_HASWELL(dev)) {
 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 		if (tmp & TRANS_DDI_FUNC_ENABLE) {
 			switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 			case TRANS_DDI_EDP_INPUT_A_ON:
 			case TRANS_DDI_EDP_INPUT_A_ONOFF:
 				pipe = PIPE_A;
 				break;
 			case TRANS_DDI_EDP_INPUT_B_ONOFF:
 				pipe = PIPE_B;
 				break;
 			case TRANS_DDI_EDP_INPUT_C_ONOFF:
 				pipe = PIPE_C;
 				break;
+			}
 			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 			crtc->cpu_transcoder = TRANSCODER_EDP;
 			DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
 				      pipe_name(pipe));
+		}
+	}
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 		tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
 		if (tmp & PIPECONF_ENABLE)
 			crtc->active = true;
 		else
 			crtc->active = false;
 		crtc->base.enabled = crtc->active;
 		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
 			      crtc->base.base.id,
 			      crtc->active ? "enabled" : "disabled");
+	}
 	if (IS_HASWELL(dev))
 		intel_ddi_setup_hw_pll_state(dev);
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		pipe = 0;
 		if (encoder->get_hw_state(encoder, &pipe)) {
 			encoder->base.crtc =
 				dev_priv->pipe_to_crtc_mapping[pipe];
 		} else {
 			encoder->base.crtc = NULL;
+		}
 		encoder->connectors_active = false;
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
 			      encoder->base.base.id,
 			      drm_get_encoder_name(&encoder->base),
 			      encoder->base.crtc ? "enabled" : "disabled",
 			      pipe);
+	}
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
 		if (connector->get_hw_state(connector)) {
 			connector->base.dpms = DRM_MODE_DPMS_ON;
 			connector->encoder->connectors_active = true;
 			connector->base.encoder = &connector->encoder->base;
 		} else {
 			connector->base.dpms = DRM_MODE_DPMS_OFF;
 			connector->base.encoder = NULL;
+		}
 		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
 			      connector->base.base.id,
 			      drm_get_connector_name(&connector->base),
 			      connector->base.encoder ? "enabled" : "disabled");
+	}
 	/* HW state is read out, now we need to sanitize this mess. */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		intel_sanitize_encoder(encoder);
+	}
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 		intel_sanitize_crtc(crtc);
+	}
 	if (force_restore) {
 		for_each_pipe(pipe) {
 			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 			intel_set_mode(&crtc->base, &crtc->base.mode,
 				       crtc->base.x, crtc->base.y, crtc->base.fb);
+		}
 		i915_redisable_vga(dev);
 	} else {
 		intel_modeset_update_staged_output_state(dev);
+	}
 	intel_modeset_check_state(dev);
 	drm_mode_config_reset(dev);
+}
 void intel_modeset_gem_init(struct drm_device *dev)
+{
 	intel_modeset_init_hw(dev);
 	intel_setup_overlay(dev);
 	intel_modeset_setup_hw_state(dev, false);
+}
 void intel_modeset_cleanup(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
 	drm_kms_helper_poll_fini(dev);
 	mutex_lock(&dev->struct_mutex);
 	intel_unregister_dsm_handler();
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		/* Skip inactive CRTCs */
 		if (!crtc->fb)
 			continue;
 		intel_crtc = to_intel_crtc(crtc);
 		intel_increase_pllclock(crtc);
+	}
 	intel_disable_fbc(dev);
 	intel_disable_gt_powersave(dev);
 	ironlake_teardown_rc6(dev);
 	if (IS_VALLEYVIEW(dev))
 		vlv_init_dpio(dev);
 	mutex_unlock(&dev->struct_mutex);
 	/* Disable the irq before mode object teardown, for the irq might
 	 * enqueue unpin/hotplug work. */
 	drm_irq_uninstall(dev);
 	cancel_work_sync(&dev_priv->hotplug_work);
 	cancel_work_sync(&dev_priv->rps.work);
 	/* flush any delayed tasks or pending work */
 	flush_scheduled_work();
 	drm_mode_config_cleanup(dev);
+}
 /*
  * Return which encoder is currently attached for connector.
  */
 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
+{
 	return &intel_attached_encoder(connector)->base;
+}
 void intel_connector_attach_encoder(struct intel_connector *connector,
 				    struct intel_encoder *encoder)
+{
 	connector->encoder = encoder;
 	drm_mode_connector_attach_encoder(&connector->base,
 					  &encoder->base);
+}
 /*
  * set vga decode state - true == enable VGA decode
  */
 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 gmch_ctrl;
 	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
 	if (state)
 		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
 	else
 		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
 	return 0;
+}
 #ifdef CONFIG_DEBUG_FS
 #include <linux/seq_file.h>
 struct intel_display_error_state {
 	struct intel_cursor_error_state {
 		u32 control;
 		u32 position;
 		u32 base;
 		u32 size;
 	} cursor[I915_MAX_PIPES];
 	struct intel_pipe_error_state {
 		u32 conf;
 		u32 source;
 		u32 htotal;
 		u32 hblank;
 		u32 hsync;
 		u32 vtotal;
 		u32 vblank;
 		u32 vsync;
 	} pipe[I915_MAX_PIPES];
 	struct intel_plane_error_state {
 		u32 control;
 		u32 stride;
 		u32 size;
 		u32 pos;
 		u32 addr;
 		u32 surface;
 		u32 tile_offset;
 	} plane[I915_MAX_PIPES];
 };
 struct intel_display_error_state *
 intel_display_capture_error_state(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_display_error_state *error;
 	enum transcoder cpu_transcoder;
 	int i;
 	error = kmalloc(sizeof(*error), GFP_ATOMIC);
 	if (error == NULL)
 		return NULL;
 	for_each_pipe(i) {
 		cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
 		error->cursor[i].control = I915_READ(CURCNTR(i));
 		error->cursor[i].position = I915_READ(CURPOS(i));
 		error->cursor[i].base = I915_READ(CURBASE(i));
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
 		error->plane[i].size = I915_READ(DSPSIZE(i));
 		error->plane[i].pos = I915_READ(DSPPOS(i));
 		error->plane[i].addr = I915_READ(DSPADDR(i));
 		if (INTEL_INFO(dev)->gen >= 4) {
 			error->plane[i].surface = I915_READ(DSPSURF(i));
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
+		}
 		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
 		error->pipe[i].source = I915_READ(PIPESRC(i));
 		error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
 		error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
 		error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
 		error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
 		error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
 		error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
+	}
 	return error;
+}
 void
 intel_display_print_error_state(struct seq_file *m,
 				struct drm_device *dev,
 				struct intel_display_error_state *error)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 	seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
 	for_each_pipe(i) {
 		seq_printf(m, "Pipe [%d]:\n", i);
 		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
 		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
 		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
 		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
 		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
 		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
 		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
 		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
 		seq_printf(m, "Plane [%d]:\n", i);
 		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
 		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
 		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
 		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
 		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
 		if (INTEL_INFO(dev)->gen >= 4) {
 			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
 			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
+		}
 		seq_printf(m, "Cursor [%d]:\n", i);
 		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
 		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
 		seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
+	}
+}
 #endif