Sat Sep 7 00:35:53 2013 UTC ()
Flesh out allwinner support.


(matt)
diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/awin_ahcisata.c
diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/awin_board.c
diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/awin_intr.h
diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/awin_sdhc.c
diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_com.c
diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_gpio.c
diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_io.c
diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_twi.c
diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_usb.c
diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/awin_reg.h
diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/awin_var.h
diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/files.awin
cvs diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/Attic/awin_ahcisata.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_ahcisata.c 2013/09/04 09:09:25 1.2
+++ src/sys/arch/arm/allwinner/Attic/awin_ahcisata.c 2013/09/07 00:35:52 1.3
@@ -21,28 +21,29 @@ @@ -21,28 +21,29 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.2 2013/09/04 09:09:25 jmcneill Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
35 35
 36#include <sys/param.h>
36#include <sys/bus.h> 37#include <sys/bus.h>
37#include <sys/device.h> 38#include <sys/device.h>
38#include <sys/intr.h> 39#include <sys/intr.h>
39#include <sys/systm.h> 40#include <sys/systm.h>
40 41
41#include <arm/allwinner/awin_reg.h> 42#include <arm/allwinner/awin_reg.h>
42#include <arm/allwinner/awin_var.h> 43#include <arm/allwinner/awin_var.h>
43 44
44#include <dev/ata/atavar.h> 45#include <dev/ata/atavar.h>
45#include <dev/ic/ahcisatavar.h> 46#include <dev/ic/ahcisatavar.h>
46 47
47static int awin_ahci_match(device_t, cfdata_t, void *); 48static int awin_ahci_match(device_t, cfdata_t, void *);
48static void awin_ahci_attach(device_t, device_t, void *); 49static void awin_ahci_attach(device_t, device_t, void *);
@@ -61,34 +62,68 @@ awin_ahci_match(device_t parent, cfdata_ @@ -61,34 +62,68 @@ awin_ahci_match(device_t parent, cfdata_
61 struct awinio_attach_args * const aio = aux; 62 struct awinio_attach_args * const aio = aux;
62 const struct awin_locators * const loc = &aio->aio_loc; 63 const struct awin_locators * const loc = &aio->aio_loc;
63 const int port = cf->cf_loc[AWINIOCF_PORT]; 64 const int port = cf->cf_loc[AWINIOCF_PORT];
64 65
65 if (strcmp(cf->cf_name, loc->loc_name)) 66 if (strcmp(cf->cf_name, loc->loc_name))
66 return 0; 67 return 0;
67 68
68 if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port) 69 if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port)
69 return 0; 70 return 0;
70 71
71 return 1; 72 return 1;
72} 73}
73 74
 75static void inline
 76awin_ahci_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
 77 bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
 78{
 79 const uint32_t old = bus_space_read_4(bst, bsh, o);
 80 const uint32_t new = set_mask | (old & ~clr_mask);
 81 if (old != new) {
 82 bus_space_write_4(bst, bsh, o, new);
 83 }
 84}
 85
 86static void
 87awin_ahci_enable(bus_space_tag_t bst, bus_space_handle_t bsh)
 88{
 89 /*
 90 * SATA needs PLL6 to be a 100MHz clock.
 91 */
 92 awin_pll6_enable();
 93
 94 /*
 95 * Make sure it's enabled for the AHB.
 96 */
 97 awin_ahci_set_clear(bst, bsh, AWIN_AHB_GATING0_REG,
 98 AWIN_AHB_GATING0_SATA, 0);
 99 delay(10000);
 100
 101 /*
 102 * Now turn it on.
 103 */
 104 bus_space_write_4(bst, bsh, AWIN_SATA_CLK_REG, AWIN_CLK_ENABLE);
 105}
 106
74static void 107static void
75awin_ahci_attach(device_t parent, device_t self, void *aux) 108awin_ahci_attach(device_t parent, device_t self, void *aux)
76{ 109{
77 struct awin_ahci_softc * const asc = device_private(self); 110 struct awin_ahci_softc * const asc = device_private(self);
78 struct ahci_softc * const sc = &asc->asc_sc; 111 struct ahci_softc * const sc = &asc->asc_sc;
79 struct awinio_attach_args * const aio = aux; 112 struct awinio_attach_args * const aio = aux;
80 const struct awin_locators * const loc = &aio->aio_loc; 113 const struct awin_locators * const loc = &aio->aio_loc;
81 114
 115 awin_ahci_enable(aio->aio_core_bst, aio->aio_ccm_bsh);
 116
82 sc->sc_atac.atac_dev = self; 117 sc->sc_atac.atac_dev = self;
83 sc->sc_dmat = aio->aio_dmat; 118 sc->sc_dmat = aio->aio_dmat;
84 sc->sc_ahcit = aio->aio_core_bst; 119 sc->sc_ahcit = aio->aio_core_bst;
85 sc->sc_ahcis = loc->loc_size; 120 sc->sc_ahcis = loc->loc_size;
86 121
87 bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh, 122 bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
88 loc->loc_offset, loc->loc_size, &sc->sc_ahcih); 123 loc->loc_offset, loc->loc_size, &sc->sc_ahcih);
89 124
90 aprint_naive(": AHCI SATA controller\n"); 125 aprint_naive(": AHCI SATA controller\n");
91 aprint_normal(": AHCI SATA controller\n"); 126 aprint_normal(": AHCI SATA controller\n");
92 127
93 asc->asc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL, 128 asc->asc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL,
94 ahci_intr, sc); 129 ahci_intr, sc);
cvs diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/Attic/awin_board.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_board.c 2013/09/04 17:45:40 1.2
+++ src/sys/arch/arm/allwinner/Attic/awin_board.c 2013/09/07 00:35:52 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $ */ 1/* $NetBSD: awin_board.c,v 1.3 2013/09/07 00:35:52 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -24,27 +24,27 @@ @@ -24,27 +24,27 @@
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#include "opt_allwinner.h" 31#include "opt_allwinner.h"
32 32
33#define _ARM32_BUS_DMA_PRIVATE 33#define _ARM32_BUS_DMA_PRIVATE
34 34
35#include <sys/cdefs.h> 35#include <sys/cdefs.h>
36 36
37__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $"); 37__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
38 38
39#include <sys/param.h> 39#include <sys/param.h>
40#include <sys/bus.h> 40#include <sys/bus.h>
41#include <sys/cpu.h> 41#include <sys/cpu.h>
42#include <sys/device.h> 42#include <sys/device.h>
43 43
44#include <prop/proplib.h> 44#include <prop/proplib.h>
45 45
46#include <net/if.h> 46#include <net/if.h>
47#include <net/if_ether.h> 47#include <net/if_ether.h>
48 48
49#include <arm/mainbus/mainbus.h> 49#include <arm/mainbus/mainbus.h>
50 50
@@ -54,27 +54,27 @@ __KERNEL_RCSID(1, "$NetBSD: awin_board.c @@ -54,27 +54,27 @@ __KERNEL_RCSID(1, "$NetBSD: awin_board.c
54bus_space_handle_t awin_core_bsh; 54bus_space_handle_t awin_core_bsh;
55 55
56struct arm32_bus_dma_tag awin_dma_tag = { 56struct arm32_bus_dma_tag awin_dma_tag = {
57 _BUS_DMAMAP_FUNCS, 57 _BUS_DMAMAP_FUNCS,
58 _BUS_DMAMEM_FUNCS, 58 _BUS_DMAMEM_FUNCS,
59 _BUS_DMATAG_FUNCS, 59 _BUS_DMATAG_FUNCS,
60}; 60};
61 61
62#ifdef AWIN_CONSOLE_EARLY 62#ifdef AWIN_CONSOLE_EARLY
63#include <dev/ic/ns16550reg.h> 63#include <dev/ic/ns16550reg.h>
64#include <dev/ic/comreg.h> 64#include <dev/ic/comreg.h>
65#include <dev/cons.h> 65#include <dev/cons.h>
66 66
67static volatile uin32t_t *uart_base; 67static volatile uint32_t *uart_base;
68 68
69static int 69static int
70awin_cngetc(dev_t dv) 70awin_cngetc(dev_t dv)
71{ 71{
72 if ((uart_base[com_lsr] & LSR_RXRDY) == 0) 72 if ((uart_base[com_lsr] & LSR_RXRDY) == 0)
73 return -1; 73 return -1;
74 74
75 return uart_base[com_data] & 0xff; 75 return uart_base[com_data] & 0xff;
76} 76}
77 77
78static void 78static void
79awin_cnputc(dev_t dv, int c) 79awin_cnputc(dev_t dv, int c)
80{ 80{
@@ -85,88 +85,121 @@ awin_cnputc(dev_t dv, int c) @@ -85,88 +85,121 @@ awin_cnputc(dev_t dv, int c)
85 85
86 uart_base[com_data] = c & 0xff; 86 uart_base[com_data] = c & 0xff;
87 87
88 timo = 150000; 88 timo = 150000;
89 while ((uart_base[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 89 while ((uart_base[com_lsr] & LSR_TSRE) == 0 && --timo > 0)
90 ; 90 ;
91} 91}
92 92
93static struct consdev awin_earlycons = { 93static struct consdev awin_earlycons = {
94 .cn_putc = awin_cnputc, 94 .cn_putc = awin_cnputc,
95 .cn_getc = awin_cngetc, 95 .cn_getc = awin_cngetc,
96 .cn_pollc = nullcnpollc, 96 .cn_pollc = nullcnpollc,
97}; 97};
98#endif /* BCM53XX_CONSOLE_EARLY */ 98#endif /* AWIN_CONSOLE_EARLY */
99 99
100static void 100static void
101awin_cpu_clk(void) 101awin_cpu_clk(void)
102{ 102{
103 struct cpu_info * const ci = curcpu(); 103 struct cpu_info * const ci = curcpu();
104 const uint32_t cpu0_cfg = bus_space_read_4(&awin_bs_tag, awin_core_bsh, 104 const uint32_t cpu0_cfg = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
105 AWIN_CCM_OFFSET + AWIN_CPU_AHB_APB0_CFG_REG); 105 AWIN_CCM_OFFSET + AWIN_CPU_AHB_APB0_CFG_REG);
106 const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL); 106 const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL);
107 switch (cpu_clk_sel) { 107 switch (__SHIFTOUT(cpu_clk_sel, AWIN_CPU_CLK_SRC_SEL)) {
108 case AWIN_CPU_CLK_SRC_SEL_LOSC: 108 case AWIN_CPU_CLK_SRC_SEL_LOSC:
109 ci->ci_data.cpu_cc_freq = 32768; 109 ci->ci_data.cpu_cc_freq = 32768;
110 break; 110 break;
111 case AWIN_CPU_CLK_SRC_SEL_OSC24M: 111 case AWIN_CPU_CLK_SRC_SEL_OSC24M:
112 ci->ci_data.cpu_cc_freq = AWIN_REF_FREQ; 112 ci->ci_data.cpu_cc_freq = AWIN_REF_FREQ;
113 break; 113 break;
114 case AWIN_CPU_CLK_SRC_SEL_PLL1: { 114 case AWIN_CPU_CLK_SRC_SEL_PLL1: {
115 const uint32_t pll1_cfg = bus_space_read_4(&awin_bs_tag, 115 const uint32_t pll1_cfg = bus_space_read_4(&awin_bs_tag,
116 awin_core_bsh, AWIN_CCM_OFFSET + AWIN_PLL1_CFG_REG); 116 awin_core_bsh, AWIN_CCM_OFFSET + AWIN_PLL1_CFG_REG);
117 u_int p = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_OUT_EXP_DIVP); 117 u_int p = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_OUT_EXP_DIVP);
118 u_int n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N); 118 u_int n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N);
119 u_int k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1; 119 u_int k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
120 u_int m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1; 120 u_int m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1;
121 ci->ci_data.cpu_cc_freq = 121 ci->ci_data.cpu_cc_freq =
122 (AWIN_REF_FREQ * (n ? n : 1) * k / m) >> p; 122 ((uint64_t)AWIN_REF_FREQ * (n ? n : 1) * k / m) >> p;
123 break; 123 break;
124 } 124 }
125 case AWIN_CPU_CLK_SRC_SEL_200MHZ: 125 case AWIN_CPU_CLK_SRC_SEL_200MHZ:
126 ci->ci_data.cpu_cc_freq = 200000000; 126 ci->ci_data.cpu_cc_freq = 200000000;
127 break; 127 break;
128 } 128 }
129} 129}
130 130
131void 131void
132awin_bootstrap(vaddr_t iobase, vaddr_t uartbase) 132awin_bootstrap(vaddr_t iobase, vaddr_t uartbase)
133{ 133{
134 int error; 134 int error;
135 135
136#ifdef AWIN_CONSOLE_EARLY 136#ifdef AWIN_CONSOLE_EARLY
137 uart_base = (volatile uint32_t *)uartbase; 137 uart_base = (volatile uint32_t *)uartbase;
138 cn_tab = &awin_earlycons; 138 cn_tab = &awin_earlycons;
 139 printf("Early console started\n");
139#endif 140#endif
140 141
141 error = bus_space_map(&awin_bs_tag, AWIN_CORE_PBASE, 142 error = bus_space_map(&awin_bs_tag, AWIN_CORE_PBASE,
142 AWIN_CORE_SIZE, 0, &awin_core_bsh); 143 AWIN_CORE_SIZE, 0, &awin_core_bsh);
143 if (error) 144 if (error)
144 panic("%s: failed to map BCM53xx %s registers: %d", 145 panic("%s: failed to map a[12]0 %s registers: %d",
145 __func__, "io", error); 146 __func__, "io", error);
146 KASSERT(awin_core_bsh == iobase); 147 KASSERT(awin_core_bsh == iobase);
147 148
 149 printf("CPU Speed is");
148 awin_cpu_clk(); 150 awin_cpu_clk();
 151 printf(" %"PRIu64"\n", curcpu()->ci_data.cpu_cc_freq);
 152
 153 printf("Determining GPIO configuration");
 154 awin_gpio_init();
 155 printf("\n");
149} 156}
150 157
151#ifdef MULTIPROCESSOR 158#ifdef MULTIPROCESSOR
152void 159void
153awin_cpu_hatch(struct cpu_info *ci) 160awin_cpu_hatch(struct cpu_info *ci)
154{ 161{
155 gtmr_init_cpu_clock(ci); 162 gtmr_init_cpu_clock(ci);
156} 163}
157#endif 164#endif
158 165
159psize_t  166psize_t
160awin_memprobe(void) 167awin_memprobe(void)
161{ 168{
162 const uint32_t dcr = bus_space_read_4(&awin_bs_tag, awin_core_bsh, 169 const uint32_t dcr = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
163 AWIN_DRAM_OFFSET + AWIN_DRAM_DCR_REG); 170 AWIN_DRAM_OFFSET + AWIN_DRAM_DCR_REG);
164 171
165 psize_t memsize = __SHIFTOUT(dcr, AWIN_DRAM_DCR_IO_WIDTH); 172 psize_t memsize = __SHIFTOUT(dcr, AWIN_DRAM_DCR_IO_WIDTH);
166 memsize <<= __SHIFTOUT(dcr, AWIN_DRAM_DCR_CHIP_DENSITY) + 28 - 3; 173 memsize <<= __SHIFTOUT(dcr, AWIN_DRAM_DCR_CHIP_DENSITY) + 28 - 3;
167#ifdef VERBOSE_INIT_ARM 174#ifdef VERBOSE_INIT_ARM
168 printf("sdram_config = %#x, memsize = %uMB\n", dcr, 175 printf("sdram_config = %#x, memsize = %uMB\n", dcr,
169 (u_int)(memsize >> 20)); 176 (u_int)(memsize >> 20));
170#endif 177#endif
171 return memsize; 178 return memsize;
172} 179}
 180
 181void
 182awin_pll6_enable(void)
 183{
 184 bus_space_tag_t bst = &awin_bs_tag;
 185 bus_space_handle_t bsh = awin_core_bsh;
 186
 187 /*
 188 * SATA needs PLL6 to be a 100MHz clock.
 189 */
 190 const uint32_t ocfg = bus_space_read_4(bst, bsh, AWIN_PLL6_CFG_REG);
 191 const u_int k = __SHIFTOUT(ocfg, AWIN_PLL_CFG_FACTOR_K);
 192
 193 /*
 194 * Output freq is 24MHz * n * k / m / 6.
 195 * To get to 100MHz, k & m must be equal and n must be 25.
 196 */
 197 uint32_t ncfg = ocfg;
 198 ncfg &= ~(AWIN_PLL_CFG_FACTOR_M|AWIN_PLL_CFG_FACTOR_N);
 199 ncfg |= __SHIFTIN(k, AWIN_PLL_CFG_FACTOR_M);
 200 ncfg |= __SHIFTIN(25, AWIN_PLL_CFG_FACTOR_N);
 201 ncfg |= AWIN_PLL_CFG_ENABLE | AWIN_PLL6_CFG_SATA_CLK_EN;
 202 if (ncfg != ocfg) {
 203 bus_space_write_4(bst, bsh, AWIN_PLL6_CFG_REG, ncfg);
 204 }
 205}
cvs diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/Attic/awin_intr.h (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_intr.h 2013/09/04 02:39:01 1.2
+++ src/sys/arch/arm/allwinner/Attic/awin_intr.h 2013/09/07 00:35:52 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: awin_intr.h,v 1.2 2013/09/04 02:39:01 matt Exp $ */ 1/* $NetBSD: awin_intr.h,v 1.3 2013/09/07 00:35:52 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2013 The NetBSD Foundation, Inc. 3 * Copyright (c) 2013 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -21,28 +21,28 @@ @@ -21,28 +21,28 @@
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#ifndef _ARM_ALLWINNER_AWIN_INTR_H_ 31#ifndef _ARM_ALLWINNER_AWIN_INTR_H_
32#define _ARM_ALLWINNER_AWIN_INTR_H_  32#define _ARM_ALLWINNER_AWIN_INTR_H_
33 33
34#define PIC_MAXSOURCES 128 34#define PIC_MAXSOURCES 160
35#define PIC_MAXMAXSOURCES 256 35#define PIC_MAXMAXSOURCES 192
36 36
37/* 37/*
38 * The Allwinner can use a generic interrupt controller so pull in that stuff. 38 * The Allwinner can use a generic interrupt controller so pull in that stuff.
39 */ 39 */
40#include <arm/cortex/gic_intr.h> 40#include <arm/cortex/gic_intr.h>
41#include <arm/cortex/gtmr_intr.h> /* A7/A9/A15 Timer PPIs */ 41#include <arm/cortex/gtmr_intr.h> /* A7/A9/A15 Timer PPIs */
42 42
43/* 43/*
44 * There are for the A20 but the A10 are the same but offset by 32 less. 44 * There are for the A20 but the A10 are the same but offset by 32 less.
45 */ 45 */
46#define AWIN_IRQ_UART0 33 46#define AWIN_IRQ_UART0 33
47#define AWIN_IRQ_UART1 34 47#define AWIN_IRQ_UART1 34
48#define AWIN_IRQ_UART2 35 48#define AWIN_IRQ_UART2 35
@@ -71,53 +71,53 @@ @@ -71,53 +71,53 @@
71#define AWIN_IRQ_CAN 58 71#define AWIN_IRQ_CAN 58
72#define AWIN_IRQ_DMA 59 72#define AWIN_IRQ_DMA 59
73#define AWIN_IRQ_PIO 60 73#define AWIN_IRQ_PIO 60
74#define AWIN_IRQ_TP 61 74#define AWIN_IRQ_TP 61
75#define AWIN_IRQ_ADDC 62 75#define AWIN_IRQ_ADDC 62
76#define AWIN_IRQ_LRADC 63 76#define AWIN_IRQ_LRADC 63
77#define AWIN_IRQ_SDMMC0 64 77#define AWIN_IRQ_SDMMC0 64
78#define AWIN_IRQ_SDMMC1 65 78#define AWIN_IRQ_SDMMC1 65
79#define AWIN_IRQ_SDMMC2 66 79#define AWIN_IRQ_SDMMC2 66
80#define AWIN_IRQ_SDMMC3 67 80#define AWIN_IRQ_SDMMC3 67
81#define AWIN_IRQ_MS 68 81#define AWIN_IRQ_MS 68
82#define AWIN_IRQ_NAND 69 82#define AWIN_IRQ_NAND 69
83#define AWIN_IRQ_USB0 70 83#define AWIN_IRQ_USB0 70
84#define AWIN_IRQ_USB1 71 84#define AWIN_IRQ_USB1 71 // EHCI0
85#define AWIN_IRQ_USB2 72 85#define AWIN_IRQ_USB2 72 // EHCI1
86#define AWIN_IRQ_SCR 73 86#define AWIN_IRQ_SCR 73
87#define AWIN_IRQ_CSI0 74 87#define AWIN_IRQ_CSI0 74
88#define AWIN_IRQ_CSI1 75 88#define AWIN_IRQ_CSI1 75
89#define AWIN_IRQ_LCD0 76 89#define AWIN_IRQ_LCD0 76
90#define AWIN_IRQ_LCD1 77 90#define AWIN_IRQ_LCD1 77
91#define AWIN_IRQ_MP 78 91#define AWIN_IRQ_MP 78
92#define AWIN_IRQ_DE_XE0 79 92#define AWIN_IRQ_DE_XE0 79
93#define AWIN_IRQ_DE_XE1 80 93#define AWIN_IRQ_DE_XE1 80
94#define AWIN_IRQ_PMU 81 94#define AWIN_IRQ_PMU 81
95#define AWIN_IRQ_SPI3 82 95#define AWIN_IRQ_SPI3 82
96#define AWIN_IRQ_TZASC 83 96#define AWIN_IRQ_TZASC 83
97#define AWIN_IRQ_PATA 84 97#define AWIN_IRQ_PATA 84
98#define AWIN_IRQ_VE 85 98#define AWIN_IRQ_VE 85
99#define AWIN_IRQ_SS 86 99#define AWIN_IRQ_SS 86
100#define AWIN_IRQ_EMAC 87 100#define AWIN_IRQ_EMAC 87
101#define AWIN_IRQ_SATA 88 101#define AWIN_IRQ_SATA 88
102#define AWIN_IRQ__RSVD89 89 102#define AWIN_IRQ__RSVD89 89
103#define AWIN_IRQ_HDMI0 90 103#define AWIN_IRQ_HDMI0 90
104#define AWIN_IRQ_TVE 91 104#define AWIN_IRQ_TVE 91
105#define AWIN_IRQ_ACE 92 105#define AWIN_IRQ_ACE 92
106#define AWIN_IRQ_TVD 93 106#define AWIN_IRQ_TVD 93
107#define AWIN_IRQ_PS2_0 94 107#define AWIN_IRQ_PS2_0 94
108#define AWIN_IRQ_PS2_1 95 108#define AWIN_IRQ_PS2_1 95
109#define AWIN_IRQ_USB3 96 109#define AWIN_IRQ_USB3 96 // OHCI0
110#define AWIN_IRQ_USB4 97 110#define AWIN_IRQ_USB4 97 // OHCI1
111#define AWIN_IRQ_PERFM 98 111#define AWIN_IRQ_PERFM 98
112#define AWIN_IRQ_TMR4 99 112#define AWIN_IRQ_TMR4 99
113#define AWIN_IRQ_TMR5 100 113#define AWIN_IRQ_TMR5 100
114#define AWIN_IRQ_GPU_GP 101 114#define AWIN_IRQ_GPU_GP 101
115#define AWIN_IRQ_GPU_GPMMU 102 115#define AWIN_IRQ_GPU_GPMMU 102
116#define AWIN_IRQ_GPU_PP0 103 116#define AWIN_IRQ_GPU_PP0 103
117#define AWIN_IRQ_GPU_PPMMU0 104 117#define AWIN_IRQ_GPU_PPMMU0 104
118#define AWIN_IRQ_GPU_PMU 105 118#define AWIN_IRQ_GPU_PMU 105
119#define AWIN_IRQ_GPU_PP1 106 119#define AWIN_IRQ_GPU_PP1 106
120#define AWIN_IRQ_GPU_PPMMU1 107 120#define AWIN_IRQ_GPU_PPMMU1 107
121#define AWIN_IRQ_GPU_RSV0 108 121#define AWIN_IRQ_GPU_RSV0 108
122#define AWIN_IRQ_GPU_RSV1 109 122#define AWIN_IRQ_GPU_RSV1 109
123#define AWIN_IRQ_GPU_RSV2 110 123#define AWIN_IRQ_GPU_RSV2 110
cvs diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/Attic/awin_sdhc.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_sdhc.c 2013/09/04 09:14:57 1.2
+++ src/sys/arch/arm/allwinner/Attic/awin_sdhc.c 2013/09/07 00:35:52 1.3
@@ -21,83 +21,104 @@ @@ -21,83 +21,104 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_sdhc.c,v 1.2 2013/09/04 09:14:57 jmcneill Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_sdhc.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
35 35
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/device.h> 37#include <sys/device.h>
38#include <sys/intr.h> 38#include <sys/intr.h>
39#include <sys/systm.h> 39#include <sys/systm.h>
40 40
41#include <arm/allwinner/awin_reg.h> 41#include <arm/allwinner/awin_reg.h>
42#include <arm/allwinner/awin_var.h> 42#include <arm/allwinner/awin_var.h>
43 43
44#include <dev/sdmmc/sdhcreg.h> 44#include <dev/sdmmc/sdhcreg.h>
45#include <dev/sdmmc/sdhcvar.h> 45#include <dev/sdmmc/sdhcvar.h>
46 46
47static int awin_sdhc_match(device_t, cfdata_t, void *); 47static int awin_sdhc_match(device_t, cfdata_t, void *);
48static void awin_sdhc_attach(device_t, device_t, void *); 48static void awin_sdhc_attach(device_t, device_t, void *);
49 49
50struct awin_sdhc_softc { 50struct awin_sdhc_softc {
51 struct sdhc_softc asc_sc; 51 struct sdhc_softc asc_sc;
52 bus_space_tag_t asc_bst; 52 bus_space_tag_t asc_bst;
53 bus_space_handle_t asc_bsh; 53 bus_space_handle_t asc_bsh;
54 struct sdhc_host *asc_hosts[1]; 54 struct sdhc_host *asc_hosts[1];
55 void *asc_ih; 55 void *asc_ih;
56}; 56};
57 57
 58static const struct awin_gpio_pinset awin_sdhc_pinsets[] = {
 59 { 'F', AWIN_PIO_PF_SDC0_FUNC, AWIN_PIO_PF_SDC0_PINS },
 60 { 'G', AWIN_PIO_PG_SDC1_FUNC, AWIN_PIO_PG_SDC1_PINS },
 61 { 'C', AWIN_PIO_PC_SDC2_FUNC, AWIN_PIO_PC_SDC2_PINS },
 62 { 'I', AWIN_PIO_PI_SDC3_FUNC, AWIN_PIO_PI_SDC3_PINS },
 63};
 64
 65static const struct awin_gpio_pinset awin_sdhc_alt_pinsets[] = {
 66 { 0, 0, 0 },
 67 { 'H', AWIN_PIO_PH_SDC1_FUNC, AWIN_PIO_PH_SDC1_PINS },
 68 { 0, 0, 0 },
 69 { 0, 0, 0 },
 70};
 71
58CFATTACH_DECL_NEW(awin_sdhc, sizeof(struct awin_sdhc_softc), 72CFATTACH_DECL_NEW(awin_sdhc, sizeof(struct awin_sdhc_softc),
59 awin_sdhc_match, awin_sdhc_attach, NULL, NULL); 73 awin_sdhc_match, awin_sdhc_attach, NULL, NULL);
60 74
61static int awinsdhc_ports; 75static int awin_sdhc_ports;
62 76
63static int 77static int
64awin_sdhc_match(device_t parent, cfdata_t cf, void *aux) 78awin_sdhc_match(device_t parent, cfdata_t cf, void *aux)
65{ 79{
66 struct awinio_attach_args * const aio = aux; 80 struct awinio_attach_args * const aio = aux;
67 const struct awin_locators * const loc = &aio->aio_loc; 81 const struct awin_locators * const loc = &aio->aio_loc;
68 const int port = cf->cf_loc[AWINIOCF_PORT]; 82 const struct awin_gpio_pinset * const pinset = loc->loc_port
 83 + ((cf->cf_flags & 1) ? awin_sdhc_alt_pinsets : awin_sdhc_pinsets);
69 84
70 if (strcmp(cf->cf_name, loc->loc_name)) 85 KASSERT(!strcmp(cf->cf_name, loc->loc_name));
71 return 0; 86 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
 87 || cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
 88 KASSERT((awin_sdhc_ports & __BIT(loc->loc_port)) == 0);
72 89
73 if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port) 90 if (!awin_gpio_pinset_available(pinset))
74 return 0; 91 return 0;
75 92
76 KASSERT((awinsdhc_ports & __BIT(loc->loc_port)) == 0); 
77 
78 return 1; 93 return 1;
79} 94}
80 95
81static void 96static void
82awin_sdhc_attach(device_t parent, device_t self, void *aux) 97awin_sdhc_attach(device_t parent, device_t self, void *aux)
83{ 98{
84 struct awin_sdhc_softc * const asc = device_private(self); 99 struct awin_sdhc_softc * const asc = device_private(self);
85 struct sdhc_softc * const sc = &asc->asc_sc; 100 struct sdhc_softc * const sc = &asc->asc_sc;
86 struct awinio_attach_args * const aio = aux; 101 struct awinio_attach_args * const aio = aux;
87 const struct awin_locators * const loc = &aio->aio_loc; 102 const struct awin_locators * const loc = &aio->aio_loc;
 103 cfdata_t cf = device_cfdata(self);
 104 const struct awin_gpio_pinset * const pinset = loc->loc_port
 105 + ((cf->cf_flags & 1) ? awin_sdhc_alt_pinsets : awin_sdhc_pinsets);
88 int error; 106 int error;
89 107
90 awinsdhc_ports |= __BIT(loc->loc_port); 108 awin_sdhc_ports |= __BIT(loc->loc_port);
 109
 110 awin_gpio_pinset_acquire(pinset);
 111
91 asc->asc_bst = aio->aio_core_bst; 112 asc->asc_bst = aio->aio_core_bst;
92 bus_space_subregion(asc->asc_bst, aio->aio_core_bsh, 113 bus_space_subregion(asc->asc_bst, aio->aio_core_bsh,
93 loc->loc_offset, loc->loc_size, &asc->asc_bsh); 114 loc->loc_offset, loc->loc_size, &asc->asc_bsh);
94 115
95 sc->sc_dev = self; 116 sc->sc_dev = self;
96 sc->sc_dmat = aio->aio_dmat; 117 sc->sc_dmat = aio->aio_dmat;
97 sc->sc_host = asc->asc_hosts; 118 sc->sc_host = asc->asc_hosts;
98 sc->sc_flags |= SDHC_FLAG_32BIT_ACCESS; 119 sc->sc_flags |= SDHC_FLAG_32BIT_ACCESS;
99 sc->sc_flags |= SDHC_FLAG_HAVE_CGM; 120 sc->sc_flags |= SDHC_FLAG_HAVE_CGM;
100 //sc->sc_flags |= SDHC_FLAG_USE_DMA; 121 //sc->sc_flags |= SDHC_FLAG_USE_DMA;
101 122
102 aprint_naive(": SDHC controller\n"); 123 aprint_naive(": SDHC controller\n");
103 aprint_normal(": SDHC controller%s\n", 124 aprint_normal(": SDHC controller%s\n",
cvs diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/Attic/awin_com.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_com.c 2013/09/04 02:39:01 1.1
+++ src/sys/arch/arm/allwinner/Attic/awin_com.c 2013/09/07 00:35:52 1.2
@@ -21,94 +21,129 @@ @@ -21,94 +21,129 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.1 2013/09/04 02:39:01 matt Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
35 35
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/device.h> 37#include <sys/device.h>
38#include <sys/intr.h> 38#include <sys/intr.h>
39#include <sys/systm.h> 39#include <sys/systm.h>
40#include <sys/time.h> 40#include <sys/time.h>
41#include <sys/termios.h> 41#include <sys/termios.h>
42 42
43#include <arm/allwinner/awin_reg.h> 43#include <arm/allwinner/awin_reg.h>
44#include <arm/allwinner/awin_var.h> 44#include <arm/allwinner/awin_var.h>
45 45
46#include <dev/ic/comvar.h> 46#include <dev/ic/comvar.h>
47 47
48static int awin_com_match(device_t, cfdata_t, void *); 48static int awin_com_match(device_t, cfdata_t, void *);
49static void awin_com_attach(device_t, device_t, void *); 49static void awin_com_attach(device_t, device_t, void *);
50 50
51struct awin_com_softc { 51struct awin_com_softc {
52 struct com_softc asc_sc; 52 struct com_softc asc_sc;
53 void *asc_ih; 53 void *asc_ih;
54}; 54};
55 55
 56static const struct awin_gpio_pinset awin_com_pinsets[] = {
 57 { 'B', AWIN_PIO_PB_UART0_FUNC, AWIN_PIO_PB_UART0_PINS },
 58 { 'A', AWIN_PIO_PA_UART1_FUNC, AWIN_PIO_PA_UART1_PINS },
 59 { 'I', AWIN_PIO_PI_UART2_FUNC, AWIN_PIO_PI_UART2_PINS },
 60 { 'H', AWIN_PIO_PH_UART3_FUNC, AWIN_PIO_PH_UART3_PINS },
 61 { 'H', AWIN_PIO_PH_UART4_FUNC, AWIN_PIO_PH_UART4_PINS },
 62 { 'H', AWIN_PIO_PH_UART5_FUNC, AWIN_PIO_PH_UART5_PINS },
 63 { 'I', AWIN_PIO_PI_UART6_FUNC, AWIN_PIO_PI_UART6_PINS },
 64 { 'I', AWIN_PIO_PI_UART7_FUNC, AWIN_PIO_PI_UART7_PINS },
 65};
 66
 67/* alternative pinnings */
 68static const struct awin_gpio_pinset awin_com_alt_pinsets[] = {
 69 { 'F', AWIN_PIO_PF_UART0_FUNC, AWIN_PIO_PF_UART0_PINS },
 70 { 0, 0, 0},
 71 { 'A', AWIN_PIO_PA_UART2_FUNC, AWIN_PIO_PA_UART2_PINS },
 72 { 'G', AWIN_PIO_PG_UART3_FUNC, AWIN_PIO_PG_UART3_PINS },
 73 { 'G', AWIN_PIO_PG_UART4_FUNC, AWIN_PIO_PG_UART4_PINS },
 74 { 'I', AWIN_PIO_PI_UART5_FUNC, AWIN_PIO_PI_UART5_PINS },
 75 { 'A', AWIN_PIO_PA_UART6_FUNC, AWIN_PIO_PA_UART6_PINS },
 76 { 'A', AWIN_PIO_PA_UART7_FUNC, AWIN_PIO_PA_UART7_PINS },
 77};
 78
56CFATTACH_DECL_NEW(awin_com, sizeof(struct awin_com_softc), 79CFATTACH_DECL_NEW(awin_com, sizeof(struct awin_com_softc),
57 awin_com_match, awin_com_attach, NULL, NULL); 80 awin_com_match, awin_com_attach, NULL, NULL);
58 81
59static int awin_com_ports; 82static int awin_com_ports;
60 83
61static int 84static int
62awin_com_match(device_t parent, cfdata_t cf, void *aux) 85awin_com_match(device_t parent, cfdata_t cf, void *aux)
63{ 86{
64 struct awinio_attach_args * const aio = aux; 87 struct awinio_attach_args * const aio = aux;
65 const struct awin_locators * const loc = &aio->aio_loc; 88 const struct awin_locators * const loc = &aio->aio_loc;
66 const int port = cf->cf_loc[AWINIOCF_PORT]; 
67 bus_space_tag_t iot = aio->aio_core_a4x_bst; 89 bus_space_tag_t iot = aio->aio_core_a4x_bst;
68 bus_space_handle_t bsh; 90 bus_space_handle_t bsh;
69 91 const struct awin_gpio_pinset * const pinset = loc->loc_port +
70 if (strcmp(cf->cf_name, loc->loc_name)) 92 ((cf->cf_flags & 1) ? awin_com_alt_pinsets : awin_com_pinsets);
71 return 0; 
72 93
73 KASSERT(loc->loc_offset >= AWIN_UART0_OFFSET); 94 KASSERT(!strcmp(cf->cf_name, loc->loc_name));
 95 KASSERT(loc->loc_offset >= AWIN_UART0_OFFSET);
74 KASSERT(loc->loc_offset <= AWIN_UART7_OFFSET); 96 KASSERT(loc->loc_offset <= AWIN_UART7_OFFSET);
75 KASSERT((loc->loc_offset & 0x3ff) == 0); 97 KASSERT((loc->loc_offset & 0x3ff) == 0);
76 KASSERT((awin_com_ports & __BIT(loc->loc_port)) == 0); 98 KASSERT((awin_com_ports & __BIT(loc->loc_port)) == 0);
 99 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
 100 || cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
77 101
78 if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port) 102 if (!awin_gpio_pinset_available(pinset))
79 return 0; 103 return 0;
 104
 105 if (com_is_console(iot, AWIN_CORE_PBASE + loc->loc_offset, NULL))
 106 return 1;
 107
 108 awin_gpio_pinset_acquire(pinset);
80 109
81 if (com_is_console(iot, AWIN_CORE_PBASE + loc->loc_offset, NULL)) 110 bus_space_subregion(iot, aio->aio_core_bsh,
82 return 1; 111 loc->loc_offset, loc->loc_size, &bsh);
83 112
84 bus_space_subregion(iot, aio->aio_core_bsh, 113 const int rv = comprobe1(iot, bsh);
85 loc->loc_offset, loc->loc_size, &bsh); 
86 114
87 return comprobe1(iot, bsh); 115 awin_gpio_pinset_release(pinset);
 116
 117 return rv;
88} 118}
89 119
90static void 120static void
91awin_com_attach(device_t parent, device_t self, void *aux) 121awin_com_attach(device_t parent, device_t self, void *aux)
92{ 122{
 123 cfdata_t cf = device_cfdata(self);
93 struct awin_com_softc * const asc = device_private(self); 124 struct awin_com_softc * const asc = device_private(self);
94 struct com_softc * const sc = &asc->asc_sc; 125 struct com_softc * const sc = &asc->asc_sc;
95 struct awinio_attach_args * const aio = aux; 126 struct awinio_attach_args * const aio = aux;
96 const struct awin_locators * const loc = &aio->aio_loc; 127 const struct awin_locators * const loc = &aio->aio_loc;
97 bus_space_tag_t iot = aio->aio_core_a4x_bst; 128 bus_space_tag_t iot = aio->aio_core_a4x_bst;
98 const bus_addr_t iobase = AWIN_CORE_PBASE + loc->loc_offset; 129 const bus_addr_t iobase = AWIN_CORE_PBASE + loc->loc_offset;
 130 const struct awin_gpio_pinset * const pinset = loc->loc_port +
 131 ((cf->cf_flags & 1) ? awin_com_alt_pinsets : awin_com_pinsets);
99 bus_space_handle_t ioh; 132 bus_space_handle_t ioh;
100 133
101 awin_com_ports |= __BIT(loc->loc_port); 134 awin_com_ports |= __BIT(loc->loc_port);
 135
 136 awin_gpio_pinset_acquire(pinset);
102 137
103 sc->sc_dev = self; 138 sc->sc_dev = self;
104 sc->sc_frequency = AWIN_UART_FREQ; 139 sc->sc_frequency = AWIN_UART_FREQ;
105 sc->sc_type = COM_TYPE_NORMAL; 140 sc->sc_type = COM_TYPE_NORMAL;
106 141
107 if (com_is_console(iot, iobase, &ioh) == 0 142 if (com_is_console(iot, iobase, &ioh) == 0
108 && bus_space_subregion(iot, aio->aio_core_bsh, 143 && bus_space_subregion(iot, aio->aio_core_bsh,
109 loc->loc_offset / 4, loc->loc_size, &ioh)) { 144 loc->loc_offset / 4, loc->loc_size, &ioh)) {
110 panic(": can't map registers"); 145 panic(": can't map registers");
111 } 146 }
112 COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase); 147 COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
113 148
114 com_attach_subr(sc); 149 com_attach_subr(sc);
cvs diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/Attic/awin_gpio.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_gpio.c 2013/09/04 02:39:01 1.1
+++ src/sys/arch/arm/allwinner/Attic/awin_gpio.c 2013/09/07 00:35:52 1.2
@@ -21,65 +21,307 @@ @@ -21,65 +21,307 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.1 2013/09/04 02:39:01 matt Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
35 35
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/device.h> 37#include <sys/device.h>
38#include <sys/intr.h> 38#include <sys/intr.h>
39#include <sys/systm.h> 39#include <sys/systm.h>
40 40
 41#include <sys/gpio.h>
 42
 43#include <dev/gpio/gpiovar.h>
 44
41#include <arm/allwinner/awin_reg.h> 45#include <arm/allwinner/awin_reg.h>
42#include <arm/allwinner/awin_var.h> 46#include <arm/allwinner/awin_var.h>
43 47
44static int awin_gpio_match(device_t, cfdata_t, void *); 48static int awin_gpio_match(device_t, cfdata_t, void *);
45static void awin_gpio_attach(device_t, device_t, void *); 49static void awin_gpio_attach(device_t, device_t, void *);
46 50
47struct awin_gpio_softc { 51static const int ist_maps[] = {
 52 [IST_LEVEL_LOW] = AWIN_PIO_EINT_LOW_LEVEL,
 53 [IST_LEVEL_HIGH] = AWIN_PIO_EINT_HIGH_LEVEL,
 54 [IST_EDGE_FALLING] = AWIN_PIO_EINT_POSITIVE_EDGE,
 55 [IST_EDGE_RISING] = AWIN_PIO_EINT_NEGATIVE_EDGE,
 56 [IST_EDGE_BOTH] = AWIN_PIO_EINT_DOUBLE_EDGE,
 57};
 58
 59struct awin_gpio_pin_cfg {
 60 uint32_t val[4];
 61};
 62
 63static struct awin_gpio_pin_group {
 64 uint32_t grp_pin_mask;
 65 uint32_t grp_pin_inuse_mask;
 66 bus_space_handle_t grp_bsh;
 67 struct awin_gpio_pin_cfg grp_cfg;
 68} pin_groups[] = {
 69 [0] = { .grp_pin_mask = __BIT(AWIN_PIO_PA_PINS) - 1 },
 70 [1] = { .grp_pin_mask = __BIT(AWIN_PIO_PB_PINS) - 1 },
 71 [2] = { .grp_pin_mask = __BIT(AWIN_PIO_PC_PINS) - 1 },
 72 [3] = { .grp_pin_mask = __BIT(AWIN_PIO_PD_PINS) - 1 },
 73 [4] = { .grp_pin_mask = __BIT(AWIN_PIO_PE_PINS) - 1 },
 74 [5] = { .grp_pin_mask = __BIT(AWIN_PIO_PF_PINS) - 1 },
 75 [6] = { .grp_pin_mask = __BIT(AWIN_PIO_PG_PINS) - 1 },
 76 [7] = { .grp_pin_mask = __BIT(AWIN_PIO_PH_PINS) - 1 },
 77 [8] = { .grp_pin_mask = __BIT(AWIN_PIO_PI_PINS) - 1 },
 78};
 79
 80struct awin_eint_info {
 81 uint32_t grp_pin ;
 82};
 83
 84static struct awin_gpio_softc {
48 device_t sc_dev; 85 device_t sc_dev;
49 bus_space_tag_t sc_bst; 86 bus_space_tag_t sc_bst;
50 bus_space_handle_t sc_bsh; 87 bus_space_handle_t sc_bsh;
 88} awin_gpio_sc = {
 89 .sc_bst = &awin_bs_tag,
51}; 90};
52 91
53CFATTACH_DECL_NEW(awin_gpio, sizeof(struct awin_gpio_softc), 92CFATTACH_DECL_NEW(awin_gpio, sizeof(struct awin_gpio_softc),
54 awin_gpio_match, awin_gpio_attach, NULL, NULL); 93 awin_gpio_match, awin_gpio_attach, NULL, NULL);
55 94
56static int 95static int
57awin_gpio_match(device_t parent, cfdata_t cf, void *aux) 96awin_gpio_match(device_t parent, cfdata_t cf, void *aux)
58{ 97{
59 struct awinio_attach_args * const aio = aux; 98 struct awinio_attach_args * const aio = aux;
60 const struct awin_locators * const loc = &aio->aio_loc; 99 const struct awin_locators * const loc = &aio->aio_loc;
61 100
62 if (strcmp(cf->cf_name, loc->loc_name)) 101 KASSERT(!strcmp(cf->cf_name, loc->loc_name));
63 return 0; 102 KASSERT(loc->loc_port == AWINIOCF_PORT_DEFAULT);
64 
65 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT); 103 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT);
66 104
 105 if (awin_gpio_sc.sc_dev != NULL)
 106 return 0;
 107
67 return 1; 108 return 1;
68} 109}
69 110
70static void 111static void
71awin_gpio_attach(device_t parent, device_t self, void *aux) 112awin_gpio_attach(device_t parent, device_t self, void *aux)
72{ 113{
73 struct awin_gpio_softc * const sc = device_private(self); 114 struct awin_gpio_softc * const sc = &awin_gpio_sc;
74 struct awinio_attach_args * const aio = aux; 115 struct awinio_attach_args * const aio = aux;
75 const struct awin_locators * const loc = &aio->aio_loc; 116 const struct awin_locators * const loc = &aio->aio_loc;
76 117
77 sc->sc_dev = self; 118 sc->sc_dev = self;
78 119
79 sc->sc_bst = aio->aio_core_bst; 120 sc->sc_bst = aio->aio_core_bst;
80 bus_space_subregion(sc->sc_bst, aio->aio_core_bsh, 121 bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
81 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 122 loc->loc_offset, loc->loc_size, &sc->sc_bsh);
82 123
83 aprint_naive("\n"); 124 aprint_naive("\n");
84 aprint_normal("\n"); 125 aprint_normal("\n");
85} 126}
 127
 128static u_int
 129awin_gpio_get_pin_func(const struct awin_gpio_pin_cfg *cfg, u_int pin)
 130{
 131 const u_int shift = (pin & 7) << 2;
 132 const u_int i = pin >> 3;
 133 return (cfg->val[i] >> shift) & 0x0f;
 134}
 135
 136static void
 137awin_gpio_set_pin_func(struct awin_gpio_pin_cfg *cfg, u_int pin, u_int func)
 138{
 139 const u_int shift = (pin & 7) << 2;
 140 const u_int i = pin >> 3;
 141
 142 cfg->val[i] &= ~(0x0f << shift);
 143 cfg->val[i] |= func << shift;
 144}
 145
 146static void
 147awin_gpio_update_cfg_regs(bus_space_tag_t bst, struct awin_gpio_pin_group *grp,
 148 const struct awin_gpio_pin_cfg *ncfg)
 149{
 150 for (u_int i = 0; i < 4; i++) {
 151 if (grp->grp_cfg.val[i] != ncfg->val[i]) {
 152 bus_space_write_4(bst, grp->grp_bsh,
 153 AWIN_PIO_CFG0_REG + 4 * i, ncfg->val[i]);
 154 grp->grp_cfg.val[i] = ncfg->val[i];
 155 }
 156 }
 157}
 158
 159void
 160awin_gpio_init(void)
 161{
 162 struct awin_gpio_softc * const sc = &awin_gpio_sc;
 163 bus_size_t offset = AWIN_PIO_OFFSET;
 164
 165 printf(" free");
 166 for (u_int i = 0;
 167 i < __arraycount(pin_groups);
 168 i++, offset += AWIN_PIO_GRP_SIZE) {
 169 struct awin_gpio_pin_group * const grp = &pin_groups[i];
 170 bus_space_subregion(sc->sc_bst, awin_core_bsh,
 171 offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
 172
 173 for (u_int j = 0; j < 4; j++) {
 174 grp->grp_cfg.val[j] = bus_space_read_4(sc->sc_bst,
 175 grp->grp_bsh, AWIN_PIO_CFG0_REG + j * 4);
 176 }
 177
 178 for (uint32_t j = 0, mask = 1;
 179 (mask & grp->grp_pin_mask) != 0;
 180 j++, mask <<= 1) {
 181 u_int func = awin_gpio_get_pin_func(&grp->grp_cfg, j);
 182 if (func > AWIN_PIO_FUNC_OUTPUT) {
 183 grp->grp_pin_inuse_mask |= mask;
 184 }
 185 }
 186 printf(" P%c=%d", 'A' + i,
 187 popcount32(grp->grp_pin_mask & ~grp->grp_pin_inuse_mask));
 188 }
 189}
 190
 191bool
 192awin_gpio_pinset_available(const struct awin_gpio_pinset *req)
 193{
 194 KASSERT(req != NULL);
 195
 196 if (!req->pinset_group)
 197 return false;
 198
 199 KASSERT('A' <= req->pinset_group && req->pinset_group <= 'I');
 200
 201 struct awin_gpio_pin_group * const grp =
 202 &pin_groups[req->pinset_group - 'A'];
 203
 204 /*
 205 * If there are unconnected pins, then they've been remove from
 206 * the groups pin mask. If we want pins that are unconnected,
 207 * fail the request.
 208 */
 209 if (req->pinset_mask & ~grp->grp_pin_mask)
 210 return false;
 211
 212 /*
 213 * If none of the pins are in use, they must be available.
 214 */
 215 if (req->pinset_mask & ~grp->grp_pin_inuse_mask)
 216 return true;
 217
 218 /*
 219 * Check to see if the pins are already setup for this function.
 220 */
 221 for (uint32_t j = 0, inuse = req->pinset_mask & grp->grp_pin_inuse_mask;
 222 inuse != 0;
 223 j++, inuse >>= 1) {
 224 const u_int n = ffs(inuse) - 1;
 225 j += n;
 226 inuse >>= n;
 227 /*
 228 * If this pin is in use but it's for a different
 229 * function, fail the request.
 230 */
 231 if (awin_gpio_get_pin_func(&grp->grp_cfg, j) != req->pinset_func)
 232 return false;
 233 }
 234
 235 /*
 236 * Nothing incompatible encountered so the pins must be available.
 237 */
 238 return true;
 239}
 240
 241void
 242awin_gpio_pinset_acquire(const struct awin_gpio_pinset *req)
 243{
 244 KASSERT(awin_gpio_pinset_available(req));
 245
 246 struct awin_gpio_pin_group * const grp =
 247 &pin_groups[req->pinset_group - 'A'];
 248
 249
 250 /*
 251 * If all the pins already have right function, just return.
 252 */
 253 if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) {
 254 return;
 255 }
 256
 257 /*
 258 * Copy the current config.
 259 */
 260 struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
 261
 262 /*
 263 * For each pin not inuse, update the cloned config's function for it.
 264 */
 265 for (uint32_t j = 0, todo = req->pinset_mask & ~grp->grp_pin_inuse_mask;
 266 todo != 0;
 267 j++, todo >>= 1) {
 268 const u_int n = ffs(todo) - 1;
 269 j += n;
 270 todo >>= n;
 271 /*
 272 * Change the function of this pin.
 273 */
 274 awin_gpio_set_pin_func(&ncfg, j, req->pinset_func);
 275 }
 276
 277 /*
 278 * Now update any config register that changed.
 279 */
 280 awin_gpio_update_cfg_regs(&awin_bs_tag, grp, &ncfg);
 281
 282 /*
 283 * Mark all these pins as in use.
 284 */
 285 grp->grp_pin_inuse_mask |= req->pinset_mask;
 286}
 287
 288void
 289awin_gpio_pinset_release(const struct awin_gpio_pinset *req)
 290{
 291 KASSERT(awin_gpio_pinset_available(req));
 292
 293 struct awin_gpio_pin_group * const grp =
 294 &pin_groups[req->pinset_group - 'A'];
 295
 296#if 0
 297 /*
 298 * Copy the current config.
 299 */
 300 struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
 301
 302 /*
 303 * For each pin not inuse, update the cloned config's function for it.
 304 */
 305 for (uint32_t j = 0, todo = req->pinset_mask;
 306 todo != 0;
 307 j++, todo >>= 1) {
 308 const u_int n = ffs(todo) - 1;
 309 j += n;
 310 todo >>= n;
 311 /*
 312 * Change the function of this pin.
 313 */
 314 awin_gpio_set_pin_func(&ncfg, AWIN_PIO_FUNC_INPUT);
 315 }
 316
 317 /*
 318 * Now update any config register that changed.
 319 */
 320 awin_gpio_update_cfg_regs(sc->sc_bst, grp, &ncfg);
 321#endif
 322
 323 /*
 324 * Clear these pins as being in use.
 325 */
 326 grp->grp_pin_inuse_mask &= ~req->pinset_mask;
 327}
cvs diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/Attic/awin_io.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_io.c 2013/09/04 02:39:01 1.1
+++ src/sys/arch/arm/allwinner/Attic/awin_io.c 2013/09/07 00:35:52 1.2
@@ -21,48 +21,49 @@ @@ -21,48 +21,49 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.1 2013/09/04 02:39:01 matt Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
35 35
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/cpu.h> 37#include <sys/cpu.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/intr.h> 39#include <sys/intr.h>
40#include <sys/systm.h> 40#include <sys/systm.h>
41 41
42#include <arm/locore.h> 42#include <arm/locore.h>
43#include <arm/mainbus/mainbus.h> 43#include <arm/mainbus/mainbus.h>
44 44
45#include <arm/allwinner/awin_reg.h> 45#include <arm/allwinner/awin_reg.h>
46#include <arm/allwinner/awin_var.h> 46#include <arm/allwinner/awin_var.h>
47 47
48static int awinio_match(device_t, cfdata_t, void *); 48static int awinio_match(device_t, cfdata_t, void *);
49static void awinio_attach(device_t, device_t, void *); 49static void awinio_attach(device_t, device_t, void *);
50 50
51static struct awinio_softc { 51static struct awinio_softc {
52 device_t sc_dev; 52 device_t sc_dev;
53 bus_space_tag_t sc_bst; 53 bus_space_tag_t sc_bst;
54 bus_space_tag_t sc_a4x_bst; 54 bus_space_tag_t sc_a4x_bst;
55 bus_space_handle_t sc_bsh; 55 bus_space_handle_t sc_bsh;
 56 bus_space_handle_t sc_ccm_bsh;
56 bus_dma_tag_t sc_dmat; 57 bus_dma_tag_t sc_dmat;
57} awinio_sc; 58} awinio_sc;
58 59
59CFATTACH_DECL_NEW(awin_io, 0, 60CFATTACH_DECL_NEW(awin_io, 0,
60 awinio_match, awinio_attach, NULL, NULL); 61 awinio_match, awinio_attach, NULL, NULL);
61 62
62static int 63static int
63awinio_match(device_t parent, cfdata_t cf, void *aux) 64awinio_match(device_t parent, cfdata_t cf, void *aux)
64{ 65{
65 if (awinio_sc.sc_dev != NULL) 66 if (awinio_sc.sc_dev != NULL)
66 return 0; 67 return 0;
67 68
68 return 1; 69 return 1;
@@ -89,32 +90,33 @@ awinio_print(void *aux, const char *pnp) @@ -89,32 +90,33 @@ awinio_print(void *aux, const char *pnp)
89 90
90static const struct awin_locators awin_locators[] = { 91static const struct awin_locators awin_locators[] = {
91 { "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ }, 92 { "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ },
92 { "awintmr", OFFANDSIZE(TMR), NOPORT, AWIN_IRQ_TMR0, A10 }, 93 { "awintmr", OFFANDSIZE(TMR), NOPORT, AWIN_IRQ_TMR0, A10 },
93 { "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, AANY }, 94 { "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, AANY },
94 { "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, AANY }, 95 { "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, AANY },
95 { "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, AANY }, 96 { "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, AANY },
96 { "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, AANY }, 97 { "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, AANY },
97 { "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, AANY }, 98 { "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, AANY },
98 { "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, AANY }, 99 { "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, AANY },
99 { "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, AANY }, 100 { "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, AANY },
100 { "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, AANY }, 101 { "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, AANY },
101 { "awinwdt", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY }, 102 { "awinwdt", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY },
102 { "awinusb", OFFANDSIZE(USB1), 0, AWIN_IRQ_USB1, AANY }, 103 { "awinusb", OFFANDSIZE(USB1), 0, NOINTR, AANY },
103 { "awinusb", OFFANDSIZE(USB2), 1, AWIN_IRQ_USB2, AANY }, 104 { "awinusb", OFFANDSIZE(USB2), 1, NOINTR, AANY },
104 { "sdhc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, AANY }, 105 { "sdhc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, AANY },
105 { "sdhc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, AANY }, 106 { "sdhc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, AANY },
106 { "sdhc", OFFANDSIZE(SDMMC2), 2, AWIN_IRQ_SDMMC2, AANY }, 107 { "sdhc", OFFANDSIZE(SDMMC2), 2, AWIN_IRQ_SDMMC2, AANY },
107 { "sdhc", OFFANDSIZE(SDMMC3), 3, AWIN_IRQ_SDMMC3, AANY }, 108 { "sdhc", OFFANDSIZE(SDMMC3), 3, AWIN_IRQ_SDMMC3, AANY },
 109 { "sdhc", OFFANDSIZE(SDMMC1), 4, AWIN_IRQ_SDMMC1, AANY },
108 { "ahcisata", OFFANDSIZE(SATA), NOPORT, AWIN_IRQ_SATA, AANY }, 110 { "ahcisata", OFFANDSIZE(SATA), NOPORT, AWIN_IRQ_SATA, AANY },
109 { "twi", OFFANDSIZE(TWI0), 0, AWIN_IRQ_TWI0, AANY }, 111 { "twi", OFFANDSIZE(TWI0), 0, AWIN_IRQ_TWI0, AANY },
110 { "twi", OFFANDSIZE(TWI1), 1, AWIN_IRQ_TWI1, AANY }, 112 { "twi", OFFANDSIZE(TWI1), 1, AWIN_IRQ_TWI1, AANY },
111 { "twi", OFFANDSIZE(TWI2), 2, AWIN_IRQ_TWI2, AANY }, 113 { "twi", OFFANDSIZE(TWI2), 2, AWIN_IRQ_TWI2, AANY },
112 { "twi", OFFANDSIZE(TWI3), 3, AWIN_IRQ_TWI3, AANY }, 114 { "twi", OFFANDSIZE(TWI3), 3, AWIN_IRQ_TWI3, AANY },
113 { "twi", OFFANDSIZE(TWI4), 4, AWIN_IRQ_TWI4, AANY }, 115 { "twi", OFFANDSIZE(TWI4), 4, AWIN_IRQ_TWI4, AANY },
114 { "spi", OFFANDSIZE(SPI0), 0, AWIN_IRQ_SPI0, AANY }, 116 { "spi", OFFANDSIZE(SPI0), 0, AWIN_IRQ_SPI0, AANY },
115 { "spi", OFFANDSIZE(SPI1), 1, AWIN_IRQ_SPI1, AANY }, 117 { "spi", OFFANDSIZE(SPI1), 1, AWIN_IRQ_SPI1, AANY },
116 { "spi", OFFANDSIZE(SPI2), 1, AWIN_IRQ_SPI2, AANY }, 118 { "spi", OFFANDSIZE(SPI2), 1, AWIN_IRQ_SPI2, AANY },
117 { "spi", OFFANDSIZE(SPI3), 3, AWIN_IRQ_SPI3, AANY }, 119 { "spi", OFFANDSIZE(SPI3), 3, AWIN_IRQ_SPI3, AANY },
118 { "awinfe", OFFANDSIZE(EMAC), NOPORT, AWIN_IRQ_EMAC, AANY }, 120 { "awinfe", OFFANDSIZE(EMAC), NOPORT, AWIN_IRQ_EMAC, AANY },
119 { "awinge", AWIN_GMAC_OFFSET, AWIN_GMAC_SIZE, NOPORT, AWIN_IRQ_GMAC, A20 }, 121 { "awinge", AWIN_GMAC_OFFSET, AWIN_GMAC_SIZE, NOPORT, AWIN_IRQ_GMAC, A20 },
120 { "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY }, 122 { "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY },
@@ -138,43 +140,47 @@ static void @@ -138,43 +140,47 @@ static void
138awinio_attach(device_t parent, device_t self, void *aux) 140awinio_attach(device_t parent, device_t self, void *aux)
139{ 141{
140 struct awinio_softc * const sc = &awinio_sc; 142 struct awinio_softc * const sc = &awinio_sc;
141 const bool a10_p = CPU_ID_CORTEX_A8_P(curcpu()->ci_arm_cpuid); 143 const bool a10_p = CPU_ID_CORTEX_A8_P(curcpu()->ci_arm_cpuid);
142 const bool a20_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid); 144 const bool a20_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid);
143 145
144 sc->sc_dev = self; 146 sc->sc_dev = self;
145 147
146 sc->sc_bst = &awin_bs_tag; 148 sc->sc_bst = &awin_bs_tag;
147 sc->sc_a4x_bst = &awin_a4x_bs_tag; 149 sc->sc_a4x_bst = &awin_a4x_bs_tag;
148 sc->sc_bsh = awin_core_bsh; 150 sc->sc_bsh = awin_core_bsh;
149 sc->sc_dmat = &awin_dma_tag; 151 sc->sc_dmat = &awin_dma_tag;
150 152
 153 bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET, 0x1000,
 154 &sc->sc_ccm_bsh);
 155
151 aprint_naive("\n"); 156 aprint_naive("\n");
152 aprint_normal("\n"); 157 aprint_normal("\n");
153 158
154 const struct awin_locators * const eloc = 159 const struct awin_locators * const eloc =
155 awin_locators + __arraycount(awin_locators); 160 awin_locators + __arraycount(awin_locators);
156 for (const struct awin_locators *loc = awin_locators; loc < eloc; loc++) { 161 for (const struct awin_locators *loc = awin_locators; loc < eloc; loc++) {
157 if (loc->loc_flags & AWINIO_ONLY) { 162 if (loc->loc_flags & AWINIO_ONLY) {
158 if (a10_p && !(loc->loc_flags & AWINIO_ONLY_A10)) 163 if (a10_p && !(loc->loc_flags & AWINIO_ONLY_A10))
159 continue; 164 continue;
160 if (a20_p && !(loc->loc_flags & AWINIO_ONLY_A20)) 165 if (a20_p && !(loc->loc_flags & AWINIO_ONLY_A20))
161 continue; 166 continue;
162 } 167 }
163 struct awinio_attach_args aio = { 168 struct awinio_attach_args aio = {
164 .aio_loc = *loc, 169 .aio_loc = *loc,
165 .aio_core_bst = sc->sc_bst, 170 .aio_core_bst = sc->sc_bst,
166 .aio_core_a4x_bst = sc->sc_a4x_bst, 171 .aio_core_a4x_bst = sc->sc_a4x_bst,
167 .aio_core_bsh = sc->sc_bsh, 172 .aio_core_bsh = sc->sc_bsh,
 173 .aio_ccm_bsh = sc->sc_ccm_bsh,
168 .aio_dmat = sc->sc_dmat, 174 .aio_dmat = sc->sc_dmat,
169 }; 175 };
170 cfdata_t cf = config_search_ia(awinio_find, 176 cfdata_t cf = config_search_ia(awinio_find,
171 sc->sc_dev, "awinio", &aio); 177 sc->sc_dev, "awinio", &aio);
172 if (cf == NULL) { 178 if (cf == NULL) {
173 if (loc->loc_flags & AWINIO_REQUIRED) 179 if (loc->loc_flags & AWINIO_REQUIRED)
174 panic("%s: failed to find %s!", __func__, 180 panic("%s: failed to find %s!", __func__,
175 loc->loc_name); 181 loc->loc_name);
176 continue; 182 continue;
177 } 183 }
178 config_attach(sc->sc_dev, cf, &aio, awinio_print); 184 config_attach(sc->sc_dev, cf, &aio, awinio_print);
179 } 185 }
180} 186}
cvs diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/Attic/awin_twi.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_twi.c 2013/09/04 02:39:01 1.1
+++ src/sys/arch/arm/allwinner/Attic/awin_twi.c 2013/09/07 00:35:52 1.2
@@ -21,67 +21,114 @@ @@ -21,67 +21,114 @@
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "locators.h" 30#include "locators.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33 33
34__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.1 2013/09/04 02:39:01 matt Exp $"); 34__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
35 35
36#include <sys/bus.h> 36#include <sys/bus.h>
37#include <sys/device.h> 37#include <sys/device.h>
38#include <sys/intr.h> 38#include <sys/intr.h>
39#include <sys/systm.h> 39#include <sys/systm.h>
40 40
 41#include <dev/i2c/i2cvar.h>
 42#include <dev/i2c/gttwsivar.h>
 43
41#include <arm/allwinner/awin_reg.h> 44#include <arm/allwinner/awin_reg.h>
42#include <arm/allwinner/awin_var.h> 45#include <arm/allwinner/awin_var.h>
43 46
44static int awin_twi_match(device_t, cfdata_t, void *); 47static int awin_twi_match(device_t, cfdata_t, void *);
45static void awin_twi_attach(device_t, device_t, void *); 48static void awin_twi_attach(device_t, device_t, void *);
46 49
47struct awin_twi_softc { 50struct awin_twi_softc {
48 device_t sc_dev; 51 struct gttwsi_softc asc_sc;
49 bus_space_tag_t sc_bst; 52 void *asc_ih;
50 bus_space_handle_t sc_bsh; 53};
51 bus_dma_tag_t sc_dmat; 54
 55static int awin_twi_ports;
 56
 57static const struct awin_gpio_pinset awin_twi_pinsets[] = {
 58 [0] = { 'B', AWIN_PIO_PB_TWI0_FUNC, AWIN_PIO_PB_TWI0_PINS },
 59 [1] = { 'B', AWIN_PIO_PB_TWI1_FUNC, AWIN_PIO_PB_TWI1_PINS },
 60 [2] = { 'B', AWIN_PIO_PB_TWI2_FUNC, AWIN_PIO_PB_TWI2_PINS },
 61 [3] = { 'I', AWIN_PIO_PI_TWI3_FUNC, AWIN_PIO_PI_TWI3_PINS },
 62 [4] = { 'I', AWIN_PIO_PI_TWI4_FUNC, AWIN_PIO_PI_TWI4_PINS },
52}; 63};
53 64
54CFATTACH_DECL_NEW(awin_twi, sizeof(struct awin_twi_softc), 65CFATTACH_DECL_NEW(awin_twi, sizeof(struct awin_twi_softc),
55 awin_twi_match, awin_twi_attach, NULL, NULL); 66 awin_twi_match, awin_twi_attach, NULL, NULL);
56 67
57static int 68static int
58awin_twi_match(device_t parent, cfdata_t cf, void *aux) 69awin_twi_match(device_t parent, cfdata_t cf, void *aux)
59{ 70{
60 struct awinio_attach_args * const aio = aux; 71 struct awinio_attach_args * const aio = aux;
61 const struct awin_locators * const loc = &aio->aio_loc; 72 const struct awin_locators * const loc = &aio->aio_loc;
62 73
63 if (strcmp(cf->cf_name, loc->loc_name)) 74 KASSERT(!strcmp(cf->cf_name, loc->loc_name));
 75 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
 76 || cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
 77 KASSERT((awin_twi_ports & __BIT(loc->loc_port)) == 0);
 78
 79 /*
 80 * We don't have alternative mappings so if one is requested
 81 * fail the match.
 82 */
 83 if (cf->cf_flags & 1)
64 return 0; 84 return 0;
65 85
66 KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT); 86 if (!awin_gpio_pinset_available(&awin_twi_pinsets[loc->loc_port]))
 87 return 0;
67 88
68 return 1; 89 return 1;
69} 90}
70 91
71static void 92static void
72awin_twi_attach(device_t parent, device_t self, void *aux) 93awin_twi_attach(device_t parent, device_t self, void *aux)
73{ 94{
74 struct awin_twi_softc * const sc = device_private(self); 95 struct awin_twi_softc * const asc = device_private(self);
75 struct awinio_attach_args * const aio = aux; 96 struct awinio_attach_args * const aio = aux;
76 const struct awin_locators * const loc = &aio->aio_loc; 97 const struct awin_locators * const loc = &aio->aio_loc;
 98 bus_space_handle_t bsh;
77 99
78 sc->sc_dev = self; 100 awin_twi_ports |= __BIT(loc->loc_port);
79 
80 sc->sc_bst = aio->aio_core_bst; 
81 sc->sc_dmat = aio->aio_dmat; 
82 bus_space_subregion(sc->sc_bst, aio->aio_core_bsh, 
83 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 
84 101
85 aprint_naive("\n"); 102 /*
86 aprint_normal("\n"); 103 * Acquite the PIO pins needed for the TWI port.
 104 */
 105 awin_gpio_pinset_acquire(&awin_twi_pinsets[loc->loc_port]);
 106
 107 /*
 108 * Get a bus space handle for this TWI port.
 109 */
 110 bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
 111 loc->loc_offset, loc->loc_size, &bsh);
 112
 113 /*
 114 * Do the MI attach
 115 */
 116 gttwsi_attach_subr(self, aio->aio_core_bst, bsh);
 117
 118 /*
 119 * Establish interrupt for it
 120 */
 121 asc->asc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
 122 gttwsi_intr, &asc->asc_sc);
 123 if (asc->asc_ih == NULL) {
 124 aprint_error_dev(self, "failed to establish interrupt %d\n",
 125 loc->loc_intr);
 126 return;
 127 }
 128 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
 129
 130 /*
 131 * Configure its children
 132 */
 133 gttwsi_config_children(self);
87} 134}
cvs diff -r1.1 -r1.2 src/sys/arch/arm/allwinner/Attic/awin_usb.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_usb.c 2013/09/04 02:39:01 1.1
+++ src/sys/arch/arm/allwinner/Attic/awin_usb.c 2013/09/07 00:35:52 1.2
@@ -22,27 +22,27 @@ @@ -22,27 +22,27 @@
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29#define USBH_PRIVATE 29#define USBH_PRIVATE
30 30
31#include "locators.h" 31#include "locators.h"
32 32
33#include <sys/cdefs.h> 33#include <sys/cdefs.h>
34 34
35__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.1 2013/09/04 02:39:01 matt Exp $"); 35__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
36 36
37#include <sys/bus.h> 37#include <sys/bus.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/intr.h> 39#include <sys/intr.h>
40#include <sys/systm.h> 40#include <sys/systm.h>
41 41
42#include <arm/allwinner/awin_reg.h> 42#include <arm/allwinner/awin_reg.h>
43#include <arm/allwinner/awin_var.h> 43#include <arm/allwinner/awin_var.h>
44 44
45#include <dev/usb/usb.h> 45#include <dev/usb/usb.h>
46#include <dev/usb/usbdi.h> 46#include <dev/usb/usbdi.h>
47#include <dev/usb/usbdivar.h> 47#include <dev/usb/usbdivar.h>
48#include <dev/usb/usb_mem.h> 48#include <dev/usb/usb_mem.h>
@@ -54,39 +54,43 @@ __KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v @@ -54,39 +54,43 @@ __KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v
54#include <dev/usb/ehcivar.h> 54#include <dev/usb/ehcivar.h>
55 55
56#include <dev/pci/pcidevs.h> 56#include <dev/pci/pcidevs.h>
57 57
58struct awinusb_softc { 58struct awinusb_softc {
59 device_t usbsc_dev; 59 device_t usbsc_dev;
60 bus_dma_tag_t usbsc_dmat; 60 bus_dma_tag_t usbsc_dmat;
61 bus_space_tag_t usbsc_bst; 61 bus_space_tag_t usbsc_bst;
62 bus_space_handle_t usbsc_ehci_bsh; 62 bus_space_handle_t usbsc_ehci_bsh;
63 bus_space_handle_t usbsc_ohci_bsh; 63 bus_space_handle_t usbsc_ohci_bsh;
64 64
65 device_t usbsc_ohci_dev; 65 device_t usbsc_ohci_dev;
66 device_t usbsc_ehci_dev; 66 device_t usbsc_ehci_dev;
67 void *usbsc_ohci_sc; 67 void *usbsc_ohci_ih;
68 void *usbsc_ehci_sc; 68 void *usbsc_ehci_ih;
69 void *usbsc_ih; 
70}; 69};
71 70
72struct awinusb_attach_args { 71struct awinusb_attach_args {
73 const char *usbaa_name; 72 const char *usbaa_name;
74 bus_dma_tag_t usbaa_dmat; 73 bus_dma_tag_t usbaa_dmat;
75 bus_space_tag_t usbaa_bst; 74 bus_space_tag_t usbaa_bst;
76 bus_space_handle_t usbaa_bsh; 75 bus_space_handle_t usbaa_bsh;
 76 bus_space_handle_t usbaa_ccm_bsh;
77 bus_size_t usbaa_size; 77 bus_size_t usbaa_size;
 78 int usbaa_port;
78}; 79};
79 80
 81static const int awinusb_ohci_irqs[2] = { AWIN_IRQ_USB3, AWIN_IRQ_USB4 };
 82static const int awinusb_ehci_irqs[2] = { AWIN_IRQ_USB1, AWIN_IRQ_USB2 };
 83
80#ifdef OHCI_DEBUG 84#ifdef OHCI_DEBUG
81#define OHCI_DPRINTF(x) if (ohcidebug) printf x 85#define OHCI_DPRINTF(x) if (ohcidebug) printf x
82extern int ohcidebug; 86extern int ohcidebug;
83#else 87#else
84#define OHCI_DPRINTF(x) 88#define OHCI_DPRINTF(x)
85#endif 89#endif
86 90
87static int ohci_awinusb_match(device_t, cfdata_t, void *); 91static int ohci_awinusb_match(device_t, cfdata_t, void *);
88static void ohci_awinusb_attach(device_t, device_t, void *); 92static void ohci_awinusb_attach(device_t, device_t, void *);
89 93
90CFATTACH_DECL_NEW(ohci_awinusb, sizeof(struct ohci_softc), 94CFATTACH_DECL_NEW(ohci_awinusb, sizeof(struct ohci_softc),
91 ohci_awinusb_match, ohci_awinusb_attach, NULL, NULL); 95 ohci_awinusb_match, ohci_awinusb_attach, NULL, NULL);
92 96
@@ -94,50 +98,66 @@ static int @@ -94,50 +98,66 @@ static int
94ohci_awinusb_match(device_t parent, cfdata_t cf, void *aux) 98ohci_awinusb_match(device_t parent, cfdata_t cf, void *aux)
95{ 99{
96 struct awinusb_attach_args * const usbaa = aux; 100 struct awinusb_attach_args * const usbaa = aux;
97 101
98 if (strcmp(cf->cf_name, usbaa->usbaa_name)) 102 if (strcmp(cf->cf_name, usbaa->usbaa_name))
99 return 0; 103 return 0;
100 104
101 return 1; 105 return 1;
102} 106}
103 107
104static void 108static void
105ohci_awinusb_attach(device_t parent, device_t self, void *aux) 109ohci_awinusb_attach(device_t parent, device_t self, void *aux)
106{ 110{
 111 struct awinusb_softc * const usbsc = device_private(parent);
107 struct ohci_softc * const sc = device_private(self); 112 struct ohci_softc * const sc = device_private(self);
108 struct awinusb_attach_args * const usbaa = aux; 113 struct awinusb_attach_args * const usbaa = aux;
109 114
110 sc->sc_dev = self; 115 sc->sc_dev = self;
111 116
 117#if 0
 118 awinusb_enable(usbaa->usbaa_bst, usbaa->usbaa_ccm_bsh,
 119 AWIN_USB_CLK_USBPHY1_RST, AWIN_APB_GATING1_OHCI0);
 120#endif
 121
112 sc->iot = usbaa->usbaa_bst; 122 sc->iot = usbaa->usbaa_bst;
113 sc->ioh = usbaa->usbaa_bsh; 123 sc->ioh = usbaa->usbaa_bsh;
114 sc->sc_size = usbaa->usbaa_size; 124 sc->sc_size = usbaa->usbaa_size;
115 sc->sc_bus.dmatag = usbaa->usbaa_dmat; 125 sc->sc_bus.dmatag = usbaa->usbaa_dmat;
116 sc->sc_bus.hci_private = sc; 126 sc->sc_bus.hci_private = sc;
117 127
118 //sc->sc_id_vendor = PCI_VENDOR_ALLWINNER; 128 //sc->sc_id_vendor = PCI_VENDOR_ALLWINNER;
119 strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor)); 129 strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor));
120 130
121 aprint_naive(": OHCI USB controller\n"); 131 aprint_naive(": OHCI USB controller\n");
122 aprint_normal(": OHCI USB controller\n"); 132 aprint_normal(": OHCI USB controller\n");
123 133
124 int error = ohci_init(sc); 134 int error = ohci_init(sc);
125 if (error != USBD_NORMAL_COMPLETION) { 135 if (error != USBD_NORMAL_COMPLETION) {
126 aprint_error_dev(self, "init failed, error=%d\n", error); 136 aprint_error_dev(self, "init failed, error=%d\n", error);
127 } else { 137 } else {
128 /* Attach usb device. */ 138 /* Attach usb device. */
129 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 139 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
130 } 140 }
 141
 142 const int irq = awinusb_ohci_irqs[usbaa->usbaa_port];
 143 usbsc->usbsc_ohci_ih = intr_establish(irq, IPL_USB,
 144 IST_LEVEL, ohci_intr, sc);
 145 if (usbsc->usbsc_ohci_ih == NULL) {
 146 aprint_error_dev(self, "failed to establish interrupt %d\n",
 147 irq);
 148 return;
 149 }
 150 aprint_normal_dev(self, "interrupting on irq %d\n", irq);
131} 151}
132 152
133#ifdef EHCI_DEBUG 153#ifdef EHCI_DEBUG
134#define EHCI_DPRINTF(x) if (ehcidebug) printf x 154#define EHCI_DPRINTF(x) if (ehcidebug) printf x
135extern int ehcidebug; 155extern int ehcidebug;
136#else 156#else
137#define EHCI_DPRINTF(x) 157#define EHCI_DPRINTF(x)
138#endif 158#endif
139 159
140static int ehci_awinusb_match(device_t, cfdata_t, void *); 160static int ehci_awinusb_match(device_t, cfdata_t, void *);
141static void ehci_awinusb_attach(device_t, device_t, void *); 161static void ehci_awinusb_attach(device_t, device_t, void *);
142 162
143CFATTACH_DECL_NEW(ehci_awinusb, sizeof(struct ehci_softc), 163CFATTACH_DECL_NEW(ehci_awinusb, sizeof(struct ehci_softc),
@@ -177,44 +197,36 @@ ehci_awinusb_attach(device_t parent, dev @@ -177,44 +197,36 @@ ehci_awinusb_attach(device_t parent, dev
177 //sc->sc_id_vendor = PCI_VENDOR_ALLWINNER; 197 //sc->sc_id_vendor = PCI_VENDOR_ALLWINNER;
178 strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor)); 198 strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor));
179 199
180 aprint_naive(": EHCI USB controller\n"); 200 aprint_naive(": EHCI USB controller\n");
181 aprint_normal(": ECHI USB controller\n"); 201 aprint_normal(": ECHI USB controller\n");
182 202
183 int error = ehci_init(sc); 203 int error = ehci_init(sc);
184 if (error != USBD_NORMAL_COMPLETION) { 204 if (error != USBD_NORMAL_COMPLETION) {
185 aprint_error_dev(self, "init failed, error=%d\n", error); 205 aprint_error_dev(self, "init failed, error=%d\n", error);
186 } else { 206 } else {
187 /* Attach usb device. */ 207 /* Attach usb device. */
188 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 208 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
189 } 209 }
190} 
191 210
192/* 211 const int irq = awinusb_ehci_irqs[usbaa->usbaa_port];
193 * There's only IRQ shared between both OCHI and EHCI devices. 212 usbsc->usbsc_ehci_ih = intr_establish(irq, IPL_USB,
194 */ 213 IST_LEVEL, ehci_intr, sc);
195static int 214 if (usbsc->usbsc_ehci_ih == NULL) {
196awinusb_intr(void *arg) 215 aprint_error_dev(self, "failed to establish interrupt %d\n",
197{ 216 irq);
198 struct awinusb_softc * const usbsc = arg; 217 return;
199 int rv0 = 0, rv1 = 0; 218 }
200 219 aprint_normal_dev(self, "interrupting on irq %d\n", irq);
201 if (usbsc->usbsc_ohci_sc) 
202 rv0 = ohci_intr(usbsc->usbsc_ohci_sc); 
203 
204 if (usbsc->usbsc_ehci_sc) 
205 rv1 = ehci_intr(usbsc->usbsc_ehci_sc); 
206 
207 return rv0 ? rv0 : rv1; 
208} 220}
209 221
210static int awinusb_match(device_t, cfdata_t, void *); 222static int awinusb_match(device_t, cfdata_t, void *);
211static void awinusb_attach(device_t, device_t, void *); 223static void awinusb_attach(device_t, device_t, void *);
212 224
213CFATTACH_DECL_NEW(awin_usb, sizeof(struct awinusb_softc), 225CFATTACH_DECL_NEW(awin_usb, sizeof(struct awinusb_softc),
214 awinusb_match, awinusb_attach, NULL, NULL); 226 awinusb_match, awinusb_attach, NULL, NULL);
215 227
216static int awinusb_ports; 228static int awinusb_ports;
217 229
218int 230int
219awinusb_match(device_t parent, cfdata_t cf, void *aux) 231awinusb_match(device_t parent, cfdata_t cf, void *aux)
220{ 232{
@@ -247,65 +259,61 @@ awinusb_attach(device_t parent, device_t @@ -247,65 +259,61 @@ awinusb_attach(device_t parent, device_t
247 usbsc->usbsc_dmat = aio->aio_dmat; 259 usbsc->usbsc_dmat = aio->aio_dmat;
248 260
249 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh, 261 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh,
250 loc->loc_offset + AWIN_EHCI_OFFSET, AWIN_EHCI_SIZE, 262 loc->loc_offset + AWIN_EHCI_OFFSET, AWIN_EHCI_SIZE,
251 &usbsc->usbsc_ehci_bsh); 263 &usbsc->usbsc_ehci_bsh);
252 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh, 264 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh,
253 loc->loc_offset + AWIN_OHCI_OFFSET, AWIN_OHCI_SIZE, 265 loc->loc_offset + AWIN_OHCI_OFFSET, AWIN_OHCI_SIZE,
254 &usbsc->usbsc_ohci_bsh); 266 &usbsc->usbsc_ohci_bsh);
255 267
256#if 0 268#if 0
257 /* 269 /*
258 * Bring the PHYs out of reset. 270 * Bring the PHYs out of reset.
259 */ 271 */
260 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh, 272 uint32_t v = bus_space_read_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
 273 AWIN_USB_CLK_REG);
 274
 275 v &= ~(loc->loc_port == 0 ? AWIN_USB_CLK_PHY1_RST : AWIN_USB_CLK_PHY2_RST);
 276 bus_space_write_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
261 USBH_PHY_CTRL_P0, USBH_PHY_CTRL_INIT); 277 USBH_PHY_CTRL_P0, USBH_PHY_CTRL_INIT);
262 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh, 278 bus_space_write_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
263 USBH_PHY_CTRL_P1, USBH_PHY_CTRL_INIT); 279 USBH_PHY_CTRL_P1, USBH_PHY_CTRL_INIT);
264#endif 280#endif
265 281
266 /* 282 /*
267 * Disable interrupts 283 * Disable interrupts
268 */ 284 */
269 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ohci_bsh, 285 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ohci_bsh,
270 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 286 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
271 bus_size_t caplength = bus_space_read_1(usbsc->usbsc_bst, 287 bus_size_t caplength = bus_space_read_1(usbsc->usbsc_bst,
272 usbsc->usbsc_ehci_bsh, EHCI_CAPLENGTH); 288 usbsc->usbsc_ehci_bsh, EHCI_CAPLENGTH);
273 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh, 289 bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh,
274 caplength + EHCI_USBINTR, 0); 290 caplength + EHCI_USBINTR, 0);
275 291
276 aprint_naive("\n"); 292 aprint_naive("\n");
277 aprint_normal("\n"); 293 aprint_normal("\n");
278 294
279 struct awinusb_attach_args usbaa_ohci = { 295 struct awinusb_attach_args usbaa_ohci = {
280 .usbaa_name = "ohci", 296 .usbaa_name = "ohci",
281 .usbaa_dmat = usbsc->usbsc_dmat, 297 .usbaa_dmat = usbsc->usbsc_dmat,
282 .usbaa_bst = usbsc->usbsc_bst, 298 .usbaa_bst = usbsc->usbsc_bst,
283 .usbaa_bsh = usbsc->usbsc_ohci_bsh, 299 .usbaa_bsh = usbsc->usbsc_ohci_bsh,
 300 .usbaa_ccm_bsh = aio->aio_ccm_bsh,
284 .usbaa_size = AWIN_OHCI_SIZE, 301 .usbaa_size = AWIN_OHCI_SIZE,
 302 .usbaa_port = loc->loc_port,
285 }; 303 };
286 304
287 usbsc->usbsc_ohci_dev = config_found(self, &usbaa_ohci, NULL); 305 usbsc->usbsc_ohci_dev = config_found(self, &usbaa_ohci, NULL);
288 if (usbsc->usbsc_ohci_dev != NULL) 
289 usbsc->usbsc_ohci_sc = device_private(usbsc->usbsc_ohci_dev); 
290 306
291 struct awinusb_attach_args usbaa_ehci = { 307 struct awinusb_attach_args usbaa_ehci = {
292 .usbaa_name = "ehci", 308 .usbaa_name = "ehci",
293 .usbaa_dmat = usbsc->usbsc_dmat, 309 .usbaa_dmat = usbsc->usbsc_dmat,
294 .usbaa_bst = usbsc->usbsc_bst, 310 .usbaa_bst = usbsc->usbsc_bst,
295 .usbaa_bsh = usbsc->usbsc_ehci_bsh, 311 .usbaa_bsh = usbsc->usbsc_ehci_bsh,
 312 .usbaa_ccm_bsh = aio->aio_ccm_bsh,
296 .usbaa_size = AWIN_EHCI_SIZE, 313 .usbaa_size = AWIN_EHCI_SIZE,
 314 .usbaa_port = loc->loc_port,
297 }; 315 };
298 316
299 usbsc->usbsc_ehci_dev = config_found(self, &usbaa_ehci, NULL); 317 config_found(self, &usbaa_ehci, NULL);
300 if (usbsc->usbsc_ehci_dev != NULL) 318
301 usbsc->usbsc_ehci_sc = device_private(usbsc->usbsc_ehci_dev); 
302 
303 usbsc->usbsc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL, 
304 awinusb_intr, usbsc); 
305 if (usbsc->usbsc_ih == NULL) { 
306 aprint_error_dev(self, "failed to establish interrupt %d\n", 
307 loc->loc_intr); 
308 return; 
309 } 
310 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 
311} 319}
cvs diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/Attic/awin_reg.h (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_reg.h 2013/09/04 17:45:40 1.3
+++ src/sys/arch/arm/allwinner/Attic/awin_reg.h 2013/09/07 00:35:52 1.4
@@ -24,359 +24,517 @@ @@ -24,359 +24,517 @@
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#ifndef _ARM_ALLWINNER_AWIN_REG_H 31#ifndef _ARM_ALLWINNER_AWIN_REG_H
32#define _ARM_ALLWINNER_AWIN_REG_H 32#define _ARM_ALLWINNER_AWIN_REG_H
33 33
34#define AWIN_LOSC_FREQ (32*1024) /* 32KHz */ 34#define AWIN_LOSC_FREQ (32*1024) /* 32KHz */
35#define AWIN_REF_FREQ (24*1000*1000) /* 24MHz */ 35#define AWIN_REF_FREQ (24*1000*1000) /* 24MHz */
36 36
37#define AWIN_CPUBIST_PBASE 0x3f501000 37#define AWIN_CPUBIST_PBASE 0x3F501000
38#define AWIN_CPUBIST_SIZE 0x00001000 38#define AWIN_CPUBIST_SIZE 0x00001000
39#define AWIN_SRAM_PBASE 0x00000000 39#define AWIN_SRAM_PBASE 0x00000000
40#define AWIN_SRAM_SIZE 0x00100000 /* round to 1MB */ 40#define AWIN_SRAM_SIZE 0x00100000 /* round to 1MB */
41#define AWIN_SRAMA1_PBASE 0x00000000 41#define AWIN_SRAMA1_PBASE 0x00000000
42#define AWIN_SRAMA1_SIZE 0x00004000 42#define AWIN_SRAMA1_SIZE 0x00004000
43#define AWIN_SRAMA2_PBASE 0x00004000 43#define AWIN_SRAMA2_PBASE 0x00004000
44#define AWIN_SRAMA2_SIZE 0x00004000 44#define AWIN_SRAMA2_SIZE 0x00004000
45#define AWIN_SRAMA3_PBASE 0x00008000 45#define AWIN_SRAMA3_PBASE 0x00008000
46#define AWIN_SRAMA3_SIZE 0x00003400 46#define AWIN_SRAMA3_SIZE 0x00003400
47#define AWIN_SRAMA4_PBASE 0x0000b400 47#define AWIN_SRAMA4_PBASE 0x0000B400
48#define AWIN_SRAMA4_SIZE 0x00000c00 48#define AWIN_SRAMA4_SIZE 0x00000C00
49#define AWIN_SRAMD_PBASE 0x00010000 49#define AWIN_SRAMD_PBASE 0x00010000
50#define AWIN_SRAMD_SIZE 0x00001000 50#define AWIN_SRAMD_SIZE 0x00001000
51#define AWIN_SRAMB_PBASE 0x00020000 /* Secure */ 51#define AWIN_SRAMB_PBASE 0x00020000 /* Secure */
52#define AWIN_SRAMB_SIZE 0x00010000 /* Secure */ 52#define AWIN_SRAMB_SIZE 0x00010000 /* Secure */
53 53
54#define AWIN_CORE_PBASE 0x01c00000 54#define AWIN_CORE_PBASE 0x01C00000
55#define AWIN_CORE_SIZE 0x00300000 55#define AWIN_CORE_SIZE 0x00300000
56#define AWIN_SRAM_OFFSET 0x00000000 56#define AWIN_SRAM_OFFSET 0x00000000
57#define AWIN_DRAM_OFFSET 0x00001000 57#define AWIN_DRAM_OFFSET 0x00001000
58#define AWIN_DMA_OFFSET 0x00002000 58#define AWIN_DMA_OFFSET 0x00002000
59#define AWIN_NFC_OFFSET 0x00003000 59#define AWIN_NFC_OFFSET 0x00003000
60#define AWIN_TS_OFFSET 0x00004000 60#define AWIN_TS_OFFSET 0x00004000
61#define AWIN_SPI0_OFFSET 0x00005000 61#define AWIN_SPI0_OFFSET 0x00005000
62#define AWIN_SPI1_OFFSET 0x00006000 62#define AWIN_SPI1_OFFSET 0x00006000
63#define AWIN_MS_OFFSET 0x00007000 63#define AWIN_MS_OFFSET 0x00007000
64#define AWIN_TVD_OFFSET 0x00008000 64#define AWIN_TVD_OFFSET 0x00008000
65#define AWIN_CSI0_OFFSET 0x00009000 65#define AWIN_CSI0_OFFSET 0x00009000
66#define AWIN_TVE0_OFFSET 0x0000a000 66#define AWIN_TVE0_OFFSET 0x0000A000
67#define AWIN_EMAC_OFFSET 0x0000b000 67#define AWIN_EMAC_OFFSET 0x0000B000
68#define AWIN_LCD0_OFFSET 0x0000c000 68#define AWIN_LCD0_OFFSET 0x0000C000
69#define AWIN_LCD1_OFFSET 0x0000d000 69#define AWIN_LCD1_OFFSET 0x0000D000
70#define AWIN_VE_OFFSET 0x0000e000 70#define AWIN_VE_OFFSET 0x0000E000
71#define AWIN_SDMMC0_OFFSET 0x0000f000 71#define AWIN_SDMMC0_OFFSET 0x0000F000
72#define AWIN_SDMMC1_OFFSET 0x00010000 72#define AWIN_SDMMC1_OFFSET 0x00010000
73#define AWIN_SDMMC2_OFFSET 0x00011000 73#define AWIN_SDMMC2_OFFSET 0x00011000
74#define AWIN_SDMMC3_OFFSET 0x00012000 74#define AWIN_SDMMC3_OFFSET 0x00012000
75#define AWIN_USB0_OFFSET 0x00013000 75#define AWIN_USB0_OFFSET 0x00013000
76#define AWIN_USB1_OFFSET 0x00014000 76#define AWIN_USB1_OFFSET 0x00014000
77#define AWIN_SS_OFFSET 0x00015000 77#define AWIN_SS_OFFSET 0x00015000
78#define AWIN_HDMI_OFFSET 0x00016000 78#define AWIN_HDMI_OFFSET 0x00016000
79#define AWIN_SPI2_OFFSET 0x00017000 79#define AWIN_SPI2_OFFSET 0x00017000
80#define AWIN_SATA_OFFSET 0x00018000 /* A20 */ 80#define AWIN_SATA_OFFSET 0x00018000 /* A20 */
81#define AWIN_PATA_OFFSET 0x00019000 /* A10 */ 81#define AWIN_PATA_OFFSET 0x00019000 /* A10 */
82#define AWIN_ACE_OFFSET 0x0001a000 82#define AWIN_ACE_OFFSET 0x0001A000
83#define AWIN_TVE1_OFFSET 0x0001b000 83#define AWIN_TVE1_OFFSET 0x0001B000
84#define AWIN_USB2_OFFSET 0x0001c000 84#define AWIN_USB2_OFFSET 0x0001C000
85#define AWIN_CSI1_OFFSET 0x0001d000 85#define AWIN_CSI1_OFFSET 0x0001D000
86#define AWIN_TZASC_OFFSET 0x0001e000 /* A10 */ 86#define AWIN_TZASC_OFFSET 0x0001E000 /* A10 */
87#define AWIN_SPI3_OFFSET 0x0001f000 87#define AWIN_SPI3_OFFSET 0x0001F000
88#define AWIN_CCM_OFFSET 0x00020000 88#define AWIN_CCM_OFFSET 0x00020000
89#define AWIN_INTC_OFFSET 0x00020400 89#define AWIN_INTC_OFFSET 0x00020400
90#define AWIN_PIO_OFFSET 0x00020800 90#define AWIN_PIO_OFFSET 0x00020800
91#define AWIN_TMR_OFFSET 0x00020c00 91#define AWIN_TMR_OFFSET 0x00020C00
92#define AWIN_SPDIF_OFFSET 0x00021000 /* A20 */ 92#define AWIN_SPDIF_OFFSET 0x00021000 /* A20 */
93#define AWIN_AC97_OFFSET 0x00021400 93#define AWIN_AC97_OFFSET 0x00021400
94#define AWIN_IR0_OFFSET 0x00021800 94#define AWIN_IR0_OFFSET 0x00021800
95#define AWIN_IR1_OFFSET 0x00021c00 95#define AWIN_IR1_OFFSET 0x00021C00
96#define AWIN_IIS0_OFFSET 0x00022000 96#define AWIN_IIS0_OFFSET 0x00022000
97#define AWIN_IIS1_OFFSET 0x00022400 97#define AWIN_IIS1_OFFSET 0x00022400
98#define AWIN_LRADC_OFFSET 0x00022800 98#define AWIN_LRADC_OFFSET 0x00022800
99#define AWIN_ADDA_OFFSET 0x00022c00 99#define AWIN_ADDA_OFFSET 0x00022C00
100#define AWIN_KEYPAD_OFFSET 0x00023000 100#define AWIN_KEYPAD_OFFSET 0x00023000
101#define AWIN_TZPC_OFFSET 0x00023400 /* A10 */ 101#define AWIN_TZPC_OFFSET 0x00023400 /* A10 */
102#define AWIN_SID_OFFSET 0x00023800 102#define AWIN_SID_OFFSET 0x00023800
103#define AWIN_SJTAG_OFFSET 0x00023c00 103#define AWIN_SJTAG_OFFSET 0x00023C00
104#define AWIN__RSVD3_OFFSET 0x00024000 104#define AWIN__RSVD3_OFFSET 0x00024000
105#define AWIN_IIS2_OFFSET 0x00024400 105#define AWIN_IIS2_OFFSET 0x00024400
106#define AWIN__RSVD4_OFFSET 0x00024800 106#define AWIN__RSVD4_OFFSET 0x00024800
107#define AWIN__RSVD5_OFFSET 0x00024c00 107#define AWIN__RSVD5_OFFSET 0x00024C00
108#define AWIN_TP_OFFSET 0x00025000 108#define AWIN_TP_OFFSET 0x00025000
109#define AWIN_PMU_OFFSET 0x00025400 109#define AWIN_PMU_OFFSET 0x00025400
110#define AWIN__RSVD6_OFFSET 0x00025800 110#define AWIN__RSVD6_OFFSET 0x00025800
111#define AWIN_CPUCNF_OFFSET 0x00025c00 111#define AWIN_CPUCNF_OFFSET 0x00025C00
112#define AWIN__RSVD7_OFFSET 0x00026000 112#define AWIN__RSVD7_OFFSET 0x00026000
113#define AWIN__RSVD8_OFFSET 0x00026400 113#define AWIN__RSVD8_OFFSET 0x00026400
114#define AWIN__RSVD9_OFFSET 0x00026800 114#define AWIN__RSVD9_OFFSET 0x00026800
115#define AWIN__RSVD10_OFFSET 0x00026c00 115#define AWIN__RSVD10_OFFSET 0x00026C00
116#define AWIN__RSVD11_OFFSET 0x00027000 116#define AWIN__RSVD11_OFFSET 0x00027000
117#define AWIN__RSVD12_OFFSET 0x00027400 117#define AWIN__RSVD12_OFFSET 0x00027400
118#define AWIN__RSVD13_OFFSET 0x00027800 118#define AWIN__RSVD13_OFFSET 0x00027800
119#define AWIN__RSVD14_OFFSET 0x00027c00 119#define AWIN__RSVD14_OFFSET 0x00027C00
120#define AWIN_UART_FREQ AWIN_REF_FREQ /* 24MHz */ 120#define AWIN_UART_FREQ AWIN_REF_FREQ /* 24MHz */
121#define AWIN_UART_SIZE 0x00000100 121#define AWIN_UART_SIZE 0x00000100
122#define AWIN_UART0_OFFSET 0x00028000 122#define AWIN_UART0_OFFSET 0x00028000
123#define AWIN_UART1_OFFSET 0x00028400 123#define AWIN_UART1_OFFSET 0x00028400
124#define AWIN_UART2_OFFSET 0x00028800 124#define AWIN_UART2_OFFSET 0x00028800
125#define AWIN_UART3_OFFSET 0x00028c00 125#define AWIN_UART3_OFFSET 0x00028C00
126#define AWIN_UART4_OFFSET 0x00029000 126#define AWIN_UART4_OFFSET 0x00029000
127#define AWIN_UART5_OFFSET 0x00029400 127#define AWIN_UART5_OFFSET 0x00029400
128#define AWIN_UART6_OFFSET 0x00029800 128#define AWIN_UART6_OFFSET 0x00029800
129#define AWIN_UART7_OFFSET 0x00029c00 129#define AWIN_UART7_OFFSET 0x00029C00
130#define AWIN_PS20_OFFSET 0x0002a000 130#define AWIN_PS20_OFFSET 0x0002A000
131#define AWIN_PS21_OFFSET 0x0002a400 131#define AWIN_PS21_OFFSET 0x0002A400
132#define AWIN__RSVD15_OFFSET 0x0002a800 132#define AWIN__RSVD15_OFFSET 0x0002A800
133#define AWIN_TWI0_OFFSET 0x0002ac00 133#define AWIN_TWI0_OFFSET 0x0002AC00 /* Marvell I2C */
134#define AWIN_TWI1_OFFSET 0x0002b000 134#define AWIN_TWI1_OFFSET 0x0002B000 /* Marvell I2C */
135#define AWIN_TWI2_OFFSET 0x0002b400 135#define AWIN_TWI2_OFFSET 0x0002B400 /* Marvell I2C */
136#define AWIN_TWI3_OFFSET 0x0002b800 136#define AWIN_TWI3_OFFSET 0x0002B800 /* Marvell I2C */
137#define AWIN_CAN_OFFSET 0x0002bc00 137#define AWIN_CAN_OFFSET 0x0002BC00
138#define AWIN_TWI4_OFFSET 0x0002c000 /* A20 */ 138#define AWIN_TWI4_OFFSET 0x0002C000 /* A20 */
139#define AWIN_SCR_OFFSET 0x0002c400 139#define AWIN_SCR_OFFSET 0x0002C400
140#define AWIN_GPS_OFFSET 0x00030000 140#define AWIN_GPS_OFFSET 0x00030000
141#define AWIN_MALI400_OFFSET 0x00040000 141#define AWIN_MALI400_OFFSET 0x00040000
142#define AWIN_GMAC_OFFSET 0x00050000 142#define AWIN_GMAC_OFFSET 0x00050000
143#define AWIN_GMAC_SIZE 0x00010000 /* A20 */ 143#define AWIN_GMAC_SIZE 0x00010000 /* A20 */
144#define AWIN_HSTMR_OFFSET 0x00060000 /* A20 */ 144#define AWIN_HSTMR_OFFSET 0x00060000 /* A20 */
145#define AWIN_GIC_OFFSET 0x00080000 /* A20 */ 145#define AWIN_GIC_OFFSET 0x00080000 /* A20 */
146#define AWIN_HDMI1_OFFSET 0x000E0000 /* A20 */ 146#define AWIN_HDMI1_OFFSET 0x000E0000 /* A20 */
147#define AWIN_SRAMC_OFFSET 0x00100000 147#define AWIN_SRAMC_OFFSET 0x00100000
148#define AWIN_DE_FE0_OFFSET 0x00200000 148#define AWIN_DE_FE0_OFFSET 0x00200000
149#define AWIN_DE_FE1_OFFSET 0x00220000 149#define AWIN_DE_FE1_OFFSET 0x00220000
150#define AWIN_DE_BE1_OFFSET 0x00240000 150#define AWIN_DE_BE1_OFFSET 0x00240000
151#define AWIN_DE_BE0_OFFSET 0x00260000 151#define AWIN_DE_BE0_OFFSET 0x00260000
152#define AWIN_MP_OFFSET 0x00280000 152#define AWIN_MP_OFFSET 0x00280000
153#define AWIN_AVG_OFFSET 0x002A0000 153#define AWIN_AVG_OFFSET 0x002A0000
154#define AWIN_SDRAM_PBASE 0x40000000 154#define AWIN_SDRAM_PBASE 0x40000000
155 155
156/* A10/A20 DRAM Controller */ 156/* A10/A20 DRAM Controller */
157#define AWIN_DRAM_CCR_REG 0x0000 157#define AWIN_DRAM_CCR_REG 0x0000
158#define AWIN_DRAM_DCR_REG 0x0004 158#define AWIN_DRAM_DCR_REG 0x0004
159#define AWIN_DRAM_IOCR_REG 0x0008 159#define AWIN_DRAM_IOCR_REG 0x0008
160#define AWIN_DRAM_CSR_REG 0x000c 160#define AWIN_DRAM_CSR_REG 0x000C
161#define AWIN_DRAM_DRR_REG 0x0010 161#define AWIN_DRAM_DRR_REG 0x0010
162#define AWIN_DRAM_TPR0_REG 0x0014 162#define AWIN_DRAM_TPR0_REG 0x0014
163#define AWIN_DRAM_TPR1_REG 0x0018 163#define AWIN_DRAM_TPR1_REG 0x0018
164#define AWIN_DRAM_TPR2_REG 0x001c 164#define AWIN_DRAM_TPR2_REG 0x001C
165#define AWIN_DRAM_GDLLCR_REG 0x0020 165#define AWIN_DRAM_GDLLCR_REG 0x0020
166#define AWIN_DRAM_RSLR0_REG 0x004c 166#define AWIN_DRAM_RSLR0_REG 0x004C
167#define AWIN_DRAM_RSLR1_REG 0x0050 167#define AWIN_DRAM_RSLR1_REG 0x0050
168#define AWIN_DRAM_RDGR0_REG 0x005c 168#define AWIN_DRAM_RDGR0_REG 0x005C
169#define AWIN_DRAM_RDGR1_REG 0x0060 169#define AWIN_DRAM_RDGR1_REG 0x0060
170#define AWIN_DRAM_ODTCR_REG 0x0098 170#define AWIN_DRAM_ODTCR_REG 0x0098
171#define AWIN_DRAM_DTR0_REG 0x009c 171#define AWIN_DRAM_DTR0_REG 0x009C
172#define AWIN_DRAM_DTR1_REG 0x00a0 172#define AWIN_DRAM_DTR1_REG 0x00A0
173#define AWIN_DRAM_DTAR_REG 0x00a4 173#define AWIN_DRAM_DTAR_REG 0x00A4
174#define AWIN_DRAM_ZQCR0_REG 0x00a8 174#define AWIN_DRAM_ZQCR0_REG 0x00A8
175#define AWIN_DRAM_ZQCR1_REG 0x00ac 175#define AWIN_DRAM_ZQCR1_REG 0x00AC
176#define AWIN_DRAM_ZQSR_REG 0x00b0 176#define AWIN_DRAM_ZQSR_REG 0x00B0
177#define AWIN_DRAM_IDCR_REG 0x00b4 177#define AWIN_DRAM_IDCR_REG 0x00B4
178#define AWIN_DRAM_MR_REG 0x01f0 178#define AWIN_DRAM_MR_REG 0x01F0
179#define AWIN_DRAM_EMR1_REG 0x01f4 179#define AWIN_DRAM_EMR1_REG 0x01F4
180#define AWIN_DRAM_EMR2_REG 0x01f8 180#define AWIN_DRAM_EMR2_REG 0x01F8
181#define AWIN_DRAM_EMR3_REG 0x01fc 181#define AWIN_DRAM_EMR3_REG 0x01FC
182#define AWIN_DRAM_DLLCTR_REG 0x0200 182#define AWIN_DRAM_DLLCTR_REG 0x0200
183#define AWIN_DRAM_DLLCR0_REG 0x0204 183#define AWIN_DRAM_DLLCR0_REG 0x0204
184#define AWIN_DRAM_DLLCR1_REG 0x0208 184#define AWIN_DRAM_DLLCR1_REG 0x0208
185#define AWIN_DRAM_DLLCR2_REG 0x020c 185#define AWIN_DRAM_DLLCR2_REG 0x020C
186#define AWIN_DRAM_DLLCR3_REG 0x0210 186#define AWIN_DRAM_DLLCR3_REG 0x0210
187#define AWIN_DRAM_DLLCR4_REG 0x0214 187#define AWIN_DRAM_DLLCR4_REG 0x0214
188#define AWIN_DRAM_DQTR0_REG 0x0218 188#define AWIN_DRAM_DQTR0_REG 0x0218
189#define AWIN_DRAM_DQTR1_REG 0x021c 189#define AWIN_DRAM_DQTR1_REG 0x021C
190#define AWIN_DRAM_DQTR2_REG 0x0220 190#define AWIN_DRAM_DQTR2_REG 0x0220
191#define AWIN_DRAM_DQTR3_REG 0x0224 191#define AWIN_DRAM_DQTR3_REG 0x0224
192#define AWIN_DRAM_DQSTR_REG 0x0228 192#define AWIN_DRAM_DQSTR_REG 0x0228
193#define AWIN_DRAM_DQSBTR_REG 0x022c 193#define AWIN_DRAM_DQSBTR_REG 0x022C
194#define AWIN_DRAM_MCR_REG 0x0230 194#define AWIN_DRAM_MCR_REG 0x0230
195#define AWIN_DRAM_PPWRSCTRL_REG 0x0240 195#define AWIN_DRAM_PPWRSCTRL_REG 0x0240
196#define AWIN_DRAM_APR_REG 0x0244 196#define AWIN_DRAM_APR_REG 0x0244
197#define AWIN_DRAM_PLDTR_REG 0x023c 197#define AWIN_DRAM_PLDTR_REG 0x023C
198#define AWIN_DRAM_HPCR0_REG 0x0240 198#define AWIN_DRAM_HPCR0_REG 0x0240
199#define AWIN_DRAM_HPCRn_REG(n) (0x0240+4*(n)) 199#define AWIN_DRAM_HPCRn_REG(n) (0x0240+4*(n))
200#define AWIN_DRAM_CSEL_REG 0x02e0 200#define AWIN_DRAM_HPCR_USB1 AWIN_DRAM_HPCRn_REG(4)
 201#define AWIN_DRAM_HPCR_USB2 AWIN_DRAM_HPCRn_REG(5)
 202#define AWIN_DRAM_CSEL_REG 0x02E0
201 203
202#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1) 204#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1)
203#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2 205#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2
204#define AWIN_DRAM_DCR_IO_WIDTH_8BIT 1 206#define AWIN_DRAM_DCR_IO_WIDTH_8BIT 1
205#define AWIN_DRAM_DCR_CHIP_DENSITY __BITS(5,3) 207#define AWIN_DRAM_DCR_CHIP_DENSITY __BITS(5,3)
206#define AWIN_DRAM_DCR_CHIP_DENSITY_256M 0 208#define AWIN_DRAM_DCR_CHIP_DENSITY_256M 0
207#define AWIN_DRAM_DCR_CHIP_DENSITY_512M 1 209#define AWIN_DRAM_DCR_CHIP_DENSITY_512M 1
208#define AWIN_DRAM_DCR_CHIP_DENSITY_1G 2 210#define AWIN_DRAM_DCR_CHIP_DENSITY_1G 2
209#define AWIN_DRAM_DCR_CHIP_DENSITY_2G 3 211#define AWIN_DRAM_DCR_CHIP_DENSITY_2G 3
210#define AWIN_DRAM_DCR_CHIP_DENSITY_4G 4 212#define AWIN_DRAM_DCR_CHIP_DENSITY_4G 4
211#define AWIN_DRAM_DCR_CHIP_DENSITY_8G 5 213#define AWIN_DRAM_DCR_CHIP_DENSITY_8G 5
212#define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6) 214#define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6)
213#define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3 215#define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3
214#define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1 216#define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1
215#define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0 217#define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0
216#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10) 218#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10)
217 219
 220#define AWIN_DRAM_HPCR_READ_CNT_EN __BIT(31)
 221#define AWIN_DRAM_HPCR_RWRITE_CNT_EN __BIT(30)
 222#define AWIN_DRAM_HPCR_COMMAND_NUM __BIT(8)
 223#define AWIN_DRAM_HPCR_WAIT_STATE __BIT(4)
 224#define AWIN_DRAM_HPCR_PRIORITY_LEVEL __BIT(2)
 225#define AWIN_DRAM_HPCR_ACCESS_EN __BIT(0)
 226
 227#define AWIN_EMAC_CTL_REG 0x0000
 228#define AWIN_EMAC_TX_MODE_REG 0x0004
 229#define AWIN_EMAC_TX_FLOW_REG 0x0008
 230#define AWIN_EMAC_TX_CTL0_REG 0x000C
 231#define AWIN_EMAC_TX_CTL1_REG 0x0010
 232#define AWIN_EMAC_TX_INS_REG 0x0014
 233#define AWIN_EMAC_TX_PL0_REG 0x0018
 234#define AWIN_EMAC_TX_PL1_REG 0x001C
 235#define AWIN_EMAC_TX_STA_REG 0x0020
 236#define AWIN_EMAC_TX_IO_DATA0_REG 0x0024
 237#define AWIN_EMAC_TX_IO_DATA1_REG 0x0028
 238#define AWIN_EMAC_TX_TSVL0_REG 0x002C
 239#define AWIN_EMAC_TX_TSVH0_REG 0x0030
 240#define AWIN_EMAC_TX_TSVL1_REG 0x0034
 241#define AWIN_EMAC_TX_TSVH1_REG 0x0038
 242#define AWIN_EMAC_RX_CTL_REG 0x003C
 243#define AWIN_EMAC_RX_HASH0_REG 0x0040
 244#define AWIN_EMAC_RX_HASH1_REG 0x0044
 245#define AWIN_EMAC_RX_STA_REG 0x0048
 246#define AWIN_EMAC_RX_IO_DATA_REG 0x004C
 247#define AWIN_EMAC_RX_FBC_REG 0x0050
 248#define AWIN_EMAC_INT_CTL_REG 0x0054
 249#define AWIN_EMAC_INT_STA_REG 0x0058
 250#define AWIN_EMAC_MAC_CTL0_REG 0x005C
 251#define AWIN_EMAC_MAC_CTL1_REG 0x0060
 252#define AWIN_EMAC_MAC_IPGT_REG 0x0064
 253#define AWIN_EMAC_MAC_IPGR_REG 0x0068
 254#define AWIN_EMAC_MAC_CLRT_REG 0x006C
 255#define AWIN_EMAC_MAC_MAXF_REG 0x0070
 256#define AWIN_EMAC_MAC_SUPP_REG 0x0074
 257#define AWIN_EMAC_MAC_TEST_REG 0x0078
 258#define AWIN_EMAC_MAC_MCFG_REG 0x007C
 259#define AWIN_EMAC_MAC_MCMD_REG 0x0080
 260#define AWIN_EMAC_MAC_MADR_REG 0x0084
 261#define AWIN_EMAC_MAC_MWTD_REG 0x0088
 262#define AWIN_EMAC_MAC_MRDD_REG 0x008C
 263#define AWIN_EMAC_MAC_MIND_REG 0x0090
 264#define AWIN_EMAC_MAC_SSRR_REG 0x0094
 265#define AWIN_EMAC_MAC_A0_REG 0x0098
 266#define AWIN_EMAC_MAC_A1_REG 0x009C
 267#define AWIN_EMAC_MAC_A2_REG 0x00A0
 268#define AWIN_EMAC_SAFX0_L_REG 0x00A4
 269#define AWIN_EMAC_SAFX0_H_REG 0x00A8
 270#define AWIN_EMAC_SAFX1_L_REG 0x00AC
 271#define AWIN_EMAC_SAFX1_H_REG 0x00B0
 272#define AWIN_EMAC_SAFX2_L_REG 0x00B4
 273#define AWIN_EMAC_SAFX2_H_REG 0x00B8
 274#define AWIN_EMAC_SAFX3_L_REG 0x00BC
 275#define AWIN_EMAC_SAFX3_H_REG 0x00C0
 276
 277#define AWIN_ACHI_BISTAFR_REG 0x00A0
 278#define AWIN_AHCI_BISTCR_REG 0x00A4
 279#define AWIN_AHCI_BISTFCTR_REG 0x00A8
 280#define AWIN_AHCI_BISTSR_REG 0x00AC
 281#define AWIN_AHCI_BISTDECR_REG 0x00B0
 282#define AWIN_AHCI_DIAGNR_REG 0x00B4
 283#define AWIN_AHCI_DIAGNR1_REG 0x00B8
 284#define AWIN_AHCI_OOBR_REG 0x00BC
 285#define AWIN_AHCI_PHYCS0R_REG 0x00C0
 286#define AWIN_AHCI_PHYCS1R_REG 0x00C4
 287#define AWIN_AHCI_PHYCS2R_REG 0x00C8
 288#define AWIN_AHCI_TIMER1MS_REG 0x00E0
 289#define AWIN_AHCI_GPARAM1R_REG 0x00E8
 290#define AWIN_AHCI_GPARAM2R_REG 0x00EC
 291#define AWIN_AHCI_PPARAMR_REG 0x00F0
 292#define AWIN_AHCI_TESTR_REG 0x00F4
 293#define AWIN_AHCI_VERSIONR_REG 0x00F8
 294#define AWIN_AHCI_IDR_REG 0x00FC
 295#define AWIN_AHCI_RWCR_REG 0x00FC
 296
 297#define AWIN_AHCI_P0DMACR_REG 0x0170
 298#define AWIN_AHCI_P0PHYCR_REG 0x0178
 299#define AWIN_AHCI_P0PHYSR_REG 0x017C
 300
 301
218#define AWIN_PLL1_CFG_REG 0x0000 302#define AWIN_PLL1_CFG_REG 0x0000
219#define AWIN_PLL1_TUN_REG 0x0004 303#define AWIN_PLL1_TUN_REG 0x0004
220#define AWIN_PLL2_CFG_REG 0x0008 304#define AWIN_PLL2_CFG_REG 0x0008
221#define AWIN_PLL2_TUN_REG 0x000c 305#define AWIN_PLL2_TUN_REG 0x000C
222#define AWIN_PLL3_CFG_REG 0x0010 306#define AWIN_PLL3_CFG_REG 0x0010
223#define AWIN_PLL4_CFG_REG 0x0018 307#define AWIN_PLL4_CFG_REG 0x0018
224#define AWIN_PLL5_CFG_REG 0x0020 308#define AWIN_PLL5_CFG_REG 0x0020
225#define AWIN_PLL5_TUN_REG 0x0024 309#define AWIN_PLL5_TUN_REG 0x0024
226#define AWIN_PLL6_CFG_REG 0x0028 310#define AWIN_PLL6_CFG_REG 0x0028
227#define AWIN_PLL6_TUN_REG 0x002c 311#define AWIN_PLL6_TUN_REG 0x002C
228#define AWIN_PLL7_CFG_REG 0x0030 312#define AWIN_PLL7_CFG_REG 0x0030
229#define AWIN_PLL1_TUN2_REG 0x0038 313#define AWIN_PLL1_TUN2_REG 0x0038
230#define AWIN_PLL6_TUN2_REG 0x003c 314#define AWIN_PLL6_TUN2_REG 0x003C
231#define AWIN_PLL8_CFG_REG 0x0040 315#define AWIN_PLL8_CFG_REG 0x0040
232#define AWIN_OSC24M_CFG_REG 0x0050 316#define AWIN_OSC24M_CFG_REG 0x0050
233#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054 317#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
234#define AWIN_APB1_CLK_DIV_REG 0x0058 318#define AWIN_APB1_CLK_DIV_REG 0x0058
235#define AWIN_AXI_GATING_REG 0x005c 319#define AWIN_AXI_GATING_REG 0x005C
236#define AWIN_AHB_GATING0_REG 0x0060 320#define AWIN_AHB_GATING0_REG 0x0060
237#define AWIN_AHB_GATING1_REG 0x0064 321#define AWIN_AHB_GATING1_REG 0x0064
238#define AWIN_APB0_GATING_REG 0x0068 322#define AWIN_APB0_GATING_REG 0x0068
239#define AWIN_APB1_GATING_REG 0x006c 323#define AWIN_APB1_GATING_REG 0x006C
240#define AWIN_NAND_SCLK_CFG_REG 0x0080 324#define AWIN_NAND_SCLK_CFG_REG 0x0080
 325#define AWIN_MS_SCLK_CFG_REG 0x0084
241#define AWIN_SD0_CLK_REG 0x0088 326#define AWIN_SD0_CLK_REG 0x0088
242#define AWIN_SD1_CLK_REG 0x008c 327#define AWIN_SD1_CLK_REG 0x008C
243#define AWIN_SD2_CLK_REG 0x0090 328#define AWIN_SD2_CLK_REG 0x0090
244#define AWIN_SD3_CLK_REG 0x0094 329#define AWIN_SD3_CLK_REG 0x0094
245#define AWIN_TS_CLK_REG 0x0098 330#define AWIN_TS_CLK_REG 0x0098
246#define AWIN_SS_CLK_REG 0x009c 331#define AWIN_SS_CLK_REG 0x009C
247#define AWIN_SPI0_CLK_REG 0x00a0 332#define AWIN_SPI0_CLK_REG 0x00A0
248#define AWIN_SPI1_CLK_REG 0x00a4 333#define AWIN_SPI1_CLK_REG 0x00A4
249#define AWIN_SPI2_CLK_REG 0x00a8 334#define AWIN_SPI2_CLK_REG 0x00A8
250#define AWIN_IR0_CLK_REG 0x00b9 335#define AWIN_IR0_CLK_REG 0x00B9
251#define AWIN_IR1_CLK_REG 0x00b4 336#define AWIN_IR1_CLK_REG 0x00B4
252#define AWIN_IIS_CLK_REG 0x00b8 337#define AWIN_IIS_CLK_REG 0x00B8
253#define AWIN_AC97_CLK_REG 0x00bc 338#define AWIN_AC97_CLK_REG 0x00BC
254#define AWIN_KEYPAD_CLK_REG 0x00c4 339#define AWIN_SPDIF_CLK_REG 0x00C0
255#define AWIN_USB_CLK_REG 0x00cc 340#define AWIN_KEYPAD_CLK_REG 0x00C4
256#define AWIN_SPI3_CLK_REG 0x00d4 341#define AWIN_SATA_CLK_REG 0x00C8
 342#define AWIN_USB_CLK_REG 0x00CC
 343#define AWIN_SPI3_CLK_REG 0x00D4
257#define AWIN_DRAM_CLK_REG 0x0100 344#define AWIN_DRAM_CLK_REG 0x0100
258#define AWIN_BE0_SCLK_CFG_REG 0x0100 345#define AWIN_BE0_SCLK_CFG_REG 0x0100
259#define AWIN_BE0_SCLK_CFG_REG 0x0100 346#define AWIN_BE0_SCLK_CFG_REG 0x0100
260#define AWIN_FE0_CLK_REG 0x0100 347#define AWIN_FE0_CLK_REG 0x0100
261#define AWIN_FE1_CLK_REG 0x0110 348#define AWIN_FE1_CLK_REG 0x0110
262#define AWIN_MP_CLK_REG 0x0114 349#define AWIN_MP_CLK_REG 0x0114
263#define AWIN_LCD0_CH0_CLK_REG 0x0118 350#define AWIN_LCD0_CH0_CLK_REG 0x0118
264#define AWIN_LCD1_CH0_CLK_REG 0x011c 351#define AWIN_LCD1_CH0_CLK_REG 0x011C
265#define AWIN_CSI_ISP_CLK_REG 0x0120 352#define AWIN_CSI_ISP_CLK_REG 0x0120
266#define AWIN_TVD_CLK_REG 0x0128 353#define AWIN_TVD_CLK_REG 0x0128
267#define AWIN_LCD0_CH1_CLK_REG 0x012c 354#define AWIN_LCD0_CH1_CLK_REG 0x012C
268#define AWIN_LCD1_CH1_CLK_REG 0x0130 355#define AWIN_LCD1_CH1_CLK_REG 0x0130
269#define AWIN_CSI0_CLK_REG 0x0134 356#define AWIN_CSI0_CLK_REG 0x0134
270#define AWIN_CSI1_CLK_REG 0x0138 357#define AWIN_CSI1_CLK_REG 0x0138
271#define AWIN_VE_CLK_REG 0x013c 358#define AWIN_VE_CLK_REG 0x013C
272#define AWIN_AUDIO_CODEC_CLK_REG 0x0140 359#define AWIN_AUDIO_CODEC_CLK_REG 0x0140
273#define AWIN_AVS_CLK_REG 0x0144 360#define AWIN_AVS_CLK_REG 0x0144
274#define AWIN_ACE_CLK_REG 0x0148 361#define AWIN_ACE_CLK_REG 0x0148
275#define AWIN_LVDS_CLK_REG 0x014c 362#define AWIN_LVDS_CLK_REG 0x014C
276#define AWIN_HDMI_CLK_REG 0x0150 363#define AWIN_HDMI_CLK_REG 0x0150
277#define AWIN_MALI400_CLK_REG 0x0154 364#define AWIN_MALI400_CLK_REG 0x0154
 365#define AWIN_MBUF_SCLK_CFG_REG 0x015C
 366#define AWIN_GMAC_CLK_REG 0x0164
 367#define AWIN_HDM1_RST_REG 0x0170
 368#define AWIN_HDM1_CTLR_REG 0x0174
 369#define AWIN_HDM1_SLOW_CLK_REG 0x0178
 370#define AWIN_HDM1_REPPEAT_CLK_REG 0x017C
 371#define AWIN_CLK_OUTA_REG 0x01F0
 372#define AWIN_CLK_OUTB_REG 0x01F4
278 373
279#define AWIN_OSC24M_CFG_ENABLE __BIT(0) 374#define AWIN_OSC24M_CFG_ENABLE __BIT(0)
280 375
281#define AWIN_PLL_CFG_ENABLE __BIT(31) 376#define AWIN_PLL_CFG_ENABLE __BIT(31)
 377#define AWIN_PLL_CFG_BYPASS __BIT(30)
 378#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
282#define AWIN_PLL_CFG_EXG_MODE __BIT(25) 379#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
283#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16) 380#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
 381#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
284#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8) 382#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
 383#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
285#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4) 384#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
 385#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
 386#define AWIN_PLL1_SIG_DELT_PAT_IN __BIT(3)
 387#define AWIN_PLL1_SIG_DELT_PAT_EN __BIT(2)
286#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0) 388#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
287 389
288#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16) 390#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
289#define AWIN_CPU_CLK_SRC_SEL_LOSC 0 391#define AWIN_CPU_CLK_SRC_SEL_LOSC 0
290#define AWIN_CPU_CLK_SRC_SEL_OSC24M 1 392#define AWIN_CPU_CLK_SRC_SEL_OSC24M 1
291#define AWIN_CPU_CLK_SRC_SEL_PLL1 2 393#define AWIN_CPU_CLK_SRC_SEL_PLL1 2
292#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3 394#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3
293#define AWIN_APB0_CLK_RATIO __BITS(9,8) 395#define AWIN_APB0_CLK_RATIO __BITS(9,8)
294 396
295#define AWIN_AHB_GATING0_NC25 __BIT(25) 397#define AWIN_AHB_GATING0_STIMER __BIT(28)
 398#define AWIN_AHB_GATING0_SATA __BIT(25)
296#define AWIN_AHB_GATING0_PATA __BIT(24) 399#define AWIN_AHB_GATING0_PATA __BIT(24)
297#define AWIN_AHB_GATING0_SPI3 __BIT(23) 400#define AWIN_AHB_GATING0_SPI3 __BIT(23)
298#define AWIN_AHB_GATING0_SPI2 __BIT(22) 401#define AWIN_AHB_GATING0_SPI2 __BIT(22)
299#define AWIN_AHB_GATING0_SPI1 __BIT(21) 402#define AWIN_AHB_GATING0_SPI1 __BIT(21)
300#define AWIN_AHB_GATING0_SPI0 __BIT(20) 403#define AWIN_AHB_GATING0_SPI0 __BIT(20)
301#define AWIN_AHB_GATING0_TS __BIT(18) 404#define AWIN_AHB_GATING0_TS __BIT(18)
302#define AWIN_AHB_GATING0_EMAC __BIT(17) 405#define AWIN_AHB_GATING0_EMAC __BIT(17)
303#define AWIN_AHB_GATING0_ACE __BIT(16) 406#define AWIN_AHB_GATING0_ACE __BIT(16)
304#define AWIN_AHB_GATING0_SDRAM __BIT(14) 407#define AWIN_AHB_GATING0_SDRAM __BIT(14)
305#define AWIN_AHB_GATING0_NAND __BIT(13) 408#define AWIN_AHB_GATING0_NAND __BIT(13)
306#define AWIN_AHB_GATING0_NC12 __BIT(12) 409#define AWIN_AHB_GATING0_NC12 __BIT(12)
307#define AWIN_AHB_GATING0_SDMMC3 __BIT(11) 410#define AWIN_AHB_GATING0_SDMMC3 __BIT(11)
308#define AWIN_AHB_GATING0_SDMMC2 __BIT(10) 411#define AWIN_AHB_GATING0_SDMMC2 __BIT(10)
309#define AWIN_AHB_GATING0_SDMMC1 __BIT(9) 412#define AWIN_AHB_GATING0_SDMMC1 __BIT(9)
310#define AWIN_AHB_GATING0_SDMMC0 __BIT(8) 413#define AWIN_AHB_GATING0_SDMMC0 __BIT(8)
311#define AWIN_AHB_GATING0_BIST __BIT(7) 414#define AWIN_AHB_GATING0_BIST __BIT(7)
312#define AWIN_AHB_GATING0_DMA __BIT(6) 415#define AWIN_AHB_GATING0_DMA __BIT(6)
313#define AWIN_AHB_GATING0_SS __BIT(5) 416#define AWIN_AHB_GATING0_SS __BIT(5)
 417#define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4)
314#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3) 418#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3)
 419#define AWIN_AHB_GATING0_USB_OHCI0 __BIT(1)
315#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1) 420#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1)
316#define AWIN_AHB_GATING0_USB0 __BIT(0) 421#define AWIN_AHB_GATING0_USB0 __BIT(0)
317 422
318#define AWIN_AHB_GATING1_MALI400 __BIT(20) 423#define AWIN_AHB_GATING1_MALI400 __BIT(20)
319#define AWIN_AHB_GATING1_MP __BIT(18) 424#define AWIN_AHB_GATING1_MP __BIT(18)
 425#define AWIN_AHB_GATING1_GMAC __BIT(17)
320#define AWIN_AHB_GATING1_DE_FE1 __BIT(15) 426#define AWIN_AHB_GATING1_DE_FE1 __BIT(15)
321#define AWIN_AHB_GATING1_DE_FE0 __BIT(14) 427#define AWIN_AHB_GATING1_DE_FE0 __BIT(14)
322#define AWIN_AHB_GATING1_DE_BE1 __BIT(13) 428#define AWIN_AHB_GATING1_DE_BE1 __BIT(13)
323#define AWIN_AHB_GATING1_DE_BE0 __BIT(12) 429#define AWIN_AHB_GATING1_DE_BE0 __BIT(12)
324#define AWIN_AHB_GATING1_HDMI __BIT(11) 430#define AWIN_AHB_GATING1_HDMI __BIT(11)
325#define AWIN_AHB_GATING1_CSI1 __BIT(9) 431#define AWIN_AHB_GATING1_CSI1 __BIT(9)
326#define AWIN_AHB_GATING1_CSI0 __BIT(8) 432#define AWIN_AHB_GATING1_CSI0 __BIT(8)
327#define AWIN_AHB_GATING1_LCD1 __BIT(5) 433#define AWIN_AHB_GATING1_LCD1 __BIT(5)
328#define AWIN_AHB_GATING1_LCD0 __BIT(4) 434#define AWIN_AHB_GATING1_LCD0 __BIT(4)
329#define AWIN_AHB_GATING1_TVE1 __BIT(3) 435#define AWIN_AHB_GATING1_TVE1 __BIT(3)
330#define AWIN_AHB_GATING1_TVE0 __BIT(2) 436#define AWIN_AHB_GATING1_TVE0 __BIT(2)
331#define AWIN_AHB_GATING1_TVD __BIT(1) 437#define AWIN_AHB_GATING1_TVD __BIT(1)
332#define AWIN_AHB_GATING1_VE __BIT(0) 438#define AWIN_AHB_GATING1_VE __BIT(0)
333 439
 440#define AWIN_APB_GATING0_KEYPAD __BIT(10)
 441#define AWIN_APB_GATING0_IIS2 __BIT(8)
 442#define AWIN_APB_GATING0_IR1 __BIT(7)
 443#define AWIN_APB_GATING0_IR0 __BIT(6)
 444#define AWIN_APB_GATING0_PIO __BIT(5)
 445#define AWIN_APB_GATING0_IIS1 __BIT(4)
 446#define AWIN_APB_GATING0_IIS0 __BIT(3)
 447#define AWIN_APB_GATING0_AC97 __BIT(2)
 448#define AWIN_APB_GATING0_SPDIF __BIT(1)
 449#define AWIN_APB_GATING0_CODEC __BIT(0)
 450
 451#define AWIN_APB_GATING1_UART7 __BIT(23)
 452#define AWIN_APB_GATING1_UART6 __BIT(22)
 453#define AWIN_APB_GATING1_UART5 __BIT(21)
 454#define AWIN_APB_GATING1_UART4 __BIT(20)
 455#define AWIN_APB_GATING1_UART3 __BIT(19)
 456#define AWIN_APB_GATING1_UART2 __BIT(18)
 457#define AWIN_APB_GATING1_UART1 __BIT(17)
 458#define AWIN_APB_GATING1_UART0 __BIT(16)
 459#define AWIN_APB_GATING1_TWI4 __BIT(15)
 460#define AWIN_APB_GATING1_PS21 __BIT(7)
 461#define AWIN_APB_GATING1_PS20 __BIT(6)
 462#define AWIN_APB_GATING1_SCR __BIT(5)
 463#define AWIN_APB_GATING1_CAN __BIT(4)
 464#define AWIN_APB_GATING1_TWI3 __BIT(3)
 465#define AWIN_APB_GATING1_TWI2 __BIT(2)
 466#define AWIN_APB_GATING1_TWI1 __BIT(1)
 467#define AWIN_APB_GATING1_TWI0 __BIT(0)
 468
334#define AWIN_CLK_ENABLE __BIT(31) 469#define AWIN_CLK_ENABLE __BIT(31)
335#define AWIN_CLK_SRC_SEL __BITS(25,24) 470#define AWIN_CLK_SRC_SEL __BITS(25,24)
336#define AWIN_CLK_SRC_SEL_OSC24M 0 471#define AWIN_CLK_SRC_SEL_OSC24M 0
337#define AWIN_CLK_SRC_SEL_PLL6 1 472#define AWIN_CLK_SRC_SEL_PLL6 1
338#define AWIN_CLK_SRC_SEL_PLL5 2 473#define AWIN_CLK_SRC_SEL_PLL5 2
 474#define AWIN_CLK_SRC_SEL_LOSC 3
 475#define AWIN_CLK_SRC_SEL_KEYPAD_LOSC 2
 476#define AWIN_CLK_SRC_SEL_SATA_PLL6 0 /* 100 MHz */
 477#define AWIN_CLK_SRC_SEL_SATA_EXT 1
 478#define AWIN_CLK_SRC_SEL_DE_PLL3 0
 479#define AWIN_CLK_SRC_SEL_DE_PLL7 1
 480#define AWIN_CLK_SRC_SEL_DE_PLL5 2
339#define AWIN_CLK_DIV_RATIO_N __BITS(17,16) 481#define AWIN_CLK_DIV_RATIO_N __BITS(17,16)
340#define AWIN_CLK_DIV_RATIO_M __BITS(3,0) 482#define AWIN_CLK_DIV_RATIO_M __BITS(3,0)
341 483
342/* SDMMC definitions */ 484#define AWIN_ISS_CLK_SRC_SEL __BITS(17,16)
343#define AWIN_SDMMC_GCTRL_REG 0x0000 485
344#define AWIN_SDMMC_CLKCR_REG 0x0004 486#define AWIN_USB_CLK_USBPHY_ENABLE __BIT(8)
345#define AWIN_SDMMC_TIMEOUT_REG 0x0008 487#define AWIN_USB_CLK_OHCI1_ENABLE __BIT(7)
346#define AWIN_SDMMC_WIDTH_REG 0x000c 488#define AWIN_USB_CLK_OHCI0_ENABLE __BIT(6)
347#define AWIN_SDMMC_BLKSZ_REG 0x0010 489#define AWIN_USB_CLK_PHY2_ENABLE __BIT(2)
348#define AWIN_SDMMC_BYTECNT_REG 0x0014 490#define AWIN_USB_CLK_PHY1_ENABLE __BIT(1)
349#define AWIN_SDMMC_CMD_REG 0x0018 491#define AWIN_USB_CLK_PHY0_ENABLE __BIT(0)
350#define AWIN_SDMMC_ARG_REG 0x001c 492
351#define AWIN_SDMMC_RESP0_REG 0x0020 493#define AWIN_DRAM_CLK_ACE_DCLK_ENABLE __BIT(29)
352#define AWIN_SDMMC_RESP1_REG 0x0024 494#define AWIN_DRAM_CLK_DE_MP_DCLK_ENABLE __BIT(28)
353#define AWIN_SDMMC_RESP2_REG 0x0028 495#define AWIN_DRAM_CLK_BE1_DCLK_ENABLE __BIT(27)
354#define AWIN_SDMMC_RESP3_REG 0x002c 496#define AWIN_DRAM_CLK_BE0_DCLK_ENABLE __BIT(26)
355#define AWIN_SDMMC_IMASK_REG 0x0030 497#define AWIN_DRAM_CLK_FE1_DCLK_ENABLE __BIT(25)
356#define AWIN_SDMMC_MINT_REG 0x0034 498#define AWIN_DRAM_CLK_FE0_DCLK_ENABLE __BIT(24)
357#define AWIN_SDMMC_RINT_REG 0x0038 499#define AWIN_DRAM_CLK_DCLK_OUT_ENABLE __BIT(16)
358#define AWIN_SDMMC_STATUS_REG 0x003c 500#define AWIN_DRAM_CLK_TVE1_DCLK_ENABLE __BIT(6)
359#define AWIN_SDMMC_FTRGLVL_REG 0x0040 501#define AWIN_DRAM_CLK_TVE0_DCLK_ENABLE __BIT(5)
360#define AWIN_SDMMC_FUNCSEL_REG 0x0044 502#define AWIN_DRAM_CLK_TVD_DCLK_ENABLE __BIT(4)
361#define AWIN_SDMMC_CBCR_REG 0x0048 503#define AWIN_DRAM_CLK_TS_DCLK_ENABLE __BIT(3)
362#define AWIN_SDMMC_BBCR_REG 0x004c 504#define AWIN_DRAM_CLK_CSI1_DCLK_ENABLE __BIT(2)
363#define AWIN_SDMMC_DMAC_REG 0x0080 505#define AWIN_DRAM_CLK_CSI0_DCLK_ENABLE __BIT(1)
364#define AWIN_SDMMC_DLBA_REG 0x0084 506#define AWIN_DRAM_CLK_VE_DCLK_ENABLE __BIT(0)
365#define AWIN_SDMMC_IDST_REG 0x0088 507
366#define AWIN_SDMMC_IDIE_REG 0x008c 508#define AWIN_GMAC_CLK_TXC_DIV __BITS(9,8)
367#define AWIN_SDMMC_CHDA_REG 0x0090 509#define AWIN_GMAC_CLK_TXC_DIV_1000 0
368#define AWIN_SDMMC_CBDA_REG 0x0094 510#define AWIN_GMAC_CLK_TXC_DIV_100 1
369#define AWIN_SDMMC_FIFO_REG 0x0100 511#define AWIN_GMAC_CLK_TXC_DIV_10 2
 512#define AWIN_GMAC_CLK_RXDC __BITS(7,5)
 513#define AWIN_GMAC_CLK_RXIE __BIT(4)
 514#define AWIN_GMAC_CLK_TXIE __BIT(3)
 515#define AWIN_GMAC_CLK_PIT __BIT(2)
 516#define AWIN_GMAC_CLK_TCS __BITS(1,0)
 517#define AWIN_GMAC_CLK_TCS_MII 0
 518#define AWIN_GMAC_CLK_TCS_EXT_125 1
 519#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
 520
 521#define AWIN_CLK_OUT_ENABLE __BIT(31)
 522#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
 523#define AWIN_CLK_OUT_SRC_SEL_32K 0
 524#define AWIN_CLK_OUT_SRC_SEL_LOSC 1
 525#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2
 526#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20)
 527#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8)
370 528
371/* USB device offsets */ 529/* USB device offsets */
372#define AWIN_EHCI_OFFSET 0x0000 530#define AWIN_EHCI_OFFSET 0x0000
373#define AWIN_EHCI_SIZE 0x0400 531#define AWIN_EHCI_SIZE 0x0400
374#define AWIN_OHCI_OFFSET 0x0400 532#define AWIN_OHCI_OFFSET 0x0400
375#define AWIN_OHCI_SIZE 0x0400 533#define AWIN_OHCI_SIZE 0x0400
376 534
377/* PATA Definitions */ 535/* PATA Definitions */
378#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */ 536#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */
379 537
380/* A10 Interrupt Register Definitions */ 538/* A10 Interrupt Register Definitions */
381#define AWIN_INTC_VECTOR_REG 0x0000 539#define AWIN_INTC_VECTOR_REG 0x0000
382#define AWIN_INTC_BASE_ADDR_REG 0x0004 540#define AWIN_INTC_BASE_ADDR_REG 0x0004
@@ -398,26 +556,227 @@ @@ -398,26 +556,227 @@
398#define AWIN_INTC_MASK2_REG 0x0058 556#define AWIN_INTC_MASK2_REG 0x0058
399#define AWIN_INTC_RESP0_REG 0x0060 557#define AWIN_INTC_RESP0_REG 0x0060
400#define AWIN_INTC_RESP1_REG 0x0064 558#define AWIN_INTC_RESP1_REG 0x0064
401#define AWIN_INTC_RESP2_REG 0x0068 559#define AWIN_INTC_RESP2_REG 0x0068
402#define AWIN_INTC_FF0_REG 0x0070 560#define AWIN_INTC_FF0_REG 0x0070
403#define AWIN_INTC_FF1_REG 0x0074 561#define AWIN_INTC_FF1_REG 0x0074
404#define AWIN_INTC_FF2_REG 0x0078 562#define AWIN_INTC_FF2_REG 0x0078
405#define AWIN_INTC_PRIO0_REG 0x0080 563#define AWIN_INTC_PRIO0_REG 0x0080
406#define AWIN_INTC_PRIO1_REG 0x0084 564#define AWIN_INTC_PRIO1_REG 0x0084
407#define AWIN_INTC_PRIO2_REG 0x0088 565#define AWIN_INTC_PRIO2_REG 0x0088
408#define AWIN_INTC_PRIO3_REG 0x008C 566#define AWIN_INTC_PRIO3_REG 0x008C
409#define AWIN_INTC_PRIO4_REG 0x0090 567#define AWIN_INTC_PRIO4_REG 0x0090
410 568
 569/* [G]PIO Definitions */
 570#define AWIN_PIO_CFG0_REG 0x0000
 571#define AWIN_PIO_CFG1_REG 0x0004
 572#define AWIN_PIO_CFG2_REG 0x0008
 573#define AWIN_PIO_CFG3_REG 0x000c
 574#define AWIN_PIO_DAT_REG 0x0010
 575#define AWIN_PIO_DRV0_REG 0x0014
 576#define AWIN_PIO_DRV1_REG 0x0018
 577#define AWIN_PIO_PUL0_REG 0x001c
 578#define AWIN_PIO_PUL1_REG 0x0020
 579#define AWIN_PIO_GRP_SIZE 0x0024
 580#define AWIN_PIO_INT_CFG0_REG 0x0200
 581#define AWIN_PIO_INT_CFG1_REG 0x0204
 582#define AWIN_PIO_INT_CFG2_REG 0x0208
 583#define AWIN_PIO_INT_CFG3_REG 0x020c
 584#define AWIN_PIO_INT_CTL_REG 0x0210
 585#define AWIN_PIO_INT_STA_REG 0x0214
 586#define AWIN_PIO_INT_DEB_REG 0x0218
 587#define AWIN_PIO_SDR_PAD_DEV_REG 0x0220
 588#define AWIN_PIO_SDR_PAD_PUL_REG 0x0224
 589
 590#define AWIN_PIO_CFG_PINMASK(pin) (7 << (4*((pin) & 7)))
 591#define AWIN_PIO_DRV_MASK(pin) ((x) << (2*((pin) & 15)))
 592
 593#define AWIN_PIO_FUNC_INPUT 0x0
 594#define AWIN_PIO_FUNC_OUTPUT 0x0
 595
 596#define AWIN_PIO_EINT_POSITIVE_EDGE 0x0
 597#define AWIN_PIO_EINT_NEGATIVE_EDGE 0x1
 598#define AWIN_PIO_EINT_HIGH_LEVEL 0x2
 599#define AWIN_PIO_EINT_LOW_LEVEL 0x3
 600#define AWIN_PIO_EINT_DOUBLE_EDGE 0x4
 601
 602#define AWIN_PIO_PA_PINS 18
 603#define AWIN_PIO_PA_EMAC_PINS 0x0003ffff /* PA pins 17-0 */
 604#define AWIN_PIO_PA_EMAC_FUNC 2
 605#define AWIN_PIO_PA_CAN_PINS 0x00030000 /* PA pins 17-16 */
 606#define AWIN_PIO_PA_CAN_FUNC 3
 607#define AWIN_PIO_PA_UART7_PINS 0x0000c000 /* PA pins 15-14 */
 608#define AWIN_PIO_PA_UART7_FUNC 3
 609#define AWIN_PIO_PA_UART6_PINS 0x00003000 /* PA pins 13-12 */
 610#define AWIN_PIO_PA_UART6_FUNC 3
 611#define AWIN_PIO_PA_SPI3_PINS 0x000003e0 /* PA pins 9-5 */
 612#define AWIN_PIO_PA_SPI3_FUNC 3
 613#define AWIN_PIO_PA_SPI1_PINS 0x0000001f /* PA pins 0-4 */
 614#define AWIN_PIO_PA_SPI1_FUNC 3
 615#define AWIN_PIO_PA_UART1_PINS 0x0003fc00 /* PA pins 17-10 */
 616#define AWIN_PIO_PA_UART1_FUNC 4
 617#define AWIN_PIO_PA_UART2_PINS 0x0000000f /* PA pins 3-0 */
 618#define AWIN_PIO_PA_UART2_FUNC 4
 619#define AWIN_PIO_PA_GMAC_PINS 0x0003ffff /* PA pins 17-0 */
 620#define AWIN_PIO_PA_GMAC_FUNC 5
 621#define AWIN_PIO_PA_I2S1_PINS 0x0003c200 /* PA pins 17-14,9 */
 622#define AWIN_PIO_PA_I2S1_FUNC 5
 623
 624#define AWIN_PIO_PB_PINS 24
 625#define AWIN_PIO_PB_UART0_PINS 0x00c00000 /* PB pins 23-22 */
 626#define AWIN_PIO_PB_UART0_FUNC 2
 627#define AWIN_PIO_PB_TWI2_PINS 0x00300000 /* PB pins 21-20 */
 628#define AWIN_PIO_PB_TWI2_FUNC 2
 629#define AWIN_PIO_PB_TWI1_PINS 0x000c0000 /* PB pins 19-18 */
 630#define AWIN_PIO_PB_TWI1_FUNC 2
 631#define AWIN_PIO_PB_SPI2_PINS 0x0003e000 /* PB pins 17-13 */
 632#define AWIN_PIO_PB_SPI2_FUNC 2
 633#define AWIN_PIO_PB_I2S_PINS 0x00001fe0 /* PB pins 12-5 */
 634#define AWIN_PIO_PB_I2S_FUNC 2
 635#define AWIN_PIO_PB_IR0_PINS 0x00000018 /* PB pins 4-3 */
 636#define AWIN_PIO_PB_IR0_FUNC 2
 637#define AWIN_PIO_PB_PWN_PINS 0x00000004 /* PB pins 2-2 */
 638#define AWIN_PIO_PB_PWN_FUNC 2
 639#define AWIN_PIO_PB_TWI0_PINS 0x00000003 /* PB pins 1-0 */
 640#define AWIN_PIO_PB_TWI0_FUNC 2
 641#define AWIN_PIO_PB_IR1_PINS 0x00c00000 /* PB pins 23-22 */
 642#define AWIN_PIO_PB_IR1_FUNC 3
 643#define AWIN_PIO_PB_JTAG_PINS 0x0003c000 /* PB pins 17-14 */
 644#define AWIN_PIO_PB_JTAG_FUNC 3
 645#define AWIN_PIO_PB_AC97_PINS 0x000011e0 /* PB pins 12,8-5 */
 646#define AWIN_PIO_PB_AC97_FUNC 3
 647#define AWIN_PIO_PB_SPDIF_PINS 0x00003008 /* PB pins 13-12,3-3 */
 648#define AWIN_PIO_PB_SPDIF_FUNC 4
 649#define AWIN_PIO_PB_STANBYWFI_PINS 0x00000008 /* PB pins 3-3 */
 650#define AWIN_PIO_PB_STANBYWFI_FUNC 6
 651
 652#define AWIN_PIO_PC_PINS 25
 653#define AWIN_PIO_PC_NAND_PINS 0x017fffff /* PC pins 24,22-0 */
 654#define AWIN_PIO_PC_NAND_FUNC 2
 655#define AWIN_PIO_PC_SPI0_PINS 0x00800007 /* PC pins 23-23,3-0 */
 656#define AWIN_PIO_PC_SPI0_FUNC 3
 657#define AWIN_PIO_PC_SPI2_PINS 0x00f80000 /* PC pins 23-19 */
 658#define AWIN_PIO_PC_SPI2_FUNC 3
 659#define AWIN_PIO_PC_SDC2_PINS 0x00000fc0 /* PC pins 11-6 */
 660#define AWIN_PIO_PC_SDC2_FUNC 3
 661#define AWIN_PIO_PC_EINT_PINS 0x00780000 /* PC pins 22-19 */
 662#define AWIN_PIO_PC_EINT_FUNC 3
 663
 664#define AWIN_PIO_PD_PINS 28
 665#define AWIN_PIO_PD_LCD0_PINS 0x0fffffff /* PD pins 27-0 */
 666#define AWIN_PIO_PD_LCD0_FUNC 2
 667#define AWIN_PIO_PD_SMC_PINS 0x0fe00000 /* PD pins 27-21 */
 668#define AWIN_PIO_PD_SMC_FUNC 3
 669#define AWIN_PIO_PD_CSI1_PINS 0x00100000 /* PD pins 20-20 */
 670#define AWIN_PIO_PD_CSI1_FUNC 3
 671#define AWIN_PIO_PD_LVDS1_PINS 0x000ffc00 /* PD pins 19-10 */
 672#define AWIN_PIO_PD_LVDS1_FUNC 3
 673#define AWIN_PIO_PD_LVDS0_PINS 0x000003ff /* PD pins 9-0 */
 674#define AWIN_PIO_PD_LVDS0_FUNC 3
 675
 676#define AWIN_PIO_PE_PINS 12
 677#define AWIN_PIO_PE_TS_PINS 0x00000fff /* PE pins 11-0 */
 678#define AWIN_PIO_PE_TS_FUNC 2
 679#define AWIN_PIO_PE_CSI0_PINS 0x00000fff /* PE pins 11-0 */
 680#define AWIN_PIO_PE_CSI0_FUNC 3
 681#define AWIN_PIO_PE_SMC_PINS 0x00000020 /* PE pins 5-5 */
 682#define AWIN_PIO_PE_SMC_FUNC 4
 683
 684#define AWIN_PIO_PF_PINS 6
 685#define AWIN_PIO_PF_SDC0_PINS 0x0000003f /* PF pins 5-0 */
 686#define AWIN_PIO_PF_SDC0_FUNC 2
 687#define AWIN_PIO_PF_UART0_PINS 0x00000014 /* PF pins 4,2 */
 688#define AWIN_PIO_PF_UART0_FUNC 3
 689#define AWIN_PIO_PF_JTAG_PINS 0x0000002b /* PF pins 5,3,1-0 */
 690#define AWIN_PIO_PF_JTAG_FUNC 4
 691
 692#define AWIN_PIO_PG_PINS 12
 693#define AWIN_PIO_PG_TS1_PINS 0x00000fff /* PG pins 11-0 */
 694#define AWIN_PIO_PG_TS1_FUNC 2
 695#define AWIN_PIO_PG_CSI1_PINS 0x00000fff /* PG pins 11-0 */
 696#define AWIN_PIO_PG_CSI1_FUNC 3
 697#define AWIN_PIO_PG_UART4_PINS 0x00000c00 /* PG pins 11-10 */
 698#define AWIN_PIO_PG_UART4_FUNC 4
 699#define AWIN_PIO_PG_UART3_PINS 0x00000300 /* PG pins 9-8 */
 700#define AWIN_PIO_PG_UART3_FUNC 4
 701#define AWIN_PIO_PG_SDC1_PINS 0x0000003f /* PG pins 5-0 */
 702#define AWIN_PIO_PG_SDC1_FUNC 4
 703#define AWIN_PIO_PG_CSI0_PINS 0x00000ff0 /* PG pins 11-4 */
 704#define AWIN_PIO_PG_CSI0_FUNC 5
 705
 706#define AWIN_PIO_PH_PINS 28
 707#define AWIN_PIO_PH_LCD1_PINS 0x0fffffff /* PH pins 27-0 */
 708#define AWIN_PIO_PH_LCD1_FUNC 2
 709#define AWIN_PIO_PH_PATA_PINS 0x0fffffff /* PH pins 27-0 */
 710#define AWIN_PIO_PH_PATA_FUNC 3
 711#define AWIN_PIO_PH_EMAC_PINS 0x0fffcf00 /* PH pins 27-14,11-8 */
 712#define AWIN_PIO_PH_EMAC_FUNC 3
 713#define AWIN_PIO_PH_KP_PINS 0x0fcfcf00 /* PH pins 27-22,19-14,11-8 */
 714#define AWIN_PIO_PH_KP_FUNC 4
 715#define AWIN_PIO_PH_CAN_PINS 0x00300000 /* PH pins 21-20 */
 716#define AWIN_PIO_PH_CAN_FUNC 4
 717#define AWIN_PIO_PH_PS21_PINS 0x00003000 /* PH pins 13-12 */
 718#define AWIN_PIO_PH_PS21_FUNC 4
 719#define AWIN_PIO_PH_UART5_PINS 0x000000c0 /* PH pins 7-6 */
 720#define AWIN_PIO_PH_UART5_FUNC 4
 721#define AWIN_PIO_PH_UART4_PINS 0x00000030 /* PH pins 5-4 */
 722#define AWIN_PIO_PH_UART4_FUNC 4
 723#define AWIN_PIO_PH_UART3_PINS 0x0000000f /* PH pins 3-0 */
 724#define AWIN_PIO_PH_UART3_FUNC 4
 725#define AWIN_PIO_PH_SDC1_PINS 0x0fc00000 /* PH pins 27-23 */
 726#define AWIN_PIO_PH_SDC1_FUNC 5
 727#define AWIN_PIO_PH_SMC_PINS 0x000fe000 /* PH pins 19-13 */
 728#define AWIN_PIO_PH_SMC_FUNC 5
 729#define AWIN_PIO_PH_MS_PINS 0x00000fc0 /* PH pins 11-6 */
 730#define AWIN_PIO_PH_MS_FUNC 5
 731#define AWIN_PIO_PH_EINT_PINS 0x003fffff /* PH pins 21-0 */
 732#define AWIN_PIO_PH_EINT_FUNC 6
 733#define AWIN_PIO_PH_CSI1_PINS 0x0fffffff /* PH pins 27-0 */
 734#define AWIN_PIO_PH_CSI1_FUNC 7
 735
 736#define AWIN_PIO_PI_PINS 22
 737#define AWIN_PIO_PI_PS20_PINS 0x00300000 /* PI pins 21-20 */
 738#define AWIN_PIO_PI_PS20_FUNC 2
 739#define AWIN_PIO_PI_SPI1_PINS 0x000f0000 /* PI pins 7-4 */
 740#define AWIN_PIO_PI_SPI1_FUNC 2
 741#define AWIN_PIO_PI_SDC3_PINS 0x000003f0 /* PI pins 9-4 */
 742#define AWIN_PIO_PI_SDC3_FUNC 2
 743#define AWIN_PIO_PI_PWM1_PINS 0x00000008 /* PI pins 3-3 */
 744#define AWIN_PIO_PI_PWM1_FUNC 2
 745#define AWIN_PIO_PI_UART7_PINS 0x00300000 /* PI pins 21-20 */
 746#define AWIN_PIO_PI_UART7_FUNC 3
 747#define AWIN_PIO_PI_UART2_PINS 0x000f0000 /* PI pins 19-16 */
 748#define AWIN_PIO_PI_UART2_FUNC 3
 749#define AWIN_PIO_PI_PS21_PINS 0x0000c000 /* PI pins 15-14 */
 750#define AWIN_PIO_PI_PS21_FUNC 3
 751#define AWIN_PIO_PI_UART6_PINS 0x00003000 /* PI pins 13-12 */
 752#define AWIN_PIO_PI_UART6_FUNC 3
 753#define AWIN_PIO_PI_UART5_PINS 0x00000c00 /* PI pins 11-10 */
 754#define AWIN_PIO_PI_UART5_FUNC 3
 755#define AWIN_PIO_PI_TWI4_PINS 0x0000000c /* PI pins 3-2 */
 756#define AWIN_PIO_PI_TWI4_FUNC 3
 757#define AWIN_PIO_PI_TWI3_PINS 0x00000003 /* PI pins 1-0 */
 758#define AWIN_PIO_PI_TWI3_FUNC 3
 759#define AWIN_PIO_PI_HSXX_PINS 0x00300000 /* PI pins 21-20 */
 760#define AWIN_PIO_PI_HSXX_FUNC 4
 761#define AWIN_PIO_PI_TCLKIN_PINS 0x0000c000 /* PI pins 15-14 */
 762#define AWIN_PIO_PI_TCLKIN_FUNC 4
 763#define AWIN_PIO_PI_CLKOUTB_PINS 0x00002000 /* PI pins 13-13 */
 764#define AWIN_PIO_PI_CLKOUTB_FUNC 4
 765#define AWIN_PIO_PI_CLKOUTA_PINS 0x00002000 /* PI pins 12-12 */
 766#define AWIN_PIO_PI_CLKOUTA_FUNC 4
 767#define AWIN_PIO_PI_EINT_PINS 0x000ffc00 /* PI pins 19-10 */
 768#define AWIN_PIO_PI_EINT_FUNC 6
 769
411/* Standard Timer (A10) */ 770/* Standard Timer (A10) */
412#define AWIN_TMR_IRQ_EN_REG 0x0000 771#define AWIN_TMR_IRQ_EN_REG 0x0000
413#define AWIN_TMR_IRQ_STA_REG 0x0004 772#define AWIN_TMR_IRQ_STA_REG 0x0004
414#define AWIN_TMR0_CTRL_REG 0x0010 773#define AWIN_TMR0_CTRL_REG 0x0010
415#define AWIN_TMR0_INTV_VALUE_REG 0x0014 774#define AWIN_TMR0_INTV_VALUE_REG 0x0014
416#define AWIN_TMR0_CUR_VALUE_REG 0x0018 775#define AWIN_TMR0_CUR_VALUE_REG 0x0018
417#define AWIN_TMR1_CTRL_REG 0x0020 776#define AWIN_TMR1_CTRL_REG 0x0020
418#define AWIN_TMR1_INTV_VALUE_REG 0x0024 777#define AWIN_TMR1_INTV_VALUE_REG 0x0024
419#define AWIN_TMR1_CUR_VALUE_REG 0x0028 778#define AWIN_TMR1_CUR_VALUE_REG 0x0028
420#define AWIN_TMR2_CTRL_REG 0x0030 779#define AWIN_TMR2_CTRL_REG 0x0030
421#define AWIN_TMR2_INTV_VALUE_REG 0x0034 780#define AWIN_TMR2_INTV_VALUE_REG 0x0034
422#define AWIN_TMR2_CUR_VALUE_REG 0x0038 781#define AWIN_TMR2_CUR_VALUE_REG 0x0038
423#define AWIN_TMR3_CTRL_REG 0x0040 782#define AWIN_TMR3_CTRL_REG 0x0040
@@ -441,26 +800,47 @@ @@ -441,26 +800,47 @@
441#define AWIN_RTC_YY_MM_DD_REG 0x0104 800#define AWIN_RTC_YY_MM_DD_REG 0x0104
442#define AWIN_RTC_HH_MM_SS_REG 0x0108 801#define AWIN_RTC_HH_MM_SS_REG 0x0108
443#define AWIN_DD_HH_MM_SS_REG 0x010C 802#define AWIN_DD_HH_MM_SS_REG 0x010C
444#define AWIN_ALARM_WK_HH_MM_SS_REG 0x0110 803#define AWIN_ALARM_WK_HH_MM_SS_REG 0x0110
445#define AWIN_ALARM_EN_REG 0x0114 804#define AWIN_ALARM_EN_REG 0x0114
446#define AWIN_ALARM_IRQ_EN_REG 0x0118 805#define AWIN_ALARM_IRQ_EN_REG 0x0118
447#define AWIN_ALARM_IRQ_STA_REG 0x011C 806#define AWIN_ALARM_IRQ_STA_REG 0x011C
448#define AWIN_TMR_GP_DATA0_REG 0x0120 807#define AWIN_TMR_GP_DATA0_REG 0x0120
449#define AWIN_TMR_GP_DATA1_REG 0x0124 808#define AWIN_TMR_GP_DATA1_REG 0x0124
450#define AWIN_TMR_GP_DATA2_REG 0x0128 809#define AWIN_TMR_GP_DATA2_REG 0x0128
451#define AWIN_TMR_GP_DATA3_REG 0x012C 810#define AWIN_TMR_GP_DATA3_REG 0x012C
452#define AWIN_CPU_CFG_REG 0x0140 811#define AWIN_CPU_CFG_REG 0x0140
453 812
 813#define AWIN_TMR_IRQ_WDOG __BIT(8)
 814#define AWIN_TMR_IRQ_TIMER5 __BIT(5)
 815#define AWIN_TMR_IRQ_TIMER4 __BIT(4)
 816#define AWIN_TMR_IRQ_TIMER3 __BIT(3)
 817#define AWIN_TMR_IRQ_TIMER2 __BIT(2)
 818#define AWIN_TMR_IRQ_TIMER1 __BIT(1)
 819#define AWIN_TMR_IRQ_TIMER0 __BIT(0)
 820
 821#define AWIN_TMR_CTRL_SINGLE_SHOT __BIT(7)
 822#define AWIN_TMR_CTRL_PRESCALE __BITS(6,4)
 823#define AWIN_TMR_CTRL_CLK_SRC __BITS(3,2)
 824#define AWIN_TMR_CTRL_CLK_SRC_LOSC 0
 825#define AWIN_TMR_CTRL_CLK_SRC_OSC24M 1
 826#define AWIN_TMR_CTRL_CLK_SRC_PLL6_DIV6 2
 827#define AWIN_TMR_CTRL_RELOAD __BIT(1)
 828#define AWIN_TMR_CTRL_ENABLE __BIT(0)
 829
 830#define AWIN_CNT64_CTRL_PLL6_DIV6 __BIT(2)
 831#define AWIN_CNT64_CTRL_RL_ENABLE __BIT(1)
 832#define AWIN_CNT64_CTRL_CLR_ENABLE __BIT(0)
 833
454#define AWIN_WDOG_CTRL_RSTART __BIT(1) 834#define AWIN_WDOG_CTRL_RSTART __BIT(1)
455#define AWIN_WDOG_MODE_INTV __BITS(6,3) 835#define AWIN_WDOG_MODE_INTV __BITS(6,3)
456#define AWIN_WDOG_MODE_INTV_HALFSEC 0 836#define AWIN_WDOG_MODE_INTV_HALFSEC 0
457#define AWIN_WDOG_MODE_INTV_1SEC 1 837#define AWIN_WDOG_MODE_INTV_1SEC 1
458#define AWIN_WDOG_MODE_INTV_2SEC 2 838#define AWIN_WDOG_MODE_INTV_2SEC 2
459#define AWIN_WDOG_MODE_INTV_3SEC 3 839#define AWIN_WDOG_MODE_INTV_3SEC 3
460#define AWIN_WDOG_MODE_INTV_4SEC 4 840#define AWIN_WDOG_MODE_INTV_4SEC 4
461#define AWIN_WDOG_MODE_INTV_5SEC 5 841#define AWIN_WDOG_MODE_INTV_5SEC 5
462#define AWIN_WDOG_MODE_INTV_6SEC 6 842#define AWIN_WDOG_MODE_INTV_6SEC 6
463#define AWIN_WDOG_MODE_INTV_8SEC 7 843#define AWIN_WDOG_MODE_INTV_8SEC 7
464#define AWIN_WDOG_MODE_INTV_10SEC 8 844#define AWIN_WDOG_MODE_INTV_10SEC 8
465#define AWIN_WDOG_MODE_INTV_12SEC 9 845#define AWIN_WDOG_MODE_INTV_12SEC 9
466#define AWIN_WDOG_MODE_INTV_14SEC 10 846#define AWIN_WDOG_MODE_INTV_14SEC 10
@@ -489,27 +869,27 @@ @@ -489,27 +869,27 @@
489#define AWIN_SPI_BC_REG 0x0020 869#define AWIN_SPI_BC_REG 0x0020
490#define AWIN_SPI_TC_REG 0x0024 870#define AWIN_SPI_TC_REG 0x0024
491#define AWIN_SPI_FIFO_STA_REG 0x0028 871#define AWIN_SPI_FIFO_STA_REG 0x0028
492 872
493/* A20 CPU Configuration definitions */ 873/* A20 CPU Configuration definitions */
494#define AWIN_CPU0_RST_CTRL_REG 0x0040 874#define AWIN_CPU0_RST_CTRL_REG 0x0040
495#define AWIN_CPU0_CTRL_REG 0x0044 875#define AWIN_CPU0_CTRL_REG 0x0044
496#define AWIN_CPU0_STATUS_REG 0x0048 876#define AWIN_CPU0_STATUS_REG 0x0048
497#define AWIN_CPU1_RST_CTRL_REG 0x0080 877#define AWIN_CPU1_RST_CTRL_REG 0x0080
498#define AWIN_CPU1_CTRL_REG 0x0084 878#define AWIN_CPU1_CTRL_REG 0x0084
499#define AWIN_CPU1_STATUS_REG 0x0088 879#define AWIN_CPU1_STATUS_REG 0x0088
500#define AWIN_GENER_CTRL_REG 0x0184 880#define AWIN_GENER_CTRL_REG 0x0184
501#define AWIN_EVENT_IN_REG 0x0190 881#define AWIN_EVENT_IN_REG 0x0190
502#define AWIN_PRIVATE_REG 0x01a4 882#define AWIN_PRIVATE_REG 0x01A4
503#define AWIN_IDLE_CNT0_LOW_REG 0x0200 883#define AWIN_IDLE_CNT0_LOW_REG 0x0200
504#define AWIN_IDLE_CNT0_HIGH_REG 0x0204 884#define AWIN_IDLE_CNT0_HIGH_REG 0x0204
505#define AWIN_IDLE_CNT0_CTRL_REG 0x0208 885#define AWIN_IDLE_CNT0_CTRL_REG 0x0208
506#define AWIN_IDLE_CNT1_LOW_REG 0x0210 886#define AWIN_IDLE_CNT1_LOW_REG 0x0210
507#define AWIN_IDLE_CNT1_HIGH_REG 0x0214 887#define AWIN_IDLE_CNT1_HIGH_REG 0x0214
508#define AWIN_IDLE_CNT1_CTRL_REG 0x0218 888#define AWIN_IDLE_CNT1_CTRL_REG 0x0218
509#define AWIN_OSC24M_CNT64_CTRL_REG 0x0280 889#define AWIN_OSC24M_CNT64_CTRL_REG 0x0280
510#define AWIN_OSC24M_CNT64_LOW_REG 0x0284 890#define AWIN_OSC24M_CNT64_LOW_REG 0x0284
511#define AWIN_OSC24M_CNT64_HIGH_REG 0x0288 891#define AWIN_OSC24M_CNT64_HIGH_REG 0x0288
512#define AWIN_LOSC_CNT64_CTRL_REG 0x0290 892#define AWIN_LOSC_CNT64_CTRL_REG 0x0290
513#define AWIN_LOSC_CNT64_LOW_REG 0x0294 893#define AWIN_LOSC_CNT64_LOW_REG 0x0294
514#define AWIN_LOSC_CNT64_HIGH_REG 0x0298 894#define AWIN_LOSC_CNT64_HIGH_REG 0x0298
515 895
cvs diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/Attic/awin_var.h (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_var.h 2013/09/04 17:45:40 1.3
+++ src/sys/arch/arm/allwinner/Attic/awin_var.h 2013/09/07 00:35:52 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: awin_var.h,v 1.3 2013/09/04 17:45:40 matt Exp $ */ 1/* $NetBSD: awin_var.h,v 1.4 2013/09/07 00:35:52 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2013 The NetBSD Foundation, Inc. 3 * Copyright (c) 2013 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -43,27 +43,40 @@ struct awin_locators { @@ -43,27 +43,40 @@ struct awin_locators {
43#define AWINIO_INTR_DEFAULT 0 43#define AWINIO_INTR_DEFAULT 0
44 int loc_flags; 44 int loc_flags;
45#define AWINIO_REQUIRED __BIT(8) 45#define AWINIO_REQUIRED __BIT(8)
46#define AWINIO_ONLY __BITS(7,0) 46#define AWINIO_ONLY __BITS(7,0)
47#define AWINIO_ONLY_A20 __BIT(1) 47#define AWINIO_ONLY_A20 __BIT(1)
48#define AWINIO_ONLY_A10 __BIT(0) 48#define AWINIO_ONLY_A10 __BIT(0)
49}; 49};
50 50
51struct awinio_attach_args { 51struct awinio_attach_args {
52 struct awin_locators aio_loc; 52 struct awin_locators aio_loc;
53 bus_space_tag_t aio_core_bst; 53 bus_space_tag_t aio_core_bst;
54 bus_space_tag_t aio_core_a4x_bst; 54 bus_space_tag_t aio_core_a4x_bst;
55 bus_space_handle_t aio_core_bsh; 55 bus_space_handle_t aio_core_bsh;
 56 bus_space_handle_t aio_ccm_bsh;
56 bus_dma_tag_t aio_dmat; 57 bus_dma_tag_t aio_dmat;
57}; 58};
58 59
 60struct awin_gpio_pinset {
 61 uint8_t pinset_group;
 62 uint8_t pinset_func;
 63 uint32_t pinset_mask;
 64};
 65
59extern struct bus_space awin_bs_tag; 66extern struct bus_space awin_bs_tag;
60extern struct bus_space awin_a4x_bs_tag; 67extern struct bus_space awin_a4x_bs_tag;
61extern bus_space_handle_t awin_core_bsh; 68extern bus_space_handle_t awin_core_bsh;
62extern struct arm32_bus_dma_tag awin_dma_tag; 69extern struct arm32_bus_dma_tag awin_dma_tag;
63 70
64psize_t awin_memprobe(void); 71psize_t awin_memprobe(void);
65void awin_bootstrap(vaddr_t, vaddr_t);  72void awin_bootstrap(vaddr_t, vaddr_t);
 73void awin_pll6_enable(void);
 74
 75void awin_gpio_init(void);
 76bool awin_gpio_pinset_available(const struct awin_gpio_pinset *);
 77void awin_gpio_pinset_acquire(const struct awin_gpio_pinset *);
 78void awin_gpio_pinset_release(const struct awin_gpio_pinset *);
66 79
67void awin_wdog_reset(void); 80void awin_wdog_reset(void);
68 81
69#endif /* _ARM_ALLWINNER_AWIN_VAR_H_ */ 82#endif /* _ARM_ALLWINNER_AWIN_VAR_H_ */
cvs diff -r1.3 -r1.4 src/sys/arch/arm/allwinner/Attic/files.awin (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/files.awin 2013/09/04 17:45:40 1.3
+++ src/sys/arch/arm/allwinner/Attic/files.awin 2013/09/07 00:35:52 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1# $NetBSD: files.awin,v 1.3 2013/09/04 17:45:40 matt Exp $ 1# $NetBSD: files.awin,v 1.4 2013/09/07 00:35:52 matt Exp $
2# 2#
3# Configuration info for Allwinner ARM Peripherals 3# Configuration info for Allwinner ARM Peripherals
4# 4#
5 5
6include "arch/arm/pic/files.pic" 6include "arch/arm/pic/files.pic"
7include "arch/arm/cortex/files.cortex" 7include "arch/arm/cortex/files.cortex"
8 8
9file arch/arm/arm32/arm32_boot.c 9file arch/arm/arm32/arm32_boot.c
10file arch/arm/arm32/arm32_kvminit.c 10file arch/arm/arm32/arm32_kvminit.c
11file arch/arm/arm32/arm32_reboot.c 11file arch/arm/arm32/arm32_reboot.c
12file arch/arm/arm32/irq_dispatch.S 12file arch/arm/arm32/irq_dispatch.S
13 13
14file arch/arm/allwinner/awin_board.c 14file arch/arm/allwinner/awin_board.c
@@ -44,30 +44,30 @@ file arch/arm/allwinner/awin_wdt.c awin @@ -44,30 +44,30 @@ file arch/arm/allwinner/awin_wdt.c awin
44 44
45# A10 Timers 45# A10 Timers
46device awintmr 46device awintmr
47attach awintmr at awinio with awin_tmr 47attach awintmr at awinio with awin_tmr
48file arch/arm/allwinner/awin_tmr.c awin_tmr 48file arch/arm/allwinner/awin_tmr.c awin_tmr
49 49
50# A10/A20 UART 50# A10/A20 UART
51attach com at awinio with awin_com 51attach com at awinio with awin_com
52file arch/arm/allwinner/awin_com.c awin_com 52file arch/arm/allwinner/awin_com.c awin_com
53 53
54# A10/A20 GPIO 54# A10/A20 GPIO
55device awingpio : gpiobus 55device awingpio : gpiobus
56attach awingpio at awinio with awin_gpio 56attach awingpio at awinio with awin_gpio
57file arch/arm/allwinner/awin_gpio.c awin_gpio 57file arch/arm/allwinner/awin_gpio.c awin_gpio | awin_io needs-flag
58 58
59# A10/A20 TWI (IIC) 59# A10/A20 TWI (IIC)
60device awiniic : i2cbus, i2cexec 60device awiniic : i2cbus, i2cexec, mvi2c
61attach awiniic at awinio with awin_twi 61attach awiniic at awinio with awin_twi
62file arch/arm/allwinner/awin_twi.c awin_twi 62file arch/arm/allwinner/awin_twi.c awin_twi
63 63
64# A10/A20 NAND controller 64# A10/A20 NAND controller
65device awinnand : nandbus 65device awinnand : nandbus
66attach awinnand at awinio with awin_nand 66attach awinnand at awinio with awin_nand
67file arch/arm/allwinner/awin_nand.c awin_nand 67file arch/arm/allwinner/awin_nand.c awin_nand
68 68
69# A10/A20 Security System 69# A10/A20 Security System
70device awincrypto : opencrypto 70device awincrypto : opencrypto
71attach awincrypto at awinio with awin_crypto 71attach awincrypto at awinio with awin_crypto
72file arch/arm/allwinner/awin_crypto.c awin_crypto 72file arch/arm/allwinner/awin_crypto.c awin_crypto
73 73