| @@ -214,26 +214,107 @@ | | | @@ -214,26 +214,107 @@ |
| 214 | #define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6) | | 214 | #define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6) |
| 215 | #define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3 | | 215 | #define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3 |
| 216 | #define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1 | | 216 | #define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1 |
| 217 | #define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0 | | 217 | #define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0 |
| 218 | #define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10) | | 218 | #define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10) |
| 219 | | | 219 | |
| 220 | #define AWIN_DRAM_HPCR_READ_CNT_EN __BIT(31) | | 220 | #define AWIN_DRAM_HPCR_READ_CNT_EN __BIT(31) |
| 221 | #define AWIN_DRAM_HPCR_RWRITE_CNT_EN __BIT(30) | | 221 | #define AWIN_DRAM_HPCR_RWRITE_CNT_EN __BIT(30) |
| 222 | #define AWIN_DRAM_HPCR_COMMAND_NUM __BIT(8) | | 222 | #define AWIN_DRAM_HPCR_COMMAND_NUM __BIT(8) |
| 223 | #define AWIN_DRAM_HPCR_WAIT_STATE __BIT(4) | | 223 | #define AWIN_DRAM_HPCR_WAIT_STATE __BIT(4) |
| 224 | #define AWIN_DRAM_HPCR_PRIORITY_LEVEL __BIT(2) | | 224 | #define AWIN_DRAM_HPCR_PRIORITY_LEVEL __BIT(2) |
| 225 | #define AWIN_DRAM_HPCR_ACCESS_EN __BIT(0) | | 225 | #define AWIN_DRAM_HPCR_ACCESS_EN __BIT(0) |
| 226 | | | 226 | |
| | | 227 | #define AWIN_NFC_CTL_REG 0x0000 |
| | | 228 | #define AWIN_NFC_ST_REG 0x0004 |
| | | 229 | #define AWIN_NFC_INT_REG 0x0008 |
| | | 230 | #define AWIN_NFC_TIMING_CTL_REG 0x000C |
| | | 231 | #define AWIN_NFC_TIMING_CFG_REG 0x0010 |
| | | 232 | #define AWIN_NFC_ADDR_LOW_REG 0x0014 |
| | | 233 | #define AWIN_NFC_ADDR_HIGH_REG 0x0018 |
| | | 234 | #define AWIN_NFC_SECTOR_NUM_REG 0x001C |
| | | 235 | #define AWIN_NFC_CNT_REG 0x0020 |
| | | 236 | #define AWIN_NFC_CMD_REG 0x0024 |
| | | 237 | #define AWIN_NFC_READ_CMD_SET_REG 0x0028 |
| | | 238 | #define AWIN_NFC_WRITE_CMD_SET_REG 0x002C |
| | | 239 | #define AWIN_NFC_IO_DATA_REG 0x0030 |
| | | 240 | #define AWIN_NFC_ECC_CTL_REG 0x0034 |
| | | 241 | #define AWIN_NFC_ECC_ST_REG 0x0038 |
| | | 242 | #define AWIN_NFC_DEBUG_REG 0x003C |
| | | 243 | #define AWIN_NFC_ECC_CNT0_REG 0x0040 |
| | | 244 | #define AWIN_NFC_ECC_CNT1_REG 0x0044 |
| | | 245 | #define AWIN_NFC_ECC_CNT2_REG 0x0048 |
| | | 246 | #define AWIN_NFC_ECC_CNT3_REG 0x004C |
| | | 247 | #define AWIN_NFC_USER_DB_REG 0x0050 |
| | | 248 | #define AWIN_NFC_RAM0_REG 0x0400 |
| | | 249 | #define AWIN_NFC_RAM1_REG 0x0800 |
| | | 250 | |
| | | 251 | #define AWIN_NFC_CTL_DEBUG __BIT(31) |
| | | 252 | #define AWIN_NFC_CTL_CE_SEL __BITS(26,24) |
| | | 253 | #define AWIN_NFC_CTL_RAM_METHOD __BIT(14) |
| | | 254 | #define AWIN_NFC_CTL_SAM __BIT(12) |
| | | 255 | #define AWIN_NFC_CTL_PAGE_SIZE __BITS(11,8) |
| | | 256 | #define AWIN_NFC_CTL_PAGE_SIZE_1K 0 |
| | | 257 | #define AWIN_NFC_CTL_PAGE_SIZE_2K 1 |
| | | 258 | #define AWIN_NFC_CTL_PAGE_SIZE_4K 2 |
| | | 259 | #define AWIN_NFC_CTL_PAGE_SIZE_8K 3 |
| | | 260 | #define AWIN_NFC_CTL_PAGE_SIZE_16K 4 |
| | | 261 | #define AWIN_NFC_CTL_CE_CTL1 __BIT(7) |
| | | 262 | #define AWIN_NFC_CTL_CE_CTL0 __BIT(6) |
| | | 263 | #define AWIN_NFC_CTL_RB_SEL1 __BIT(3) |
| | | 264 | #define AWIN_NFC_CTL_BUS_WIDTH16 __BIT(2) |
| | | 265 | #define AWIN_NFC_CTL_RESET __BIT(1) |
| | | 266 | #define AWIN_NFC_CTL_EN __BIT(0) |
| | | 267 | |
| | | 268 | #define AWIN_NFC_ST_STATE3 __BIT(11) |
| | | 269 | #define AWIN_NFC_ST_STATE2 __BIT(10) |
| | | 270 | #define AWIN_NFC_ST_STATE1 __BIT(9) |
| | | 271 | #define AWIN_NFC_ST_STATE0 __BIT(8) |
| | | 272 | #define AWIN_NFC_ST_MATCH_INT __BIT(5) |
| | | 273 | #define AWIN_NFC_ST_STAT __BIT(4) |
| | | 274 | #define AWIN_MFC_ST_CMD_FIFO __BIT(3) |
| | | 275 | #define AWIN_MFC_ST_DMA_INT __BIT(2) |
| | | 276 | #define AWIN_MFC_ST_CMD_INT __BIT(1) |
| | | 277 | #define AWIN_MFC_ST_RB_B2R __BIT(0) |
| | | 278 | |
| | | 279 | #define AWIN_NFC_INT_DMA_EN __BIT(2) |
| | | 280 | #define AWIN_NFC_INT_CMD_EN __BIT(1) |
| | | 281 | #define AWIN_NFC_INT_B2R_EN __BIT(0) |
| | | 282 | |
| | | 283 | #define AWIN_NFC_CMD_CMD_TYPE __BITS(31,30) |
| | | 284 | #define AWIN_NFC_CMD_SEND_CMD3 __BIT(29) |
| | | 285 | #define AWIN_NFC_CMD_SEND_CMD2 __BIT(28) |
| | | 286 | #define AWIN_NFC_CMD_ROW_AUTO_INC __BIT(27) |
| | | 287 | #define AWIN_NFC_CMD_DATA_SWAP __BIT(26) |
| | | 288 | #define AWIN_NFC_CMD_SEQ __BIT(25) |
| | | 289 | #define AWIN_NFC_CMD_SEND_CMD1 __BIT(24) |
| | | 290 | #define AWIN_NFC_CMD_WAIT_FLAG __BIT(23) |
| | | 291 | #define AWIN_NFC_CMD_SEND_CMD0 __BIT(22) |
| | | 292 | #define AWIN_NFC_CMD_DATA_TRANS __BIT(21) |
| | | 293 | #define AWIN_NFC_CMD_XS_DIR __BIT(20) |
| | | 294 | #define AWIN_NFC_CMD_SEND_ADDR __BIT(19) |
| | | 295 | #define AWIN_NFC_CMD_ADDR_NUM __BITS(18,16) |
| | | 296 | #define AWIN_NFC_CMD_HIGH __BITS(15,8) |
| | | 297 | #define AWIN_NFC_CMD_LOW __BITS(7,0) |
| | | 298 | |
| | | 299 | #define AWIN_NFC_READ_CMD_SET_RAMDOM_CMD1 __BITS(23,16) |
| | | 300 | #define AWIN_NFC_READ_CMD_SET_RANDOM_CMD0 __BITS(15,8) |
| | | 301 | #define AWIN_NFC_READ_CMD_SET_CMD __BITS(7,0) |
| | | 302 | |
| | | 303 | #define AWIN_NFC_WRITE_CMD_SET_RANDOM_CMD0 __BITS(15,8) |
| | | 304 | #define AWIN_NFC_WRITE_CMD_SET_CMD __BITS(7,0) |
| | | 305 | |
| | | 306 | #define AWIN_ECC_CTL_EN __BIT(0) |
| | | 307 | |
| 227 | #define AWIN_EMAC_CTL_REG 0x0000 | | 308 | #define AWIN_EMAC_CTL_REG 0x0000 |
| 228 | #define AWIN_EMAC_TX_MODE_REG 0x0004 | | 309 | #define AWIN_EMAC_TX_MODE_REG 0x0004 |
| 229 | #define AWIN_EMAC_TX_FLOW_REG 0x0008 | | 310 | #define AWIN_EMAC_TX_FLOW_REG 0x0008 |
| 230 | #define AWIN_EMAC_TX_CTL0_REG 0x000C | | 311 | #define AWIN_EMAC_TX_CTL0_REG 0x000C |
| 231 | #define AWIN_EMAC_TX_CTL1_REG 0x0010 | | 312 | #define AWIN_EMAC_TX_CTL1_REG 0x0010 |
| 232 | #define AWIN_EMAC_TX_INS_REG 0x0014 | | 313 | #define AWIN_EMAC_TX_INS_REG 0x0014 |
| 233 | #define AWIN_EMAC_TX_PL0_REG 0x0018 | | 314 | #define AWIN_EMAC_TX_PL0_REG 0x0018 |
| 234 | #define AWIN_EMAC_TX_PL1_REG 0x001C | | 315 | #define AWIN_EMAC_TX_PL1_REG 0x001C |
| 235 | #define AWIN_EMAC_TX_STA_REG 0x0020 | | 316 | #define AWIN_EMAC_TX_STA_REG 0x0020 |
| 236 | #define AWIN_EMAC_TX_IO_DATA0_REG 0x0024 | | 317 | #define AWIN_EMAC_TX_IO_DATA0_REG 0x0024 |
| 237 | #define AWIN_EMAC_TX_IO_DATA1_REG 0x0028 | | 318 | #define AWIN_EMAC_TX_IO_DATA1_REG 0x0028 |
| 238 | #define AWIN_EMAC_TX_TSVL0_REG 0x002C | | 319 | #define AWIN_EMAC_TX_TSVL0_REG 0x002C |
| 239 | #define AWIN_EMAC_TX_TSVH0_REG 0x0030 | | 320 | #define AWIN_EMAC_TX_TSVH0_REG 0x0030 |
| @@ -406,27 +487,27 @@ | | | @@ -406,27 +487,27 @@ |
| 406 | #define AWIN_AHB_GATING0_ACE __BIT(16) | | 487 | #define AWIN_AHB_GATING0_ACE __BIT(16) |
| 407 | #define AWIN_AHB_GATING0_SDRAM __BIT(14) | | 488 | #define AWIN_AHB_GATING0_SDRAM __BIT(14) |
| 408 | #define AWIN_AHB_GATING0_NAND __BIT(13) | | 489 | #define AWIN_AHB_GATING0_NAND __BIT(13) |
| 409 | #define AWIN_AHB_GATING0_NC12 __BIT(12) | | 490 | #define AWIN_AHB_GATING0_NC12 __BIT(12) |
| 410 | #define AWIN_AHB_GATING0_SDMMC3 __BIT(11) | | 491 | #define AWIN_AHB_GATING0_SDMMC3 __BIT(11) |
| 411 | #define AWIN_AHB_GATING0_SDMMC2 __BIT(10) | | 492 | #define AWIN_AHB_GATING0_SDMMC2 __BIT(10) |
| 412 | #define AWIN_AHB_GATING0_SDMMC1 __BIT(9) | | 493 | #define AWIN_AHB_GATING0_SDMMC1 __BIT(9) |
| 413 | #define AWIN_AHB_GATING0_SDMMC0 __BIT(8) | | 494 | #define AWIN_AHB_GATING0_SDMMC0 __BIT(8) |
| 414 | #define AWIN_AHB_GATING0_BIST __BIT(7) | | 495 | #define AWIN_AHB_GATING0_BIST __BIT(7) |
| 415 | #define AWIN_AHB_GATING0_DMA __BIT(6) | | 496 | #define AWIN_AHB_GATING0_DMA __BIT(6) |
| 416 | #define AWIN_AHB_GATING0_SS __BIT(5) | | 497 | #define AWIN_AHB_GATING0_SS __BIT(5) |
| 417 | #define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4) | | 498 | #define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4) |
| 418 | #define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3) | | 499 | #define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3) |
| 419 | #define AWIN_AHB_GATING0_USB_OHCI0 __BIT(1) | | 500 | #define AWIN_AHB_GATING0_USB_OHCI0 __BIT(2) |
| 420 | #define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1) | | 501 | #define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1) |
| 421 | #define AWIN_AHB_GATING0_USB0 __BIT(0) | | 502 | #define AWIN_AHB_GATING0_USB0 __BIT(0) |
| 422 | | | 503 | |
| 423 | #define AWIN_AHB_GATING1_MALI400 __BIT(20) | | 504 | #define AWIN_AHB_GATING1_MALI400 __BIT(20) |
| 424 | #define AWIN_AHB_GATING1_MP __BIT(18) | | 505 | #define AWIN_AHB_GATING1_MP __BIT(18) |
| 425 | #define AWIN_AHB_GATING1_GMAC __BIT(17) | | 506 | #define AWIN_AHB_GATING1_GMAC __BIT(17) |
| 426 | #define AWIN_AHB_GATING1_DE_FE1 __BIT(15) | | 507 | #define AWIN_AHB_GATING1_DE_FE1 __BIT(15) |
| 427 | #define AWIN_AHB_GATING1_DE_FE0 __BIT(14) | | 508 | #define AWIN_AHB_GATING1_DE_FE0 __BIT(14) |
| 428 | #define AWIN_AHB_GATING1_DE_BE1 __BIT(13) | | 509 | #define AWIN_AHB_GATING1_DE_BE1 __BIT(13) |
| 429 | #define AWIN_AHB_GATING1_DE_BE0 __BIT(12) | | 510 | #define AWIN_AHB_GATING1_DE_BE0 __BIT(12) |
| 430 | #define AWIN_AHB_GATING1_HDMI __BIT(11) | | 511 | #define AWIN_AHB_GATING1_HDMI __BIT(11) |
| 431 | #define AWIN_AHB_GATING1_CSI1 __BIT(9) | | 512 | #define AWIN_AHB_GATING1_CSI1 __BIT(9) |
| 432 | #define AWIN_AHB_GATING1_CSI0 __BIT(8) | | 513 | #define AWIN_AHB_GATING1_CSI0 __BIT(8) |
| @@ -522,38 +603,38 @@ | | | @@ -522,38 +603,38 @@ |
| 522 | #define AWIN_CLK_OUT_SRC_SEL __BITS(25,24) | | 603 | #define AWIN_CLK_OUT_SRC_SEL __BITS(25,24) |
| 523 | #define AWIN_CLK_OUT_SRC_SEL_32K 0 | | 604 | #define AWIN_CLK_OUT_SRC_SEL_32K 0 |
| 524 | #define AWIN_CLK_OUT_SRC_SEL_LOSC 1 | | 605 | #define AWIN_CLK_OUT_SRC_SEL_LOSC 1 |
| 525 | #define AWIN_CLK_OUT_SRC_SEL_OSC24M 2 | | 606 | #define AWIN_CLK_OUT_SRC_SEL_OSC24M 2 |
| 526 | #define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20) | | 607 | #define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20) |
| 527 | #define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8) | | 608 | #define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8) |
| 528 | | | 609 | |
| 529 | /* USB device offsets */ | | 610 | /* USB device offsets */ |
| 530 | #define AWIN_USB0_PHY_CSR_REG 0x0404 | | 611 | #define AWIN_USB0_PHY_CSR_REG 0x0404 |
| 531 | #define AWIN_EHCI_OFFSET 0x0000 | | 612 | #define AWIN_EHCI_OFFSET 0x0000 |
| 532 | #define AWIN_EHCI_SIZE 0x0400 | | 613 | #define AWIN_EHCI_SIZE 0x0400 |
| 533 | #define AWIN_OHCI_OFFSET 0x0400 | | 614 | #define AWIN_OHCI_OFFSET 0x0400 |
| 534 | #define AWIN_OHCI_SIZE 0x0400 | | 615 | #define AWIN_OHCI_SIZE 0x0400 |
| 535 | #define AWIN_USB_PMU_IRQ_REG 0x0800 | | 616 | #define AWIN_USB_PMU_IRQ_REG 0x0800 |
| 536 | | | 617 | |
| 537 | #define AWIN_USB0_PHY_CSR_ADDR __BITS(15,8) | | 618 | #define AWIN_USB0_PHY_CSR_ADDR __BITS(15,8) |
| 538 | #define AWIN_USB0_PHY_CSR_DAT __BIT(7) | | 619 | #define AWIN_USB0_PHY_CSR_DAT __BIT(7) |
| 539 | #define AWIN_USB0_PHY_CSR_CLK2 __BIT(2) | | 620 | #define AWIN_USB0_PHY_CSR_CLK2 __BIT(2) |
| 540 | #define AWIN_USB0_PHY_CSR_CLK1 __BIT(1) | | 621 | #define AWIN_USB0_PHY_CSR_CLK1 __BIT(1) |
| 541 | #define AWIN_USB0_PHY_CSR_CLK0 __BIT(0) | | 622 | #define AWIN_USB0_PHY_CSR_CLK0 __BIT(0) |
| 542 | | | 623 | |
| 543 | #define AWIN_USB_PMU_IRQ_AHB_INCR8 __BIT(10) | | 624 | #define AWIN_USB_PMU_IRQ_AHB_INCR8 __BIT(10) |
| 544 | #define AWIN_USB_PMU_IRQ_AHB_INCR4 __BIT(9) | | 625 | #define AWIN_USB_PMU_IRQ_AHB_INCR4 __BIT(9) |
| 545 | #define AWIN_USB_PMU_IRQ_AHB_INCRX __BIT(8) | | 626 | #define AWIN_USB_PMU_IRQ_AHB_INCRX __BIT(8) |
| 546 | #define AWIN_USB_PMU_IRQ_ULPI_BYPASS __BIT(0) | | 627 | #define AWIN_USB_PMU_IRQ_ULPI_BYPASS __BIT(0) |
| 547 | | | 628 | |
| 548 | /* PATA Definitions */ | | 629 | /* PATA Definitions */ |
| 549 | #define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */ | | 630 | #define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */ |
| 550 | | | 631 | |
| 551 | /* A10 Interrupt Register Definitions */ | | 632 | /* A10 Interrupt Register Definitions */ |
| 552 | #define AWIN_INTC_VECTOR_REG 0x0000 | | 633 | #define AWIN_INTC_VECTOR_REG 0x0000 |
| 553 | #define AWIN_INTC_BASE_ADDR_REG 0x0004 | | 634 | #define AWIN_INTC_BASE_ADDR_REG 0x0004 |
| 554 | #define AWIN_NMI_INT_CTRL_REG 0x000C | | 635 | #define AWIN_NMI_INT_CTRL_REG 0x000C |
| 555 | #define AWIN_INTC_IRQ_PEND0_REG 0x0010 | | 636 | #define AWIN_INTC_IRQ_PEND0_REG 0x0010 |
| 556 | #define AWIN_INTC_IRQ_PEND1_REG 0x0014 | | 637 | #define AWIN_INTC_IRQ_PEND1_REG 0x0014 |
| 557 | #define AWIN_INTC_IRQ_PEND2_REG 0x0018 | | 638 | #define AWIN_INTC_IRQ_PEND2_REG 0x0018 |
| 558 | #define AWIN_INTC_FIQ_PEND0_REG 0x0020 | | 639 | #define AWIN_INTC_FIQ_PEND0_REG 0x0020 |
| 559 | #define AWIN_INTC_FIQ_PEND1_REG 0x0024 | | 640 | #define AWIN_INTC_FIQ_PEND1_REG 0x0024 |