Sun Dec 1 01:05:17 2013 UTC ()
One const ought to be enough for every variable.


(joerg)
diff -r1.1.1.2 -r1.2 src/external/gpl3/gdb/dist/gdb/arm-tdep.c
cvs diff -r1.1.1.2 -r1.2 src/external/gpl3/gdb/dist/gdb/arm-tdep.c (expand / switch to unified diff)

--- src/external/gpl3/gdb/dist/gdb/arm-tdep.c 2013/10/03 15:49:39 1.1.1.2
+++ src/external/gpl3/gdb/dist/gdb/arm-tdep.c 2013/12/01 01:05:16 1.2
@@ -12433,40 +12433,40 @@ extract_arm_insn (insn_decode_record *in @@ -12433,40 +12433,40 @@ extract_arm_insn (insn_decode_record *in
12433} 12433}
12434 12434
12435typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); 12435typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
12436 12436
12437/* Decode arm/thumb insn depending on condition cods and opcodes; and 12437/* Decode arm/thumb insn depending on condition cods and opcodes; and
12438 dispatch it. */ 12438 dispatch it. */
12439 12439
12440static int 12440static int
12441decode_insn (insn_decode_record *arm_record, record_type_t record_type, 12441decode_insn (insn_decode_record *arm_record, record_type_t record_type,
12442 uint32_t insn_size) 12442 uint32_t insn_size)
12443{ 12443{
12444 12444
12445 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */ 12445 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12446 static const sti_arm_hdl_fp_t const arm_handle_insn[8] =  12446 static const sti_arm_hdl_fp_t arm_handle_insn[8] =
12447 { 12447 {
12448 arm_record_data_proc_misc_ld_str, /* 000. */ 12448 arm_record_data_proc_misc_ld_str, /* 000. */
12449 arm_record_data_proc_imm, /* 001. */ 12449 arm_record_data_proc_imm, /* 001. */
12450 arm_record_ld_st_imm_offset, /* 010. */ 12450 arm_record_ld_st_imm_offset, /* 010. */
12451 arm_record_ld_st_reg_offset, /* 011. */ 12451 arm_record_ld_st_reg_offset, /* 011. */
12452 arm_record_ld_st_multiple, /* 100. */ 12452 arm_record_ld_st_multiple, /* 100. */
12453 arm_record_b_bl, /* 101. */ 12453 arm_record_b_bl, /* 101. */
12454 arm_record_coproc, /* 110. */ 12454 arm_record_coproc, /* 110. */
12455 arm_record_coproc_data_proc /* 111. */ 12455 arm_record_coproc_data_proc /* 111. */
12456 }; 12456 };
12457 12457
12458 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */ 12458 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12459 static const sti_arm_hdl_fp_t const thumb_handle_insn[8] = 12459 static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
12460 { \ 12460 { \
12461 thumb_record_shift_add_sub, /* 000. */ 12461 thumb_record_shift_add_sub, /* 000. */
12462 thumb_record_add_sub_cmp_mov, /* 001. */ 12462 thumb_record_add_sub_cmp_mov, /* 001. */
12463 thumb_record_ld_st_reg_offset, /* 010. */ 12463 thumb_record_ld_st_reg_offset, /* 010. */
12464 thumb_record_ld_st_imm_offset, /* 011. */ 12464 thumb_record_ld_st_imm_offset, /* 011. */
12465 thumb_record_ld_st_stack, /* 100. */ 12465 thumb_record_ld_st_stack, /* 100. */
12466 thumb_record_misc, /* 101. */ 12466 thumb_record_misc, /* 101. */
12467 thumb_record_ldm_stm_swi, /* 110. */ 12467 thumb_record_ldm_stm_swi, /* 110. */
12468 thumb_record_branch /* 111. */ 12468 thumb_record_branch /* 111. */
12469 }; 12469 };
12470 12470
12471 uint32_t ret = 0; /* return value: negative:failure 0:success. */ 12471 uint32_t ret = 0; /* return value: negative:failure 0:success. */
12472 uint32_t insn_id = 0; 12472 uint32_t insn_id = 0;