 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wm.c,v 1.265 2013/12/29 21:28:41 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.266 2014/01/07 13:14:39 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -66,27 +66,27 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.265 2013/12/29 21:28:41 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.266 2014/01/07 13:14:39 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 @@ -4116,52 +4116,54 @@ wm_reset(struct wm_softc *sc)
+		}
+	}
 	/* Set the completion timeout for interface */
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		wm_set_pcie_completion_timeout(sc);
 	/* Clear interrupt */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
 	sc->sc_rctl &= ~RCTL_EN;
 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
 	CSR_WRITE_FLUSH(sc);
 	/* XXX set_tbi_sbp_82543() */
 	delay(10*1000);
 	/* Must acquire the MDIO ownership before MAC reset */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		wm_get_hw_semaphore_82573(sc);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * 82541 Errata 29? & 82547 Errata 28?
 	 * See also the description about PHY_RST bit in CTRL register
 	 * in 8254x_GBe_SDM.pdf.
 	 */
 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
 		CSR_WRITE(sc, WMREG_CTRL,
 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(5000);
+	}
 	switch (sc->sc_type) {
 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		/*
 		 * On some chipsets, a reset through a memory-mapped write
 		 * cycle can cause the chip to reset before completing the
 		 * write cycle.  This causes major headache that can be
 @@ -4202,26 +4204,27 @@ wm_reset(struct wm_softc *sc)
 			 * non-managed 82579
 			 */
 			if ((sc->sc_type == WM_T_PCH2)
 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
 				!= 0))
 				wm_gate_hw_phy_config_ich8lan(sc, 1);
 			reg |= CTRL_PHY_RESET;
 			phy_reset = 1;
+		}
 		wm_get_swfwhw_semaphore(sc);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		/* Don't insert a completion barrier when reset */
 		delay(20*1000);
 		wm_put_swfwhw_semaphore(sc);
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82546:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 @@ -4252,52 +4255,54 @@ wm_reset(struct wm_softc *sc)
 	if (phy_reset != 0)
 		wm_get_cfg_done(sc);
 	/* reload EEPROM */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		delay(10);
 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2000);
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		delay(5*1000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		delay(20000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
 			delay(10);
 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			CSR_WRITE_FLUSH(sc);
+		}
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		/*
 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
 		 * is set.
 		 */
 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
 		    || (sc->sc_type == WM_T_82583))
 			delay(25*1000);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 @@ -5199,54 +5204,59 @@ static void
 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
+{
 	uint32_t reg;
 	int x;
 	reg = CSR_READ(sc, WMREG_EECD);
 	for (x = nbits; x > 0; x--) {
 		if (bits & (1U << (x - 1)))
 			reg |= EECD_DI;
 		else
 			reg &= ~EECD_DI;
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
+	}
+}
 /*
  * wm_eeprom_recvbits:
+ *
  *	Receive a series of bits from the EEPROM.
  */
 static void
 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
+{
 	uint32_t reg, val;
 	int x;
 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
 	val = 0;
 	for (x = nbits; x > 0; x--) {
 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
 			val |= (1U << (x - 1));
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
+	}
 	*valp = val;
+}
 /*
  * wm_read_eeprom_uwire:
+ *
  *	Read a word from the EEPROM using the MicroWire protocol.
  */
 static int
 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 @@ -5260,48 +5270,51 @@ wm_read_eeprom_uwire(struct wm_softc *sc
 		/*
 		 * XXX: workaround for a bug in qemu-0.12.x and prior
 		 * and Xen.
+		 *
 		 * We use this workaround only for 82540 because qemu's
 		 * e1000 act as 82540.
 		 */
 		if (sc->sc_type == WM_T_82540) {
 			reg |= EECD_SK;
 			CSR_WRITE(sc, WMREG_EECD, reg);
 			reg &= ~EECD_SK;
 			CSR_WRITE(sc, WMREG_EECD, reg);
 			CSR_WRITE_FLUSH(sc);
 			delay(2);
+		}
 		/* XXX: end of workaround */
 		/* Set CHIP SELECT. */
 		reg |= EECD_CS;
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
 		/* Shift in the READ command. */
 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
 		/* Shift in address. */
 		wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
 		/* Shift out the data. */
 		wm_eeprom_recvbits(sc, &val, 16);
 		data[i] = val & 0xffff;
 		/* Clear CHIP SELECT. */
 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2);
+	}
 	return 0;
+}
 /*
  * wm_spi_eeprom_ready:
+ *
  *	Wait for a SPI EEPROM to be ready for commands.
  */
 static int
 wm_spi_eeprom_ready(struct wm_softc *sc)
 @@ -5327,52 +5340,56 @@ wm_spi_eeprom_ready(struct wm_softc *sc)
+ *
  *	Read a work from the EEPROM using the SPI protocol.
  */
 static int
 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 	uint32_t reg, val;
 	int i;
 	uint8_t opc;
 	/* Clear SK and CS. */
 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	if (wm_spi_eeprom_ready(sc))
 		return 1;
 	/* Toggle CS to flush commands. */
 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	opc = SPI_OPC_READ;
 	if (sc->sc_ee_addrbits == 8 && word >= 128)
 		opc |= SPI_OPC_A8;
 	wm_eeprom_sendbits(sc, opc, 8);
 	wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits);
 	for (i = 0; i < wordcnt; i++) {
 		wm_eeprom_recvbits(sc, &val, 16);
 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
+	}
 	/* Raise CS and clear SK. */
 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	return 0;
+}
 #define NVM_CHECKSUM			0xBABA
 #define EEPROM_SIZE			0x0040
 #define NVM_COMPAT			0x0003
 #define NVM_COMPAT_VALID_CHECKSUM	0x0001
 #define NVM_FUTURE_INIT_WORD1			0x0019
 #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM	0x0040
 /*
 @@ -5974,53 +5991,57 @@ wm_tbi_mediachange(struct ifnet *ifp)
 	    (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 		sc->sc_txcw |= TXCW_ANE;
 	} else {
 		/*
 		 * If autonegotiation is turned off, force link up and turn on
 		 * full duplex
 		 */
 		sc->sc_txcw &= ~TXCW_ANE;
 		sc->sc_ctrl |= CTRL_SLU | CTRL_FD;
 		sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(1000);
+	}
 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
 		    device_xname(sc->sc_dev),sc->sc_txcw));
 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
 	CSR_WRITE_FLUSH(sc);
 	delay(10000);
 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
 	/*
 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
 	 * optics detect a signal, 0 if they don't.
 	 */
 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
 		/* Have signal; wait for the link to come up. */
 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/*
 			 * Reset the link, and let autonegotiation do its thing
 			 */
 			sc->sc_ctrl |= CTRL_LRST;
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 			CSR_WRITE_FLUSH(sc);
 			delay(1000);
 			sc->sc_ctrl &= ~CTRL_LRST;
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 			CSR_WRITE_FLUSH(sc);
 			delay(1000);
+		}
 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
 			delay(10000);
 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
 				break;
+		}
 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
 			    device_xname(sc->sc_dev),i));
 		status = CSR_READ(sc, WMREG_STATUS);
 @@ -6134,29 +6155,31 @@ wm_tbi_check_link(struct wm_softc *sc)
 			wm_init(ifp);
 			ifp->if_start(ifp);
 		} else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/* If the timer expired, retry autonegotiation */
 			if (++sc->sc_tbi_ticks >= sc->sc_tbi_anegticks) {
 				DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
 				sc->sc_tbi_ticks = 0;
 				/*
 				 * Reset the link, and let autonegotiation do
 				 * its thing
 				 */
 				sc->sc_ctrl |= CTRL_LRST;
 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 				CSR_WRITE_FLUSH(sc);
 				delay(1000);
 				sc->sc_ctrl &= ~CTRL_LRST;
 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 				CSR_WRITE_FLUSH(sc);
 				delay(1000);
 				CSR_WRITE(sc, WMREG_TXCW,
 				    sc->sc_txcw & ~TXCW_ANE);
 				CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
+			}
+		}
+	}
 	wm_tbi_set_linkled(sc);
+}
 /*
  * wm_gmii_reset:
 @@ -6221,29 +6244,31 @@ wm_gmii_reset(struct wm_softc *sc)
 		 * In addition, we need to perform a hardware reset on the PHY
 		 * to take it out of reset.
 		 */
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		/* The PHY reset pin is active-low. */
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
 		    CTRL_EXT_SWDPIN(4));
 		reg |= CTRL_EXT_SWDPIO(4);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(10*1000);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 #if 0
 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
 #endif
 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
 		break;
 	case WM_T_82544:	/* reset 10000us */
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 @@ -6256,48 +6281,52 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_82583:
 	case WM_T_80003:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		if ((sc->sc_type == WM_T_82541)
 		    || (sc->sc_type == WM_T_82541_2)
 		    || (sc->sc_type == WM_T_82547)
 		    || (sc->sc_type == WM_T_82547_2)) {
 			/* workaround for igp are done in igp_reset() */
 			/* XXX add code to set LED after phy reset */
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(100);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	/* release PHY semaphore */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 @@ -6734,63 +6763,73 @@ i82543_mii_sendbits(struct wm_softc *sc,
+{
 	uint32_t i, v;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= MDI_DIR | CTRL_SWDPIO(3);
 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
 		if (data & i)
 			v |= MDI_IO;
 		else
 			v &= ~MDI_IO;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
+}
 static uint32_t
 i82543_mii_recvbits(struct wm_softc *sc)
+{
 	uint32_t v, i, data = 0;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= CTRL_SWDPIO(3);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	for (i = 0; i < 16; i++) {
 		data <<= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
 			data |= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	return data;
+}
 #undef MDI_IO
 #undef MDI_DIR
 #undef MDI_CLK
 /*
  * wm_gmii_i82543_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII (i82543 version).
 @@ -7445,26 +7484,27 @@ wm_kmrn_readreg(struct wm_softc *sc, int
 			return 0;
+		}
 	} else if (sc->sc_flags == WM_F_SWFWHW_SYNC) {
 		if (wm_get_swfwhw_semaphore(sc)) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to get semaphore\n", __func__);
 			return 0;
+		}
+	}
 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
 	    KUMCTRLSTA_REN);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
 	if (sc->sc_flags == WM_F_SWFW_SYNC)
 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
 	else if (sc->sc_flags == WM_F_SWFWHW_SYNC)
 		wm_put_swfwhw_semaphore(sc);
 	return rv;
+}
 /*
 @@ -8466,47 +8506,51 @@ wm_configure_k1_ich8lan(struct wm_softc
 	wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmrn_reg);
 	delay(20);
 	ctrl = CSR_READ(sc, WMREG_CTRL);
 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
 	tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
 	tmp |= CTRL_FRCSPD;
 	CSR_WRITE(sc, WMREG_CTRL, tmp);
 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS);
 	CSR_WRITE_FLUSH(sc);
 	delay(20);
 	CSR_WRITE(sc, WMREG_CTRL, ctrl);
 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
 	CSR_WRITE_FLUSH(sc);
 	delay(20);
+}
 static void
 wm_smbustopci(struct wm_softc *sc)
+{
 	uint32_t fwsm;
 	fwsm = CSR_READ(sc, WMREG_FWSM);
 	if (((fwsm & FWSM_FW_VALID) == 0)
 	    && ((wm_check_reset_block(sc) == 0))) {
 		sc->sc_ctrl |= CTRL_LANPHYPC_OVERRIDE;
 		sc->sc_ctrl &= ~CTRL_LANPHYPC_VALUE;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		sc->sc_ctrl &= ~CTRL_LANPHYPC_OVERRIDE;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(50*1000);
 		/*
 		 * Gate automatic PHY configuration by hardware on non-managed
 		 * 82579
 		 */
 		if (sc->sc_type == WM_T_PCH2)
 			wm_gate_hw_phy_config_ich8lan(sc, 1);
+	}
+}
 static void
 wm_set_pcie_completion_timeout(struct wm_softc *sc)