 @@ -1,540 +1,540 @@
-/*	$NetBSD: cpu.c,v 1.107 2014/01/07 20:11:35 palle Exp $ */
+/*	$NetBSD: cpu.c,v 1.108 2014/01/09 20:13:54 palle Exp $ */
 /*
  * Copyright (c) 1996
  *	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Aaron Brown and
  *	Harvard University.
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)cpu.c	8.5 (Berkeley) 11/23/93
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.107 2014/01/07 20:11:35 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.108 2014/01/09 20:13:54 palle Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/reboot.h>
 #include <uvm/uvm.h>
 #include <machine/autoconf.h>
 #include <machine/cpu.h>
 #include <machine/reg.h>
 #include <machine/trap.h>
 #include <machine/pmap.h>
 #include <machine/sparc64.h>
 #include <machine/openfirm.h>
 #include <sparc64/sparc64/cache.h>
 #ifdef SUN4V
 #include <sparc64/hypervisor.h>
 #endif
 int ecache_min_line_size;
 /* Linked list of all CPUs in system. */
 #if defined(MULTIPROCESSOR)
 int sparc_ncpus = 0;
 #endif
 struct cpu_info *cpus = NULL;
 volatile sparc64_cpuset_t cpus_active;/* set of active cpus */
 struct cpu_bootargs *cpu_args;	/* allocated very early in pmap_bootstrap. */
 struct pool_cache *fpstate_cache;
 static struct cpu_info *alloc_cpuinfo(u_int);
 /* The following are used externally (sysctl_hw). */
 char	machine[] = MACHINE;		/* from <machine/param.h> */
 char	machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
 char	cpu_model[100];			/* machine model (primary CPU) */
 /* These are used in locore.s, and are maximums */
 int	dcache_line_size;
 int	dcache_size;
 int	icache_line_size;
 int	icache_size;
 #ifdef MULTIPROCESSOR
 static const char *ipi_evcnt_names[IPI_EVCNT_NUM] = IPI_EVCNT_NAMES;
 #endif
 static void cpu_reset_fpustate(void);
 volatile int sync_tick = 0;
 /* The CPU configuration driver. */
 void cpu_attach(device_t, device_t, void *);
 int cpu_match(device_t, cfdata_t, void *);
 CFATTACH_DECL_NEW(cpu, 0, cpu_match, cpu_attach, NULL, NULL);
 static int
 upaid_from_node(u_int cpu_node)
+{
 	int portid;
 	if (OF_getprop(cpu_node, "upa-portid", &portid, sizeof(portid)) <= 0 &&
 	    OF_getprop(cpu_node, "portid", &portid, sizeof(portid)) <= 0)
 		panic("cpu node w/o upa-portid");
 	return portid;
+}
 struct cpu_info *
 alloc_cpuinfo(u_int cpu_node)
+{
 	paddr_t pa0, pa;
 	vaddr_t va, va0;
 	vsize_t sz = 8 * PAGE_SIZE;
 	int portid;
 	struct cpu_info *cpi, *ci;
 	extern paddr_t cpu0paddr;
 	/*
 	 * Check for UPAID in the cpus list.
 	 */
 	portid = upaid_from_node(cpu_node);
 	for (cpi = cpus; cpi != NULL; cpi = cpi->ci_next)
 		if (cpi->ci_cpuid == portid)
 			return cpi;
 	/* Allocate the aligned VA and determine the size. */
 	va = uvm_km_alloc(kernel_map, sz, 8 * PAGE_SIZE, UVM_KMF_VAONLY);
 	if (!va)
 		panic("alloc_cpuinfo: no virtual space");
 	va0 = va;
 	pa0 = cpu0paddr;
 	cpu0paddr += sz;
 	for (pa = pa0; pa < cpu0paddr; pa += PAGE_SIZE, va += PAGE_SIZE)
 		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0);
 	pmap_update(pmap_kernel());
 	cpi = (struct cpu_info *)(va0 + CPUINFO_VA - INTSTACK);
 	memset((void *)va0, 0, sz);
 	/*
 	 * Initialize cpuinfo structure.
+	 *
 	 * Arrange pcb, idle stack and interrupt stack in the same
 	 * way as is done for the boot CPU in pmap.c.
 	 */
 	cpi->ci_next = NULL;
 	cpi->ci_curlwp = NULL;
 	cpi->ci_cpuid = portid;
 	cpi->ci_fplwp = NULL;
 	cpi->ci_eintstack = NULL;
 	cpi->ci_spinup = NULL;
 	cpi->ci_paddr = pa0;
 	cpi->ci_self = cpi;
 #ifdef SUN4V
-	if ( CPU_ISSUN4V )
+	if (CPU_ISSUN4V)
 		cpi->ci_mmfsa = pa0;
 #endif
 	cpi->ci_node = cpu_node;
 	cpi->ci_idepth = -1;
 	memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending));
 	/*
 	 * Finally, add itself to the list of active cpus.
 	 */
 	for (ci = cpus; ci->ci_next != NULL; ci = ci->ci_next)
+		;
 #ifdef MULTIPROCESSOR
 	ci->ci_next = cpi;
 #endif
 	return (cpi);
+}
 int
 cpu_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct mainbus_attach_args *ma = aux;
 	if (strcmp(cf->cf_name, ma->ma_name) != 0)
 		return 0;
 	/*
 	 * If we are going to only attach a single cpu, make sure
 	 * to pick the one we are running on right now.
 	 */
 	if (upaid_from_node(ma->ma_node) != CPU_UPAID) {
 #ifdef MULTIPROCESSOR
 		if (boothowto & RB_MD1)
 #endif
 			return 0;
+	}
 	return 1;
+}
 static void
 cpu_reset_fpustate(void)
+{
 	struct fpstate64 *fpstate;
 	struct fpstate64 fps[2];
 	/* This needs to be 64-byte aligned */
 	fpstate = ALIGNFPSTATE(&fps[1]);
 	/*
 	 * Get the FSR and clear any exceptions.  If we do not unload
 	 * the queue here and it is left over from a previous crash, we
 	 * will panic in the first loadfpstate(), due to a sequence error,
 	 * so we need to dump the whole state anyway.
 	 */
 	fpstate->fs_fsr = 7 << FSR_VER_SHIFT;	/* 7 is reserved for "none" */
 	savefpstate(fpstate);
+}
 /*
  * Attach the CPU.
  * Discover interesting goop about the virtual address cache
  * (slightly funny place to do it, but this is where it is to be found).
  */
 void
 cpu_attach(device_t parent, device_t dev, void *aux)
+{
 	int node;
 	long clk, sclk = 0;
 	struct mainbus_attach_args *ma = aux;
 	struct cpu_info *ci;
 	const char *sep;
 	register int i, l;
 	int bigcache, cachesize;
 	char buf[100];
 	int 	totalsize = 0;
 	int 	linesize, dcachesize, icachesize;
 	/* tell them what we have */
 	node = ma->ma_node;
 	/*
 	 * Allocate cpu_info structure if needed.
 	 */
 	ci = alloc_cpuinfo((u_int)node);
 	/*
 	 * Only do this on the boot cpu.  Other cpu's call
 	 * cpu_reset_fpustate() from cpu_hatch() before they
 	 * call into the idle loop.
 	 * For other cpus, we need to call mi_cpu_attach()
 	 * and complete setting up cpcb.
 	 */
 	if (ci->ci_flags & CPUF_PRIMARY) {
 		fpstate_cache = pool_cache_init(sizeof(struct fpstate64),
 					SPARC64_BLOCK_SIZE, 0, 0, "fpstate",
 					NULL, IPL_NONE, NULL, NULL, NULL);
 		cpu_reset_fpustate();
+	}
 #ifdef MULTIPROCESSOR
 	else {
 		mi_cpu_attach(ci);
 		ci->ci_cpcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
+	}
 	for (i = 0; i < IPI_EVCNT_NUM; ++i)
 		evcnt_attach_dynamic(&ci->ci_ipi_evcnt[i], EVCNT_TYPE_INTR,
 				     NULL, device_xname(dev), ipi_evcnt_names[i]);
 #endif
 	evcnt_attach_dynamic(&ci->ci_tick_evcnt, EVCNT_TYPE_INTR, NULL,
 			     device_xname(dev), "timer");
 	mutex_init(&ci->ci_ctx_lock, MUTEX_SPIN, IPL_VM);
 	clk = prom_getpropint(node, "clock-frequency", 0);
 	if (clk == 0) {
 		/*
 		 * Try to find it in the OpenPROM root...
 		 */
 		clk = prom_getpropint(findroot(), "clock-frequency", 0);
+	}
 	if (clk) {
 		/* Tell OS what frequency we run on */
 		ci->ci_cpu_clockrate[0] = clk;
 		ci->ci_cpu_clockrate[1] = clk / 1000000;
+	}
 	sclk = prom_getpropint(findroot(), "stick-frequency", 0);
 	ci->ci_system_clockrate[0] = sclk;
 	ci->ci_system_clockrate[1] = sclk / 1000000;
 	snprintf(buf, sizeof buf, "%s @ %s MHz",
 		prom_getpropstring(node, "name"), clockfreq(clk));
 	snprintf(cpu_model, sizeof cpu_model, "%s (%s)", machine_model, buf);
 	aprint_normal(": %s, UPA id %d\n", buf, ci->ci_cpuid);
 	aprint_naive("\n");
 	if (ci->ci_system_clockrate[0] != 0) {
 		aprint_normal_dev(dev, "system tick frequency %d MHz\n",
 		    (int)ci->ci_system_clockrate[1]);
+	}
 	aprint_normal_dev(dev, "");
 	bigcache = 0;
 	icachesize = prom_getpropint(node, "icache-size", 0);
 	if (icachesize > icache_size)
 		icache_size = icachesize;
 	linesize = l = prom_getpropint(node, "icache-line-size", 0);
 	if (linesize > icache_line_size)
 		icache_line_size = linesize;
 	for (i = 0; (1 << i) < l && l; i++)
 		/* void */;
 	if ((1 << i) != l && l)
 		panic("bad icache line size %d", l);
 	totalsize = icachesize;
 	if (totalsize == 0)
 		totalsize = l *
 			prom_getpropint(node, "icache-nlines", 64) *
 			prom_getpropint(node, "icache-associativity", 1);
 	cachesize = totalsize /
 	    prom_getpropint(node, "icache-associativity", 1);
 	bigcache = cachesize;
 	sep = "";
 	if (totalsize > 0) {
 		aprint_normal("%s%ldK instruction (%ld b/l)", sep,
 		       (long)totalsize/1024,
 		       (long)linesize);
 		sep = ", ";
+	}
 	dcachesize = prom_getpropint(node, "dcache-size", 0);
 	if (dcachesize > dcache_size)
 		dcache_size = dcachesize;
 	linesize = l = prom_getpropint(node, "dcache-line-size", 0);
 	if (linesize > dcache_line_size)
 		dcache_line_size = linesize;
 	for (i = 0; (1 << i) < l && l; i++)
 		/* void */;
 	if ((1 << i) != l && l)
 		panic("bad dcache line size %d", l);
 	totalsize = dcachesize;
 	if (totalsize == 0)
 		totalsize = l *
 			prom_getpropint(node, "dcache-nlines", 128) *
 			prom_getpropint(node, "dcache-associativity", 1);
 	cachesize = totalsize /
 	    prom_getpropint(node, "dcache-associativity", 1);
 	if (cachesize > bigcache)
 		bigcache = cachesize;
 	if (totalsize > 0) {
 		aprint_normal("%s%ldK data (%ld b/l)", sep,
 		       (long)totalsize/1024,
 		       (long)linesize);
 		sep = ", ";
+	}
 	linesize = l =
 		prom_getpropint(node, "ecache-line-size", 0);
 	for (i = 0; (1 << i) < l && l; i++)
 		/* void */;
 	if ((1 << i) != l && l)
 		panic("bad ecache line size %d", l);
 	totalsize = prom_getpropint(node, "ecache-size", 0);
 	if (totalsize == 0)
 		totalsize = l *
 			prom_getpropint(node, "ecache-nlines", 32768) *
 			prom_getpropint(node, "ecache-associativity", 1);
 	cachesize = totalsize /
 	     prom_getpropint(node, "ecache-associativity", 1);
 	if (cachesize > bigcache)
 		bigcache = cachesize;
 	if (totalsize > 0) {
 		aprint_normal("%s%ldK external (%ld b/l)", sep,
 		       (long)totalsize/1024,
 		       (long)linesize);
+	}
 	aprint_normal("\n");
 	if (ecache_min_line_size == 0 ||
 	    linesize < ecache_min_line_size)
 		ecache_min_line_size = linesize;
 	/*
 	 * Now that we know the size of the largest cache on this CPU,
 	 * re-color our pages.
 	 */
 	uvm_page_recolor(atop(bigcache)); /* XXX */
+}
 int
 cpu_myid(void)
+{
 	char buf[32];
 	int impl;
 #ifdef SUN4V
 	if (CPU_ISSUN4V) {
 		uint64_t myid;
 		hv_cpu_myid(&myid);
 		return myid;
+	}
 #endif
 	if (OF_getprop(findroot(), "name", buf, sizeof(buf)) > 0 &&
 	    strcmp(buf, "SUNW,Ultra-Enterprise-10000") == 0)
 		return lduwa(0x1fff40000d0UL, ASI_PHYS_NON_CACHED);
 	impl = (getver() & VER_IMPL) >> VER_IMPL_SHIFT;
 	switch (impl) {
 		case IMPL_OLYMPUS_C:
 		case IMPL_JUPITER:
 			return CPU_JUPITERID;
 		case IMPL_CHEETAH:
 		case IMPL_CHEETAH_PLUS:
 		case IMPL_JAGUAR:
 		case IMPL_PANTHER:
 			return CPU_FIREPLANEID;
 		default:
 			return CPU_UPAID;
+	}
+}
 #if defined(MULTIPROCESSOR)
 vaddr_t cpu_spinup_trampoline;
 /*
  * Start secondary processors in motion.
  */
 void
 cpu_boot_secondary_processors(void)
+{
 	int i, pstate;
 	struct cpu_info *ci;
 	sync_tick = 0;
 	sparc64_ipi_init();
 	if (boothowto & RB_MD1) {
 		cpus[0].ci_next = NULL;
 		sparc_ncpus = ncpu = ncpuonline = 1;
 		return;
+	}
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		if (ci->ci_cpuid == CPU_UPAID)
 			continue;
 		cpu_pmap_prepare(ci, false);
 		cpu_args->cb_node = ci->ci_node;
 		cpu_args->cb_cpuinfo = ci->ci_paddr;
 		membar_Sync();
 		/* Disable interrupts and start another CPU. */
 		pstate = getpstate();
 		setpstate(PSTATE_KERN);
 		prom_startcpu(ci->ci_node, (void *)cpu_spinup_trampoline, 0);
 		for (i = 0; i < 2000; i++) {
 			membar_Sync();
 			if (CPUSET_HAS(cpus_active, ci->ci_index))
 				break;
 			delay(10000);
+		}
 		/* synchronize %tick ( to some degree at least ) */
 		delay(1000);
 		sync_tick = 1;
 		membar_Sync();
 		settick(0);
 		if (ci->ci_system_clockrate[0] != 0)
 			setstick(0);
 		setpstate(pstate);
 		if (!CPUSET_HAS(cpus_active, ci->ci_index))
 			printf("cpu%d: startup failed\n", ci->ci_cpuid);
+	}
+}
 void
 cpu_hatch(void)
+{
 	char *v = (char*)CPUINFO_VA;
 	int i;
 	for (i = 0; i < 4*PAGE_SIZE; i += sizeof(long))
 		flush(v + i);
 	cpu_pmap_init(curcpu());
 	CPUSET_ADD(cpus_active, cpu_number());
 	cpu_reset_fpustate();
 	curlwp = curcpu()->ci_data.cpu_idlelwp;
 	membar_Sync();
 	/* wait for the boot CPU to flip the switch */
 	while (sync_tick == 0) {
 		/* we do nothing here */
+	}
 	settick(0);
 	if (curcpu()->ci_system_clockrate[0] != 0) {
 		setstick(0);
 		stickintr_establish(PIL_CLOCK, stickintr);
 	} else {
 		tickintr_establish(PIL_CLOCK, tickintr);
+	}
 	spl0();
+}
 #endif /* MULTIPROCESSOR */

 @@ -1,2160 +1,2160 @@
-/*	$NetBSD: pmap.c,v 1.285 2014/01/07 20:11:35 palle Exp $	*/
+/*	$NetBSD: pmap.c,v 1.286 2014/01/09 20:13:54 palle Exp $	*/
 /*
+ *
  * Copyright (C) 1996-1999 Eduardo Horvath.
  * All rights reserved.
+ *
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.285 2014/01/07 20:11:35 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.286 2014/01/09 20:13:54 palle Exp $");
 #undef	NO_VCACHE /* Don't forget the locked TLB in dostart */
 #define	HWREF
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_modular.h"
 #include <sys/param.h>
 #include <sys/malloc.h>
 #include <sys/queue.h>
 #include <sys/systm.h>
 #include <sys/msgbuf.h>
 #include <sys/pool.h>
 #include <sys/exec.h>
 #include <sys/core.h>
 #include <sys/kcore.h>
 #include <sys/proc.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <sys/exec_aout.h>	/* for MID_* */
 #include <uvm/uvm.h>
 #include <machine/pcb.h>
 #include <machine/sparc64.h>
 #include <machine/ctlreg.h>
 #include <machine/promlib.h>
 #include <machine/kcore.h>
 #include <machine/bootinfo.h>
 #include <sparc64/sparc64/cache.h>
 #ifdef SUN4V
 #include <sparc64/hypervisor.h>
 #endif
 #ifdef DDB
 #include <machine/db_machdep.h>
 #include <ddb/db_command.h>
 #include <ddb/db_sym.h>
 #include <ddb/db_variables.h>
 #include <ddb/db_extern.h>
 #include <ddb/db_access.h>
 #include <ddb/db_output.h>
 #else
 #define Debugger()
 #define db_printf	printf
 #endif
 #define	MEG		(1<<20) /* 1MB */
 #define	KB		(1<<10)	/* 1KB */
 paddr_t cpu0paddr;		/* contigious phys memory preallocated for cpus */
 /* These routines are in assembly to allow access thru physical mappings */
 extern int64_t pseg_get_real(struct pmap *, vaddr_t);
 extern int pseg_set_real(struct pmap *, vaddr_t, int64_t, paddr_t);
 /*
  * Diatribe on ref/mod counting:
+ *
  * First of all, ref/mod info must be non-volatile.  Hence we need to keep it
  * in the pv_entry structure for each page.  (We could bypass this for the
  * vm_page, but that's a long story....)
+ *
  * This architecture has nice, fast traps with lots of space for software bits
  * in the TTE.  To accelerate ref/mod counts we make use of these features.
+ *
  * When we map a page initially, we place a TTE in the page table.  It's
  * inserted with the TLB_W and TLB_ACCESS bits cleared.  If a page is really
  * writable we set the TLB_REAL_W bit for the trap handler.
+ *
  * Whenever we take a TLB miss trap, the trap handler will set the TLB_ACCESS
  * bit in the approprate TTE in the page table.  Whenever we take a protection
  * fault, if the TLB_REAL_W bit is set then we flip both the TLB_W and TLB_MOD
  * bits to enable writing and mark the page as modified.
+ *
  * This means that we may have ref/mod information all over the place.  The
  * pmap routines must traverse the page tables of all pmaps with a given page
  * and collect/clear all the ref/mod information and copy it into the pv_entry.
  */
 #ifdef	NO_VCACHE
 #define	FORCE_ALIAS	1
 #else
 #define FORCE_ALIAS	0
 #endif
 #define	PV_ALIAS	0x1LL
 #define PV_REF		0x2LL
 #define PV_MOD		0x4LL
 #define PV_NVC		0x8LL
 #define PV_NC		0x10LL
 #define PV_WE		0x20LL	/* Debug -- this page was writable somtime */
 #define PV_MASK		(0x03fLL)
 #define PV_VAMASK	(~(PAGE_SIZE - 1))
 #define PV_MATCH(pv,va)	(!(((pv)->pv_va ^ (va)) & PV_VAMASK))
 #define PV_SETVA(pv,va) ((pv)->pv_va = (((va) & PV_VAMASK) | \
 					(((pv)->pv_va) & PV_MASK)))
 struct pool_cache pmap_cache;
 struct pool_cache pmap_pv_cache;
 pv_entry_t	pmap_remove_pv(struct pmap *, vaddr_t, struct vm_page *);
 void	pmap_enter_pv(struct pmap *, vaddr_t, paddr_t, struct vm_page *,
 			   pv_entry_t);
 void	pmap_page_cache(struct pmap *, paddr_t, int);
 /*
  * First and last managed physical addresses.
  * XXX only used for dumping the system.
  */
 paddr_t	vm_first_phys, vm_num_phys;
 /*
  * Here's the CPU TSB stuff.  It's allocated in pmap_bootstrap.
  */
 int tsbsize;		/* tsbents = 512 * 2^^tsbsize */
 #define TSBENTS (512<<tsbsize)
 #define	TSBSIZE	(TSBENTS * 16)
 #ifdef SUN4V
 struct tsb_desc *tsb_desc;
 #endif
 static struct pmap kernel_pmap_;
 struct pmap *const kernel_pmap_ptr = &kernel_pmap_;
 static int ctx_alloc(struct pmap *);
 static bool pmap_is_referenced_locked(struct vm_page *);
 static void ctx_free(struct pmap *, struct cpu_info *);
 /*
  * Check if any MMU has a non-zero context
  */
 static inline bool
 pmap_has_ctx(struct pmap *p)
+{
 	int i;
 	/* any context on any cpu? */
 	for (i = 0; i < sparc_ncpus; i++)
 		if (p->pm_ctx[i] > 0)
 			return true;
 	return false;
+}
 #ifdef MULTIPROCESSOR
 #define pmap_ctx(PM)	((PM)->pm_ctx[cpu_number()])
 #else
 #define pmap_ctx(PM)	((PM)->pm_ctx[0])
 #endif
 /*
  * Check if this pmap has a live mapping on some MMU.
  */
 static inline bool
 pmap_is_on_mmu(struct pmap *p)
+{
 	/* The kernel pmap is always on all MMUs */
 	if (p == pmap_kernel())
 		return true;
 	return pmap_has_ctx(p);
+}
 /*
  * Virtual and physical addresses of the start and end of kernel text
  * and data segments.
  */
 vaddr_t ktext;
 paddr_t ktextp;
 vaddr_t ektext;
 paddr_t ektextp;
 vaddr_t kdata;
 paddr_t kdatap;
 vaddr_t ekdata;
 paddr_t ekdatap;
 /*
  * Kernel 4MB pages.
  */
 extern struct tlb_entry *kernel_tlbs;
 extern int kernel_tlb_slots;
 static int npgs;
 vaddr_t	vmmap;			/* one reserved MI vpage for /dev/mem */
 int phys_installed_size;		/* Installed physical memory */
 struct mem_region *phys_installed;
 paddr_t avail_start, avail_end;	/* These are used by ps & family */
 static int ptelookup_va(vaddr_t va);
 static inline void
 clrx(void *addr)
+{
 	__asm volatile("clrx [%0]" : : "r" (addr) : "memory");
+}
 static void
 tsb_invalidate(vaddr_t va, pmap_t pm)
+{
 	struct cpu_info *ci;
 	int ctx;
 	bool kpm = (pm == pmap_kernel());
 	int i;
 	int64_t tag;
 	i = ptelookup_va(va);
 #ifdef MULTIPROCESSOR
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		if (!CPUSET_HAS(cpus_active, ci->ci_index))
 			continue;
 #else
 		ci = curcpu();
 #endif
 		ctx = pm->pm_ctx[ci->ci_index];
 		if (kpm || ctx > 0) {
 			tag = TSB_TAG(0, ctx, va);
 			if (ci->ci_tsb_dmmu[i].tag == tag) {
 				clrx(&ci->ci_tsb_dmmu[i].data);
+			}
 			if (ci->ci_tsb_immu[i].tag == tag) {
 				clrx(&ci->ci_tsb_immu[i].data);
+			}
+		}
 #ifdef MULTIPROCESSOR
+	}
 #endif
+}
 struct prom_map *prom_map;
 int prom_map_size;
 #define	PDB_CREATE		0x000001
 #define	PDB_DESTROY		0x000002
 #define	PDB_REMOVE		0x000004
 #define	PDB_CHANGEPROT		0x000008
 #define	PDB_ENTER		0x000010
 #define	PDB_DEMAP		0x000020	/* used in locore */
 #define	PDB_REF			0x000040
 #define	PDB_COPY		0x000080
 #define	PDB_MMU_ALLOC		0x000100
 #define	PDB_MMU_STEAL		0x000200
 #define	PDB_CTX_ALLOC		0x000400
 #define	PDB_CTX_STEAL		0x000800
 #define	PDB_MMUREG_ALLOC	0x001000
 #define	PDB_MMUREG_STEAL	0x002000
 #define	PDB_CACHESTUFF		0x004000
 #define	PDB_ALIAS		0x008000
 #define PDB_EXTRACT		0x010000
 #define	PDB_BOOT		0x020000
 #define	PDB_BOOT1		0x040000
 #define	PDB_GROW		0x080000
 #define	PDB_CTX_FLUSHALL	0x100000
 #define	PDB_ACTIVATE		0x200000
 #if defined(DEBUG) && !defined(PMAP_DEBUG)
 #define PMAP_DEBUG
 #endif
 #ifdef PMAP_DEBUG
 struct {
 	int kernel;	/* entering kernel mapping */
 	int user;	/* entering user mapping */
 	int ptpneeded;	/* needed to allocate a PT page */
 	int pwchange;	/* no mapping change, just wiring or protection */
 	int wchange;	/* no mapping change, just wiring */
 	int mchange;	/* was mapped but mapping to different page */
 	int managed;	/* a managed page */
 	int firstpv;	/* first mapping for this PA */
 	int secondpv;	/* second mapping for this PA */
 	int ci;		/* cache inhibited */
 	int unmanaged;	/* not a managed page */
 	int flushes;	/* cache flushes */
 	int cachehit;	/* new entry forced valid entry out */
 } enter_stats;
 struct {
 	int calls;
 	int removes;
 	int flushes;
 	int tflushes;	/* TLB flushes */
 	int pidflushes;	/* HW pid stolen */
 	int pvfirst;
 	int pvsearch;
 } remove_stats;
 #define	ENTER_STAT(x)	do { enter_stats.x ++; } while (0)
 #define	REMOVE_STAT(x)	do { remove_stats.x ++; } while (0)
 int	pmapdebug = 0;
 //int	pmapdebug = 0 | PDB_CTX_ALLOC | PDB_ACTIVATE;
 /* Number of H/W pages stolen for page tables */
 int	pmap_pages_stolen = 0;
 #define	BDPRINTF(n, f)	if (pmapdebug & (n)) prom_printf f
 #define	DPRINTF(n, f)	if (pmapdebug & (n)) printf f
 #else
 #define	ENTER_STAT(x)	do { /* nothing */ } while (0)
 #define	REMOVE_STAT(x)	do { /* nothing */ } while (0)
 #define	BDPRINTF(n, f)
 #define	DPRINTF(n, f)
 #define pmapdebug 0
 #endif
 #define pv_check()
 static int pmap_get_page(paddr_t *);
 static void pmap_free_page(paddr_t, sparc64_cpuset_t);
 static void pmap_free_page_noflush(paddr_t);
 /*
  * Global pmap locks.
  */
 static kmutex_t pmap_lock;
 static bool lock_available = false;
 /*
  * Support for big page sizes.  This maps the page size to the
  * page bits.  That is: these are the bits between 8K pages and
  * larger page sizes that cause aliasing.
  */
 #define PSMAP_ENTRY(MASK, CODE)	{ .mask = MASK, .code = CODE }
 struct page_size_map page_size_map[] = {
 #ifdef DEBUG
 	PSMAP_ENTRY(0, PGSZ_8K & 0),	/* Disable large pages */
 #endif
 	PSMAP_ENTRY((4 * 1024 * 1024 - 1) & ~(8 * 1024 - 1), PGSZ_4M),
 	PSMAP_ENTRY((512 * 1024 - 1) & ~(8 * 1024 - 1), PGSZ_512K),
 	PSMAP_ENTRY((64 * 1024 - 1) & ~(8 * 1024 - 1), PGSZ_64K),
 	PSMAP_ENTRY((8 * 1024 - 1) & ~(8 * 1024 - 1), PGSZ_8K),
 	PSMAP_ENTRY(0, 0),
 };
 /*
  * This probably shouldn't be necessary, but it stops USIII machines from
  * breaking in general, and not just for MULTIPROCESSOR.
  */
 #define USE_LOCKSAFE_PSEG_GETSET
 #if defined(USE_LOCKSAFE_PSEG_GETSET)
 static kmutex_t pseg_lock;
 static __inline__ int64_t
 pseg_get_locksafe(struct pmap *pm, vaddr_t va)
+{
 	int64_t rv;
 	bool took_lock = lock_available /*&& pm == pmap_kernel()*/;
 	if (__predict_true(took_lock))
 		mutex_enter(&pseg_lock);
 	rv = pseg_get_real(pm, va);
 	if (__predict_true(took_lock))
 		mutex_exit(&pseg_lock);
 	return rv;
+}
 static __inline__ int
 pseg_set_locksafe(struct pmap *pm, vaddr_t va, int64_t data, paddr_t ptp)
+{
 	int rv;
 	bool took_lock = lock_available /*&& pm == pmap_kernel()*/;
 	if (__predict_true(took_lock))
 		mutex_enter(&pseg_lock);
 	rv = pseg_set_real(pm, va, data, ptp);
 	if (__predict_true(took_lock))
 		mutex_exit(&pseg_lock);
 	return rv;
+}
 #define pseg_get(pm, va)		pseg_get_locksafe(pm, va)
 #define pseg_set(pm, va, data, ptp)	pseg_set_locksafe(pm, va, data, ptp)
 #else /* USE_LOCKSAFE_PSEG_GETSET */
 #define pseg_get(pm, va)		pseg_get_real(pm, va)
 #define pseg_set(pm, va, data, ptp)	pseg_set_real(pm, va, data, ptp)
 #endif /* USE_LOCKSAFE_PSEG_GETSET */
 /*
  * Enter a TTE into the kernel pmap only.  Don't do anything else.
+ *
  * Use only during bootstrapping since it does no locking and
  * can lose ref/mod info!!!!
+ *
  */
 static void pmap_enter_kpage(vaddr_t va, int64_t data)
+{
 	paddr_t newp;
 	newp = 0UL;
 	while (pseg_set(pmap_kernel(), va, data, newp) & 1) {
 		if (!pmap_get_page(&newp)) {
 			prom_printf("pmap_enter_kpage: out of pages\n");
 			panic("pmap_enter_kpage");
+		}
 		ENTER_STAT(ptpneeded);
 		BDPRINTF(PDB_BOOT1,
 			 ("pseg_set: pm=%p va=%p data=%lx newp %lx\n",
 			  pmap_kernel(), va, (long)data, (long)newp));
 		if (pmapdebug & PDB_BOOT1)
 		{int i; for (i=0; i<140000000; i++) ;}
+	}
+}
 /*
  * Check the bootargs to see if we need to enable bootdebug.
  */
 #ifdef DEBUG
 static void pmap_bootdebug(void)
+{
 	const char *cp = prom_getbootargs();
 	for (;;)
 		switch (*++cp) {
 		case '\0':
 			return;
 		case 'V':
 			pmapdebug |= PDB_BOOT|PDB_BOOT1;
 			break;
 		case 'D':
 			pmapdebug |= PDB_BOOT1;
 			break;
+		}
+}
 #else
 #define pmap_bootdebug()	/* nothing */
 #endif
 /*
  * Calculate the correct number of page colors to use.  This should be the
  * size of the E$/PAGE_SIZE.  However, different CPUs can have different sized
  * E$, so we need to take the GCM of the E$ size.
  */
 static int pmap_calculate_colors(void)
+{
 	int node;
 	int size, assoc, color, maxcolor = 1;
 	for (node = prom_firstchild(prom_findroot()); node != 0;
 	     node = prom_nextsibling(node)) {
 		char *name = prom_getpropstring(node, "device_type");
 		if (strcmp("cpu", name) != 0)
 			continue;
 		/* Found a CPU, get the E$ info. */
 		size = prom_getpropint(node, "ecache-size", -1);
 		if (size == -1) {
 			prom_printf("pmap_calculate_colors: node %x has "
 				"no ecache-size\n", node);
 			/* If we can't get the E$ size, skip the node */
 			continue;
+		}
 		assoc = prom_getpropint(node, "ecache-associativity", 1);
 		color = size/assoc/PAGE_SIZE;
 		if (color > maxcolor)
 			maxcolor = color;
+	}
 	return (maxcolor);
+}
 static void pmap_alloc_bootargs(void)
+{
 	char *v;
 	v = OF_claim(NULL, 2*PAGE_SIZE, PAGE_SIZE);
 	if ((v == NULL) || (v == (void*)-1))
 		panic("Can't claim two pages of memory.");
 	memset(v, 0, 2*PAGE_SIZE);
 	cpu_args = (struct cpu_bootargs*)v;
+}
 #if defined(MULTIPROCESSOR)
 static void pmap_mp_init(void);
 static void
 pmap_mp_init(void)
+{
 	pte_t *tp;
 	char *v;
 	int i;
 	extern void cpu_mp_startup(void);
 	if ((v = OF_claim(NULL, PAGE_SIZE, PAGE_SIZE)) == NULL) {
 		panic("pmap_mp_init: Cannot claim a page.");
+	}
 	memcpy(v, mp_tramp_code, mp_tramp_code_len);
 	*(u_long *)(v + mp_tramp_tlb_slots) = kernel_tlb_slots;
 	*(u_long *)(v + mp_tramp_func) = (u_long)cpu_mp_startup;
 	*(u_long *)(v + mp_tramp_ci) = (u_long)cpu_args;
 	tp = (pte_t *)(v + mp_tramp_code_len);
 	for (i = 0; i < kernel_tlb_slots; i++) {
 		tp[i].tag  = kernel_tlbs[i].te_va;
 		tp[i].data = TSB_DATA(0,		/* g */
 				PGSZ_4M,		/* sz */
 				kernel_tlbs[i].te_pa,	/* pa */
 , /* priv */
 , /* write */
 , /* cache */
 , /* aliased */
 , /* valid */
 /* ie */);
 		tp[i].data |= TLB_L | TLB_CV;
 		DPRINTF(PDB_BOOT1, ("xtlb[%d]: Tag: %" PRIx64 " Data: %"
 				PRIx64 "\n", i, tp[i].tag, tp[i].data));
+	}
 	for (i = 0; i < PAGE_SIZE; i += sizeof(long))
 		flush(v + i);
 	cpu_spinup_trampoline = (vaddr_t)v;
+}
 #else
 #define pmap_mp_init()	((void)0)
 #endif
 paddr_t pmap_kextract(vaddr_t va);
 paddr_t
 pmap_kextract(vaddr_t va)
+{
 	int i;
 	paddr_t paddr = (paddr_t)-1;
 	for (i = 0; i < kernel_tlb_slots; i++) {
 		if ((va & ~PAGE_MASK_4M) == kernel_tlbs[i].te_va) {
 			paddr = kernel_tlbs[i].te_pa +
 				(paddr_t)(va & PAGE_MASK_4M);
 			break;
+		}
+	}
 	if (i == kernel_tlb_slots) {
 		panic("pmap_kextract: Address %p is not from kernel space.\n"
 				"Data segment is too small?\n", (void*)va);
+	}
 	return (paddr);
+}
 /*
  * Bootstrap kernel allocator, allocates from unused space in 4MB kernel
  * data segment meaning that
+ *
  * - Access to allocated memory will never generate a trap
  * - Allocated chunks are never reclaimed or freed
  * - Allocation calls do not change PROM memlists
  */
 static struct mem_region kdata_mem_pool;
 static void
 kdata_alloc_init(vaddr_t va_start, vaddr_t va_end)
+{
 	vsize_t va_size = va_end - va_start;
 	kdata_mem_pool.start = va_start;
 	kdata_mem_pool.size  = va_size;
 	BDPRINTF(PDB_BOOT, ("kdata_alloc_init(): %d bytes @%p.\n", va_size,
 				va_start));
+}
 static vaddr_t
 kdata_alloc(vsize_t size, vsize_t align)
+{
 	vaddr_t va;
 	vsize_t asize;
 	asize = roundup(kdata_mem_pool.start, align) - kdata_mem_pool.start;
 	kdata_mem_pool.start += asize;
 	kdata_mem_pool.size  -= asize;
 	if (kdata_mem_pool.size < size) {
 		panic("kdata_alloc(): Data segment is too small.\n");
+	}
 	va = kdata_mem_pool.start;
 	kdata_mem_pool.start += size;
 	kdata_mem_pool.size  -= size;
 	BDPRINTF(PDB_BOOT, ("kdata_alloc(): Allocated %d@%p, %d free.\n",
 				size, (void*)va, kdata_mem_pool.size));
 	return (va);
+}
 /*
  * Unified routine for reading PROM properties.
  */
 static void
 pmap_read_memlist(const char *device, const char *property, void **ml,
 		  int *ml_size, vaddr_t (* ml_alloc)(vsize_t, vsize_t))
+{
 	void *va;
 	int size, handle;
 	if ( (handle = prom_finddevice(device)) == 0) {
 		prom_printf("pmap_read_memlist(): No %s device found.\n",
 				device);
 		prom_halt();
+	}
 	if ( (size = OF_getproplen(handle, property)) < 0) {
 		prom_printf("pmap_read_memlist(): %s/%s has no length.\n",
 				device, property);
 		prom_halt();
+	}
 	if ( (va = (void*)(* ml_alloc)(size, sizeof(uint64_t))) == NULL) {
 		prom_printf("pmap_read_memlist(): Cannot allocate memlist.\n");
 		prom_halt();
+	}
 	if (OF_getprop(handle, property, va, size) <= 0) {
 		prom_printf("pmap_read_memlist(): Cannot read %s/%s.\n",
 				device, property);
 		prom_halt();
+	}
 	*ml = va;
 	*ml_size = size;
+}
 /*
  * This is called during bootstrap, before the system is really initialized.
+ *
  * It's called with the start and end virtual addresses of the kernel.  We
  * bootstrap the pmap allocator now.  We will allocate the basic structures we
  * need to bootstrap the VM system here: the page frame tables, the TSB, and
  * the free memory lists.
+ *
  * Now all this is becoming a bit obsolete.  maxctx is still important, but by
  * separating the kernel text and data segments we really would need to
  * provide the start and end of each segment.  But we can't.  The rodata
  * segment is attached to the end of the kernel segment and has nothing to
  * delimit its end.  We could still pass in the beginning of the kernel and
  * the beginning and end of the data segment but we could also just as easily
  * calculate that all in here.
+ *
  * To handle the kernel text, we need to do a reverse mapping of the start of
  * the kernel, then traverse the free memory lists to find out how big it is.
  */
 void
 pmap_bootstrap(u_long kernelstart, u_long kernelend)
+{
 #ifdef MODULAR
 	extern vaddr_t module_start, module_end;
 #endif
 	extern char etext[], data_start[];	/* start of data segment */
 	extern int msgbufmapped;
 	struct mem_region *mp, *mp1, *avail, *orig;
 	int i, j, pcnt, msgbufsiz;
 	size_t s, sz;
 	int64_t data;
 	vaddr_t va, intstk;
 	uint64_t phys_msgbuf;
 	paddr_t newp = 0;
 	void *prom_memlist;
 	int prom_memlist_size;
 	BDPRINTF(PDB_BOOT, ("Entered pmap_bootstrap.\n"));
 	cache_setup_funcs();
 	/*
 	 * Calculate kernel size.
 	 */
 	ktext   = kernelstart;
 	ktextp  = pmap_kextract(ktext);
 	ektext  = roundup((vaddr_t)etext, PAGE_SIZE_4M);
 	ektextp = roundup(pmap_kextract((vaddr_t)etext), PAGE_SIZE_4M);
 	kdata   = (vaddr_t)data_start;
 	kdatap  = pmap_kextract(kdata);
 	ekdata  = roundup(kernelend, PAGE_SIZE_4M);
 	ekdatap = roundup(pmap_kextract(kernelend), PAGE_SIZE_4M);
 	BDPRINTF(PDB_BOOT, ("Virtual layout: text %lx-%lx, data %lx-%lx.\n",
 				ktext, ektext, kdata, ekdata));
 	BDPRINTF(PDB_BOOT, ("Physical layout: text %lx-%lx, data %lx-%lx.\n",
 				ktextp, ektextp, kdatap, ekdatap));
 	/* Initialize bootstrap allocator. */
 	kdata_alloc_init(kernelend + 1 * 1024 * 1024, ekdata);
 	pmap_bootdebug();
 	pmap_alloc_bootargs();
 	pmap_mp_init();
 	/*
 	 * set machine page size
 	 */
 	uvmexp.pagesize = NBPG;
 	uvmexp.ncolors = pmap_calculate_colors();
 	uvm_setpagesize();
 	/*
 	 * Get hold or the message buffer.
 	 */
 	msgbufp = (struct kern_msgbuf *)(vaddr_t)MSGBUF_VA;
 /* XXXXX -- increase msgbufsiz for uvmhist printing */
 	msgbufsiz = 4*PAGE_SIZE /* round_page(sizeof(struct msgbuf)) */;
 	BDPRINTF(PDB_BOOT, ("Trying to allocate msgbuf at %lx, size %lx\n",
 			    (long)msgbufp, (long)msgbufsiz));
 	if ((long)msgbufp !=
 	    (long)(phys_msgbuf = prom_claim_virt((vaddr_t)msgbufp, msgbufsiz)))
 		prom_printf(
 		    "cannot get msgbuf VA, msgbufp=%p, phys_msgbuf=%lx\n",
 		    (void *)msgbufp, (long)phys_msgbuf);
 	phys_msgbuf = prom_get_msgbuf(msgbufsiz, MMU_PAGE_ALIGN);
 	BDPRINTF(PDB_BOOT,
 		("We should have the memory at %lx, let's map it in\n",
 			phys_msgbuf));
 	if (prom_map_phys(phys_msgbuf, msgbufsiz, (vaddr_t)msgbufp,
 			  -1/* sunos does this */) == -1) {
 		prom_printf("Failed to map msgbuf\n");
 	} else {
 		BDPRINTF(PDB_BOOT, ("msgbuf mapped at %p\n",
 			(void *)msgbufp));
+	}
 	msgbufmapped = 1;	/* enable message buffer */
 	initmsgbuf((void *)msgbufp, msgbufsiz);
 	/*
 	 * Find out how much RAM we have installed.
 	 */
 	BDPRINTF(PDB_BOOT, ("pmap_bootstrap: getting phys installed\n"));
 	pmap_read_memlist("/memory", "reg", &prom_memlist, &prom_memlist_size,
 			kdata_alloc);
 	phys_installed = prom_memlist;
 	phys_installed_size = prom_memlist_size / sizeof(*phys_installed);
 	if (pmapdebug & PDB_BOOT1) {
 		/* print out mem list */
 		prom_printf("Installed physical memory:\n");
 		for (i = 0; i < phys_installed_size; i++) {
 			prom_printf("memlist start %lx size %lx\n",
 					(u_long)phys_installed[i].start,
 					(u_long)phys_installed[i].size);
+		}
+	}
 	BDPRINTF(PDB_BOOT1, ("Calculating physmem:"));
 	for (i = 0; i < phys_installed_size; i++)
 		physmem += btoc(phys_installed[i].size);
 	BDPRINTF(PDB_BOOT1, (" result %x or %d pages\n",
 			     (int)physmem, (int)physmem));
 	/*
 	 * Calculate approx TSB size.  This probably needs tweaking.
 	 */
 	if (physmem < btoc(64 * 1024 * 1024))
 		tsbsize = 0;
 	else if (physmem < btoc(512 * 1024 * 1024))
 		tsbsize = 1;
 	else
 		tsbsize = 2;
 	/*
 	 * Save the prom translations
 	 */
 	pmap_read_memlist("/virtual-memory", "translations", &prom_memlist,
 			&prom_memlist_size, kdata_alloc);
 	prom_map = prom_memlist;
 	prom_map_size = prom_memlist_size / sizeof(struct prom_map);
 	if (pmapdebug & PDB_BOOT) {
 		/* print out mem list */
 		prom_printf("Prom xlations:\n");
 		for (i = 0; i < prom_map_size; i++) {
 			prom_printf("start %016lx size %016lx tte %016lx\n",
 				    (u_long)prom_map[i].vstart,
 				    (u_long)prom_map[i].vsize,
 				    (u_long)prom_map[i].tte);
+		}
 		prom_printf("End of prom xlations\n");
+	}
 	/*
 	 * Here's a quick in-lined reverse bubble sort.  It gets rid of
 	 * any translations inside the kernel data VA range.
 	 */
 	for (i = 0; i < prom_map_size; i++) {
 		for (j = i; j < prom_map_size; j++) {
 			if (prom_map[j].vstart > prom_map[i].vstart) {
 				struct prom_map tmp;
 				tmp = prom_map[i];
 				prom_map[i] = prom_map[j];
 				prom_map[j] = tmp;
+			}
+		}
+	}
 	if (pmapdebug & PDB_BOOT) {
 		/* print out mem list */
 		prom_printf("Prom xlations:\n");
 		for (i = 0; i < prom_map_size; i++) {
 			prom_printf("start %016lx size %016lx tte %016lx\n",
 				    (u_long)prom_map[i].vstart,
 				    (u_long)prom_map[i].vsize,
 				    (u_long)prom_map[i].tte);
+		}
 		prom_printf("End of prom xlations\n");
+	}
 	/*
 	 * Allocate a ncpu*64KB page for the cpu_info & stack structure now.
 	 */
 	cpu0paddr = prom_alloc_phys(8 * PAGE_SIZE * sparc_ncpus, 8 * PAGE_SIZE);
 	if (cpu0paddr == 0) {
 		prom_printf("Cannot allocate cpu_infos\n");
 		prom_halt();
+	}
 	/*
 	 * Now the kernel text segment is in its final location we can try to
 	 * find out how much memory really is free.
 	 */
 	pmap_read_memlist("/memory", "available", &prom_memlist,
 			&prom_memlist_size, kdata_alloc);
 	orig = prom_memlist;
 	sz  = prom_memlist_size;
 	pcnt = prom_memlist_size / sizeof(*orig);
 	BDPRINTF(PDB_BOOT1, ("Available physical memory:\n"));
 	avail = (struct mem_region*)kdata_alloc(sz, sizeof(uint64_t));
 	for (i = 0; i < pcnt; i++) {
 		avail[i] = orig[i];
 		BDPRINTF(PDB_BOOT1, ("memlist start %lx size %lx\n",
 					(u_long)orig[i].start,
 					(u_long)orig[i].size));
+	}
 	BDPRINTF(PDB_BOOT1, ("End of available physical memory\n"));
 	BDPRINTF(PDB_BOOT, ("ktext %08lx[%08lx] - %08lx[%08lx] : "
 				"kdata %08lx[%08lx] - %08lx[%08lx]\n",
 				(u_long)ktext, (u_long)ktextp,
 				(u_long)ektext, (u_long)ektextp,
 				(u_long)kdata, (u_long)kdatap,
 				(u_long)ekdata, (u_long)ekdatap));
 	if (pmapdebug & PDB_BOOT1) {
 		/* print out mem list */
 		prom_printf("Available %lx physical memory before cleanup:\n",
 			    (u_long)avail);
 		for (i = 0; i < pcnt; i++) {
 			prom_printf("memlist start %lx size %lx\n",
 				    (u_long)avail[i].start,
 				    (u_long)avail[i].size);
+		}
 		prom_printf("End of available physical memory before cleanup\n");
 		prom_printf("kernel physical text size %08lx - %08lx\n",
 			    (u_long)ktextp, (u_long)ektextp);
 		prom_printf("kernel physical data size %08lx - %08lx\n",
 			    (u_long)kdatap, (u_long)ekdatap);
+	}
 	/*
 	 * Here's a another quick in-lined bubble sort.
 	 */
 	for (i = 0; i < pcnt; i++) {
 		for (j = i; j < pcnt; j++) {
 			if (avail[j].start < avail[i].start) {
 				struct mem_region tmp;
 				tmp = avail[i];
 				avail[i] = avail[j];
 				avail[j] = tmp;
+			}
+		}
+	}
 	/* Throw away page zero if we have it. */
 	if (avail->start == 0) {
 		avail->start += PAGE_SIZE;
 		avail->size -= PAGE_SIZE;
+	}
 	/*
 	 * Now we need to remove the area we valloc'ed from the available
 	 * memory lists.  (NB: we may have already alloc'ed the entire space).
 	 */
 	npgs = 0;
 	for (mp = avail, i = 0; i < pcnt; i++, mp = &avail[i]) {
 		/*
 		 * Now page align the start of the region.
 		 */
 		s = mp->start % PAGE_SIZE;
 		if (mp->size >= s) {
 			mp->size -= s;
 			mp->start += s;
+		}
 		/*
 		 * And now align the size of the region.
 		 */
 		mp->size -= mp->size % PAGE_SIZE;
 		/*
 		 * Check whether some memory is left here.
 		 */
 		if (mp->size == 0) {
 			memcpy(mp, mp + 1,
 			      (pcnt - (mp - avail)) * sizeof *mp);
 			pcnt--;
 			mp--;
 			continue;
+		}
 		s = mp->start;
 		sz = mp->size;
 		npgs += btoc(sz);
 		for (mp1 = avail; mp1 < mp; mp1++)
 			if (s < mp1->start)
 				break;
 		if (mp1 < mp) {
 			memcpy(mp1 + 1, mp1, (char *)mp - (char *)mp1);
 			mp1->start = s;
 			mp1->size = sz;
+		}
 #ifdef DEBUG
 /* Clear all memory we give to the VM system.  I want to make sure
  * the PROM isn't using it for something, so this should break the PROM.
  */
 /* Calling pmap_zero_page() at this point also hangs some machines
  * so don't do it at all. -- pk 26/02/2002
  */
 #if 0
+		{
 			paddr_t p;
 			for (p = mp->start; p < mp->start+mp->size;
 			     p += PAGE_SIZE)
 				pmap_zero_page(p);
+		}
 #endif
 #endif /* DEBUG */
 		/*
 		 * In future we should be able to specify both allocated
 		 * and free.
 		 */
 		BDPRINTF(PDB_BOOT1, ("uvm_page_physload(%lx, %lx)\n",
 					(long)mp->start,
 					(long)(mp->start + mp->size)));
 		uvm_page_physload(
 			atop(mp->start),
 			atop(mp->start+mp->size),
 			atop(mp->start),
 			atop(mp->start+mp->size),
 			VM_FREELIST_DEFAULT);
+	}
 	if (pmapdebug & PDB_BOOT) {
 		/* print out mem list */
 		prom_printf("Available physical memory after cleanup:\n");
 		for (i = 0; i < pcnt; i++) {
 			prom_printf("avail start %lx size %lx\n",
 				    (long)avail[i].start, (long)avail[i].size);
+		}
 		prom_printf("End of available physical memory after cleanup\n");
+	}
 	/*
 	 * Allocate and clear out pmap_kernel()->pm_segs[]
 	 */
 	pmap_kernel()->pm_refs = 1;
 	memset(&pmap_kernel()->pm_ctx, 0, sizeof(pmap_kernel()->pm_ctx));
 	/* Throw away page zero */
 	do {
 		pmap_get_page(&newp);
 	} while (!newp);
 	pmap_kernel()->pm_segs=(paddr_t *)(u_long)newp;
 	pmap_kernel()->pm_physaddr = newp;
 	/*
 	 * finish filling out kernel pmap.
 	 */
 	BDPRINTF(PDB_BOOT, ("pmap_kernel()->pm_physaddr = %lx\n",
 	    (long)pmap_kernel()->pm_physaddr));
 	/*
 	 * Tell pmap about our mesgbuf -- Hope this works already
 	 */
 	BDPRINTF(PDB_BOOT1, ("Calling consinit()\n"));
 	if (pmapdebug & PDB_BOOT1)
 		consinit();
 	BDPRINTF(PDB_BOOT1, ("Inserting mesgbuf into pmap_kernel()\n"));
 	/* it's not safe to call pmap_enter so we need to do this ourselves */
 	va = (vaddr_t)msgbufp;
 	prom_map_phys(phys_msgbuf, msgbufsiz, (vaddr_t)msgbufp, -1);
 	while (msgbufsiz) {
 		data = TSB_DATA(0 /* global */,
 			PGSZ_8K,
 			phys_msgbuf,
 /* priv */,
 /* Write */,
 /* Cacheable */,
 			FORCE_ALIAS /* ALIAS -- Disable D$ */,
 /* valid */,
 /* IE */);
 		pmap_enter_kpage(va, data);
 		va += PAGE_SIZE;
 		msgbufsiz -= PAGE_SIZE;
 		phys_msgbuf += PAGE_SIZE;
+	}
 	BDPRINTF(PDB_BOOT1, ("Done inserting mesgbuf into pmap_kernel()\n"));
 	BDPRINTF(PDB_BOOT1, ("Inserting PROM mappings into pmap_kernel()\n"));
 	for (i = 0; i < prom_map_size; i++)
 		if (prom_map[i].vstart && ((prom_map[i].vstart >> 32) == 0))
 			for (j = 0; j < prom_map[i].vsize; j += PAGE_SIZE) {
 				int k;
 				for (k = 0; page_size_map[k].mask; k++) {
 					if (((prom_map[i].vstart |
 					      prom_map[i].tte) &
 					      page_size_map[k].mask) == 0 &&
 					      page_size_map[k].mask <
 					      prom_map[i].vsize)
 						break;
+				}
 				page_size_map[k].use++;
 				/* Enter PROM map into pmap_kernel() */
 				pmap_enter_kpage(prom_map[i].vstart + j,
 					(prom_map[i].tte + j) | TLB_EXEC |
 					page_size_map[k].code);
+			}
 	BDPRINTF(PDB_BOOT1, ("Done inserting PROM mappings into pmap_kernel()\n"));
 	/*
 	 * Fix up start of kernel heap.
 	 */
 	vmmap = (vaddr_t)roundup(ekdata, 4*MEG);
 	/* Let's keep 1 page of redzone after the kernel */
 	vmmap += PAGE_SIZE;
+	{
 		extern void main(void);
 		vaddr_t u0va;
 		paddr_t pa;
 		u0va = vmmap;
 		BDPRINTF(PDB_BOOT1,
 			("Inserting lwp0 USPACE into pmap_kernel() at %p\n",
 				vmmap));
 		while (vmmap < u0va + 2*USPACE) {
 			int64_t data1;
 			if (!pmap_get_page(&pa))
 				panic("pmap_bootstrap: no pages");
 			prom_map_phys(pa, PAGE_SIZE, vmmap, -1);
 			data1 = TSB_DATA(0 /* global */,
 				PGSZ_8K,
 				pa,
 /* priv */,
 /* Write */,
 /* Cacheable */,
 				FORCE_ALIAS /* ALIAS -- Disable D$ */,
 /* valid */,
 /* IE */);
 			pmap_enter_kpage(vmmap, data1);
 			vmmap += PAGE_SIZE;
+		}
 		BDPRINTF(PDB_BOOT1,
 			 ("Done inserting stack 0 into pmap_kernel()\n"));
 		/* Now map in and initialize our cpu_info structure */
 #ifdef DIAGNOSTIC
 		vmmap += PAGE_SIZE; /* redzone -- XXXX do we need one? */
 #endif
 		if ((vmmap ^ INTSTACK) & VA_ALIAS_MASK)
 			vmmap += PAGE_SIZE; /* Matchup virtual color for D$ */
 		intstk = vmmap;
 		cpus = (struct cpu_info *)(intstk + CPUINFO_VA - INTSTACK);
 		BDPRINTF(PDB_BOOT1,
 			("Inserting cpu_info into pmap_kernel() at %p\n",
 				 cpus));
 		/* Now map in all 8 pages of interrupt stack/cpu_info */
 		pa = cpu0paddr;
 		prom_map_phys(pa, 64*KB, vmmap, -1);
 		/*
 		 * Also map it in as the interrupt stack.
 		 * This lets the PROM see this if needed.
+		 *
 		 * XXXX locore.s does not flush these mappings
 		 * before installing the locked TTE.
 		 */
 		prom_map_phys(pa, 64*KB, INTSTACK, -1);
 		for (i = 0; i < 8; i++) {
 			int64_t data1;
 			data1 = TSB_DATA(0 /* global */,
 				PGSZ_8K,
 				pa,
 /* priv */,
 /* Write */,
 /* Cacheable */,
 				FORCE_ALIAS /* ALIAS -- Disable D$ */,
 /* valid */,
 /* IE */);
 			pmap_enter_kpage(vmmap, data1);
 			vmmap += PAGE_SIZE;
 			pa += PAGE_SIZE;
+		}
 		BDPRINTF(PDB_BOOT1, ("Initializing cpu_info\n"));
 		/* Initialize our cpu_info structure */
 		memset((void *)intstk, 0, 64 * KB);
 		cpus->ci_self = cpus;
 		cpus->ci_next = NULL;
 		cpus->ci_curlwp = &lwp0;
 		cpus->ci_flags = CPUF_PRIMARY;
 		cpus->ci_cpuid = cpu_myid();
 		cpus->ci_fplwp = NULL;
 		cpus->ci_eintstack = NULL;
 		cpus->ci_spinup = main; /* Call main when we're running. */
 		cpus->ci_paddr = cpu0paddr;
 #ifdef SUN4V
-		if ( CPU_ISSUN4V )
+		if (CPU_ISSUN4V)
 			cpus->ci_mmfsa = cpu0paddr;
 #endif
 		cpus->ci_cpcb = (struct pcb *)u0va;
 		cpus->ci_idepth = -1;
 		memset(cpus->ci_intrpending, -1, sizeof(cpus->ci_intrpending));
 		uvm_lwp_setuarea(&lwp0, u0va);
 		lwp0.l_md.md_tf = (struct trapframe64*)(u0va + USPACE
 		    - sizeof(struct trapframe64));
 		cpu0paddr += 64 * KB;
 		CPUSET_CLEAR(cpus_active);
 		CPUSET_ADD(cpus_active, 0);
 		cpu_pmap_prepare(cpus, true);
 		cpu_pmap_init(cpus);
 		/* The rest will be done at CPU attach time. */
 		BDPRINTF(PDB_BOOT1,
 			 ("Done inserting cpu_info into pmap_kernel()\n"));
+	}
 	vmmap = (vaddr_t)reserve_dumppages((void *)(u_long)vmmap);
 #ifdef MODULAR
 	/*
 	 * For 32bit kernels:
 	 *   Reserve 16 MB of VA for module loading. Right now our full
 	 *   GENERIC kernel is about 13 MB, so this looks good enough.
 	 * For 64bit kernels:
 	 *   We can use all the space left before the special addresses,
 	 *   but leave 2 pages at vmmap alone (see pmap_virtual_space)
 	 *   and another red zone page.
 	 */
 #ifdef __arch64__
 	module_start = vmmap + 3*PAGE_SIZE;
 	module_end = 0x08000000;	/* keep all modules within 2GB */
 	KASSERT(module_end < KERNEND);	/* of kernel text */
 #else
 	module_start = vmmap;
 	vmmap += 16 * 1024*1024;
 	module_end = vmmap;
 #endif
 #endif
 	/*
 	 * Set up bounds of allocatable memory for vmstat et al.
 	 */
 	avail_start = avail->start;
 	for (mp = avail; mp->size; mp++)
 		avail_end = mp->start+mp->size;
 	BDPRINTF(PDB_BOOT1, ("Finished pmap_bootstrap()\n"));
 	BDPRINTF(PDB_BOOT, ("left kdata: %" PRId64 " @%" PRIx64 ".\n",
 				kdata_mem_pool.size, kdata_mem_pool.start));
+}
 /*
  * Allocate TSBs for both mmus from the locked kernel data segment page.
  * This is run before the cpu itself is activated (or by the first cpu
  * itself)
  */
 void
 cpu_pmap_prepare(struct cpu_info *ci, bool initial)
+{
 	/* allocate our TSBs */
 	ci->ci_tsb_dmmu = (pte_t *)kdata_alloc(TSBSIZE, TSBSIZE);
 	ci->ci_tsb_immu = (pte_t *)kdata_alloc(TSBSIZE, TSBSIZE);
 	memset(ci->ci_tsb_dmmu, 0, TSBSIZE);
 	memset(ci->ci_tsb_immu, 0, TSBSIZE);
 	if (!initial) {
 		KASSERT(ci != curcpu());
 		/*
 		 * Initially share ctxbusy with the boot cpu, the
 		 * cpu will replace it as soon as it runs (and can
 		 * probe the number of available contexts itself).
 		 * Untill then only context 0 (aka kernel) will be
 		 * referenced anyway.
 		 */
 		ci->ci_numctx = curcpu()->ci_numctx;
 		ci->ci_ctxbusy = curcpu()->ci_ctxbusy;
+	}
 #ifdef SUN4V
 	if (initial && CPU_ISSUN4V) {
 		tsb_desc = (struct tsb_desc *)kdata_alloc(
 			sizeof(struct tsb_desc), 16);
 		memset(tsb_desc, 0, sizeof(struct tsb_desc));
 		/* 8K page size used for TSB index computation */
 		tsb_desc->td_idxpgsz = 0;
 		tsb_desc->td_assoc = 1;
 		tsb_desc->td_size = TSBENTS;
 		tsb_desc->td_ctxidx = -1;
 		tsb_desc->td_pgsz = 0xf;
 		tsb_desc->td_pa = pmap_kextract((vaddr_t)ci->ci_tsb_dmmu);
 		BDPRINTF(PDB_BOOT1, ("cpu %d: TSB descriptor allocated at %p "
 		    "size %08x - td_pa at %p\n",
 		    ci->ci_index, tsb_desc, sizeof(struct tsb_desc),
 		    tsb_desc->td_pa));
+	}
 #endif
 	BDPRINTF(PDB_BOOT1, ("cpu %d: TSB allocated at %p/%p size %08x\n",
 	    ci->ci_index, ci->ci_tsb_dmmu, ci->ci_tsb_immu, TSBSIZE));
+}
 /*
  * Initialize the per CPU parts for the cpu running this code.
  */
 void
 cpu_pmap_init(struct cpu_info *ci)
+{
 	size_t ctxsize;
 	/*
 	 * We delay initialising ci_ctx_lock here as LOCKDEBUG isn't
 	 * running for cpu0 yet..
 	 */
 	ci->ci_pmap_next_ctx = 1;
 	/* all SUN4U use 13 bit contexts - SUN4V use at least 13 bit contexts */
 	ci->ci_numctx = 0x2000;
 	ctxsize = sizeof(paddr_t)*ci->ci_numctx;
 	ci->ci_ctxbusy = (paddr_t *)kdata_alloc(ctxsize, sizeof(uint64_t));
 	memset(ci->ci_ctxbusy, 0, ctxsize);
 	LIST_INIT(&ci->ci_pmap_ctxlist);
 	/* mark kernel context as busy */
 	ci->ci_ctxbusy[0] = pmap_kernel()->pm_physaddr;
+}
 /*
  * Initialize anything else for pmap handling.
  * Called during vm_init().
  */
 void
 pmap_init(void)
+{
 	struct vm_page *pg;
 	struct pglist pglist;
 	uint64_t data;
 	paddr_t pa;
 	psize_t size;
 	vaddr_t va;
 	BDPRINTF(PDB_BOOT1, ("pmap_init()\n"));
 	size = sizeof(struct pv_entry) * physmem;
 	if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1,
 		(paddr_t)PAGE_SIZE, (paddr_t)0, &pglist, 1, 0) != 0)
 		panic("pmap_init: no memory");
 	va = uvm_km_alloc(kernel_map, size, 0, UVM_KMF_VAONLY);
 	if (va == 0)
 		panic("pmap_init: no memory");
 	/* Map the pages */
 	TAILQ_FOREACH(pg, &pglist, pageq.queue) {
 		pa = VM_PAGE_TO_PHYS(pg);
 		pmap_zero_page(pa);
 		data = TSB_DATA(0 /* global */,
 			PGSZ_8K,
 			pa,
 /* priv */,
 /* Write */,
 /* Cacheable */,
 			FORCE_ALIAS /* ALIAS -- Disable D$ */,
 /* valid */,
 /* IE */);
 		pmap_enter_kpage(va, data);
 		va += PAGE_SIZE;
+	}
 	/*
 	 * initialize the pmap pools.
 	 */
 	pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap),
 	    SPARC64_BLOCK_SIZE, 0, 0, "pmappl", NULL, IPL_NONE, NULL, NULL,
 	    NULL);
 	pool_cache_bootstrap(&pmap_pv_cache, sizeof(struct pv_entry), 0, 0,
 	    PR_LARGECACHE, "pv_entry", NULL, IPL_NONE, NULL, NULL, NULL);
 	vm_first_phys = avail_start;
 	vm_num_phys = avail_end - avail_start;
 	mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE);
 #if defined(USE_LOCKSAFE_PSEG_GETSET)
 	mutex_init(&pseg_lock, MUTEX_SPIN, IPL_VM);
 #endif
 	lock_available = true;
+}
 /*
  * How much virtual space is available to the kernel?
  */
 static vaddr_t kbreak; /* End of kernel VA */
 void
 pmap_virtual_space(vaddr_t *start, vaddr_t *end)
+{
 	/*
 	 * Reserve one segment for kernel virtual memory.
 	 */
 #ifdef __arch64__
 	/*
 	 * On 64 bit kernels, start it beyound firmware, so
 	 * we are basically unrestricted.
 	 */
 	*start = kbreak = VM_KERNEL_MEM_VA_START;
 	*end = VM_MAX_KERNEL_ADDRESS;
 #else
 	/*
 	 * Reserve two pages for pmap_copy_page && /dev/mem, but otherwise
 	 * end it beyound the iospace and other special fixed addresses.
 	 */
 	*start = kbreak = (vaddr_t)(vmmap + 2*PAGE_SIZE);
 	*end = VM_MAX_KERNEL_ADDRESS;
 #endif
 	BDPRINTF(PDB_BOOT1, ("pmap_virtual_space: %x-%x\n", *start, *end));
+}
 /*
  * Preallocate kernel page tables to a specified VA.
  * This simply loops through the first TTE for each
  * page table from the beginning of the kernel pmap,
  * reads the entry, and if the result is
  * zero (either invalid entry or no page table) it stores
  * a zero there, populating page tables in the process.
  * This is not the most efficient technique but i don't
  * expect it to be called that often.
  */
 vaddr_t
 pmap_growkernel(vaddr_t maxkvaddr)
+{
 	struct pmap *pm = pmap_kernel();
 	paddr_t pa;
 	if (maxkvaddr >= VM_MAX_KERNEL_ADDRESS) {
 		printf("WARNING: cannot extend kernel pmap beyond %p to %p\n",
 		       (void *)VM_MAX_KERNEL_ADDRESS, (void *)maxkvaddr);
 		return (kbreak);
+	}
 	DPRINTF(PDB_GROW, ("pmap_growkernel(%lx...%lx)\n", kbreak, maxkvaddr));
 	/* Align with the start of a page table */
 	for (kbreak &= (-1 << PDSHIFT); kbreak < maxkvaddr;
 	     kbreak += (1 << PDSHIFT)) {
 		if (pseg_get(pm, kbreak) & TLB_V)
 			continue;
 		pa = 0;
 		while (pseg_set(pm, kbreak, 0, pa) & 1) {
 			DPRINTF(PDB_GROW,
 			    ("pmap_growkernel: extending %lx\n", kbreak));
 			pa = 0;
 			if (!pmap_get_page(&pa))
 				panic("pmap_growkernel: no pages");
 			ENTER_STAT(ptpneeded);
+		}
+	}
 	return (kbreak);
+}
 /*
  * Create and return a physical map.
  */
 struct pmap *
 pmap_create(void)
+{
 	struct pmap *pm;
 	DPRINTF(PDB_CREATE, ("pmap_create()\n"));
 	pm = pool_cache_get(&pmap_cache, PR_WAITOK);
 	memset(pm, 0, sizeof *pm);
 	DPRINTF(PDB_CREATE, ("pmap_create(): created %p\n", pm));
 	mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE);
 	uvm_obj_init(&pm->pm_obj, NULL, false, 1);
 	uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock);
 	if (pm != pmap_kernel()) {
 		while (!pmap_get_page(&pm->pm_physaddr)) {
 			uvm_wait("pmap_create");
+		}
 		pm->pm_segs = (paddr_t *)(u_long)pm->pm_physaddr;
+	}
 	DPRINTF(PDB_CREATE, ("pmap_create(%p): ctx %d\n", pm, pmap_ctx(pm)));
 	return pm;
+}
 /*
  * Add a reference to the given pmap.
  */
 void
 pmap_reference(struct pmap *pm)
+{
 	atomic_inc_uint(&pm->pm_refs);
+}
 /*
  * Retire the given pmap from service.
  * Should only be called if the map contains no valid mappings.
  */
 void
 pmap_destroy(struct pmap *pm)
+{
 #ifdef MULTIPROCESSOR
 	struct cpu_info *ci;
 	sparc64_cpuset_t pmap_cpus_active;
 #else
 #define pmap_cpus_active 0
 #endif
 	struct vm_page *pg, *nextpg;
 	if ((int)atomic_dec_uint_nv(&pm->pm_refs) > 0) {
 		return;
+	}
 	DPRINTF(PDB_DESTROY, ("pmap_destroy: freeing pmap %p\n", pm));
 #ifdef MULTIPROCESSOR
 	CPUSET_CLEAR(pmap_cpus_active);
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		/* XXXMRG: Move the lock inside one or both tests? */
 		mutex_enter(&ci->ci_ctx_lock);
 		if (CPUSET_HAS(cpus_active, ci->ci_index)) {
 			if (pm->pm_ctx[ci->ci_index] > 0) {
 				CPUSET_ADD(pmap_cpus_active, ci->ci_index);
 				ctx_free(pm, ci);
+			}
+		}
 		mutex_exit(&ci->ci_ctx_lock);
+	}
 #else
 	if (pmap_ctx(pm)) {
 		mutex_enter(&curcpu()->ci_ctx_lock);
 		ctx_free(pm, curcpu());
 		mutex_exit(&curcpu()->ci_ctx_lock);
+	}
 #endif
 	/* we could be a little smarter and leave pages zeroed */
 	for (pg = TAILQ_FIRST(&pm->pm_obj.memq); pg != NULL; pg = nextpg) {
 #ifdef DIAGNOSTIC
 		struct vm_page_md *md = VM_PAGE_TO_MD(pg);
 #endif
 		KASSERT((pg->flags & PG_MARKER) == 0);
 		nextpg = TAILQ_NEXT(pg, listq.queue);
 		TAILQ_REMOVE(&pm->pm_obj.memq, pg, listq.queue);
 		KASSERT(md->mdpg_pvh.pv_pmap == NULL);
 		dcache_flush_page_cpuset(VM_PAGE_TO_PHYS(pg), pmap_cpus_active);
 		uvm_pagefree(pg);
+	}
 	pmap_free_page((paddr_t)(u_long)pm->pm_segs, pmap_cpus_active);
 	uvm_obj_destroy(&pm->pm_obj, false);
 	mutex_destroy(&pm->pm_obj_lock);
 	pool_cache_put(&pmap_cache, pm);
+}
 /*
  * Copy the range specified by src_addr/len
  * from the source map to the range dst_addr/len
  * in the destination map.
+ *
  * This routine is only advisory and need not do anything.
  */
 void
 pmap_copy(struct pmap *dst_pmap, struct pmap *src_pmap, vaddr_t dst_addr, vsize_t len, vaddr_t src_addr)
+{
 	DPRINTF(PDB_CREATE, ("pmap_copy(%p, %p, %p, %lx, %p)\n",
 			     dst_pmap, src_pmap, (void *)(u_long)dst_addr,
 			     (u_long)len, (void *)(u_long)src_addr));
+}
 /*
  * Activate the address space for the specified process.  If the
  * process is the current process, load the new MMU context.
  */
 void
 pmap_activate(struct lwp *l)
+{
 	struct pmap *pmap = l->l_proc->p_vmspace->vm_map.pmap;
 	if (pmap == pmap_kernel()) {
 		return;
+	}
 	/*
 	 * This is essentially the same thing that happens in cpu_switchto()
 	 * when the newly selected process is about to run, except that we
 	 * have to make sure to clean the register windows before we set
 	 * the new context.
 	 */
 	if (l != curlwp) {
 		return;
+	}
 	write_user_windows();
 	pmap_activate_pmap(pmap);
+}
 void
 pmap_activate_pmap(struct pmap *pmap)
+{
 	if (pmap_ctx(pmap) == 0) {
 		(void) ctx_alloc(pmap);
+	}
 	DPRINTF(PDB_ACTIVATE,
 		("%s: cpu%d activating ctx %d\n", __func__,
 		 cpu_number(), pmap_ctx(pmap)));
 	dmmu_set_secondary_context(pmap_ctx(pmap));
+}
 /*
  * Deactivate the address space of the specified process.
  */
 void
 pmap_deactivate(struct lwp *l)
+{
 	DPRINTF(PDB_ACTIVATE,
 		("%s: cpu%d deactivating ctx %d\n", __func__,
 		 cpu_number(), pmap_ctx(l->l_proc->p_vmspace->vm_map.pmap)));
+}
 /*
  * pmap_kenter_pa:		[ INTERFACE ]
+ *
  *	Enter a va -> pa mapping into the kernel pmap without any
  *	physical->virtual tracking.
+ *
  *	Note: no locking is necessary in this function.
  */
 void
 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
+{
 	pte_t tte;
 	paddr_t ptp;
 	struct pmap *pm = pmap_kernel();
 	int i;
 	KASSERT(va < INTSTACK || va > EINTSTACK);
 	KASSERT(va < kdata || va > ekdata);
 	/*
 	 * Construct the TTE.
 	 */
 	ENTER_STAT(unmanaged);
 	if (pa & (PMAP_NVC|PMAP_NC)) {
 		ENTER_STAT(ci);
+	}
 	tte.data = TSB_DATA(0, PGSZ_8K, pa, 1 /* Privileged */,
 			    (VM_PROT_WRITE & prot),
 			    !(pa & PMAP_NC), pa & (PMAP_NVC), 1, 0);
 	/* We don't track mod/ref here. */
 	if (prot & VM_PROT_WRITE)
 		tte.data |= TLB_REAL_W|TLB_W;
 	if (prot & VM_PROT_EXECUTE)
 		tte.data |= TLB_EXEC;
 	tte.data |= TLB_TSB_LOCK;	/* wired */
 	ptp = 0;
  retry:
 	i = pseg_set(pm, va, tte.data, ptp);
 	if (i & 1) {
 		KASSERT((i & 4) == 0);
 		ptp = 0;
 		if (!pmap_get_page(&ptp))
 			panic("pmap_kenter_pa: no pages");
 		ENTER_STAT(ptpneeded);
 		goto retry;
+	}
 	if (ptp && i == 0) {
 		/* We allocated a spare page but didn't use it.  Free it. */
 		printf("pmap_kenter_pa: freeing unused page %llx\n",
 		       (long long)ptp);
 		pmap_free_page_noflush(ptp);
+	}
 #ifdef PMAP_DEBUG
 	i = ptelookup_va(va);
 	if (pmapdebug & PDB_ENTER)
 		prom_printf("pmap_kenter_pa: va=%08x data=%08x:%08x "
 			"tsb_dmmu[%d]=%08x\n", va, (int)(tte.data>>32),
 			(int)tte.data, i, &curcpu()->ci_tsb_dmmu[i]);
 	if (pmapdebug & PDB_MMU_STEAL && curcpu()->ci_tsb_dmmu[i].data) {
 		prom_printf("pmap_kenter_pa: evicting entry tag=%x:%08x "
 			"data=%08x:%08x tsb_dmmu[%d]=%08x\n",
 			(int)(curcpu()->ci_tsb_dmmu[i].tag>>32), (int)curcpu()->ci_tsb_dmmu[i].tag,
 			(int)(curcpu()->ci_tsb_dmmu[i].data>>32), (int)curcpu()->ci_tsb_dmmu[i].data,
 			i, &curcpu()->ci_tsb_dmmu[i]);
 		prom_printf("with va=%08x data=%08x:%08x tsb_dmmu[%d]=%08x\n",
 			va, (int)(tte.data>>32), (int)tte.data,	i,
 			&curcpu()->ci_tsb_dmmu[i]);
+	}
 #endif
+}
 /*
  * pmap_kremove:		[ INTERFACE ]
+ *
  *	Remove a mapping entered with pmap_kenter_pa() starting at va,
  *	for size bytes (assumed to be page rounded).
  */
 void
 pmap_kremove(vaddr_t va, vsize_t size)
+{
 	struct pmap *pm = pmap_kernel();
 	int64_t data;
 	paddr_t pa;
 	int rv;
 	bool flush = FALSE;
 	KASSERT(va < INTSTACK || va > EINTSTACK);
 	KASSERT(va < kdata || va > ekdata);
 	DPRINTF(PDB_DEMAP, ("pmap_kremove: start 0x%lx size %lx\n", va, size));
 	for (; size >= PAGE_SIZE; va += PAGE_SIZE, size -= PAGE_SIZE) {
 #ifdef DIAGNOSTIC
 		/*
 		 * Is this part of the permanent 4MB mapping?
 		 */
 		if (va >= ktext && va < roundup(ekdata, 4*MEG))
 			panic("pmap_kremove: va=%08x in locked TLB", (u_int)va);
 #endif
 		data = pseg_get(pm, va);
 		if ((data & TLB_V) == 0) {
 			continue;
+		}
 		flush = TRUE;
 		pa = data & TLB_PA_MASK;
 		/*
 		 * We need to flip the valid bit and
 		 * clear the access statistics.
 		 */
 		rv = pseg_set(pm, va, 0, 0);
 		if (rv & 1)
 			panic("pmap_kremove: pseg_set needs spare, rv=%d\n",
 			    rv);
 		DPRINTF(PDB_DEMAP, ("pmap_kremove: seg %x pdir %x pte %x\n",
 		    (int)va_to_seg(va), (int)va_to_dir(va),
 		    (int)va_to_pte(va)));
 		REMOVE_STAT(removes);
 		tsb_invalidate(va, pm);
 		REMOVE_STAT(tflushes);
 		/*
 		 * Here we assume nothing can get into the TLB
 		 * unless it has a PTE.
 		 */
 		tlb_flush_pte(va, pm);
 		dcache_flush_page_all(pa);
+	}
 	if (flush)
 		REMOVE_STAT(flushes);
+}
 /*
  * Insert physical page at pa into the given pmap at virtual address va.
  * Supports 64-bit pa so we can map I/O space.
  */
 int
 pmap_enter(struct pmap *pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
+{
 	pte_t tte;
 	int64_t data;
 	paddr_t opa = 0, ptp; /* XXX: gcc */
 	pv_entry_t pvh, npv = NULL, freepv;
 	struct vm_page *pg, *opg, *ptpg;
 	int s, i, uncached = 0, error = 0;
 	int size = PGSZ_8K; /* PMAP_SZ_TO_TTE(pa); */
 	bool wired = (flags & PMAP_WIRED) != 0;
 	bool wasmapped = FALSE;
 	bool dopv = TRUE;
 	/*
 	 * Is this part of the permanent mappings?
 	 */
 	KASSERT(pm != pmap_kernel() || va < INTSTACK || va > EINTSTACK);
 	KASSERT(pm != pmap_kernel() || va < kdata || va > ekdata);
 	/* Grab a spare PV. */
 	freepv = pool_cache_get(&pmap_pv_cache, PR_NOWAIT);
 	if (__predict_false(freepv == NULL)) {
 		if (flags & PMAP_CANFAIL)
 			return (ENOMEM);
 		panic("pmap_enter: no pv entries available");
+	}
 	freepv->pv_next = NULL;
 	/*
 	 * If a mapping at this address already exists, check if we're
 	 * entering the same PA again.  if it's different remove it.
 	 */
 	mutex_enter(&pmap_lock);
 	data = pseg_get(pm, va);
 	if (data & TLB_V) {
 		wasmapped = TRUE;
 		opa = data & TLB_PA_MASK;
 		if (opa != pa) {
 			opg = PHYS_TO_VM_PAGE(opa);
 			if (opg != NULL) {
 				npv = pmap_remove_pv(pm, va, opg);
+			}
+		}
+	}
 	/*
 	 * Construct the TTE.
 	 */
 	pg = PHYS_TO_VM_PAGE(pa);
 	if (pg) {
 		struct vm_page_md * const md = VM_PAGE_TO_MD(pg);
 		pvh = &md->mdpg_pvh;
 		uncached = (pvh->pv_va & (PV_ALIAS|PV_NVC));
 #ifdef DIAGNOSTIC
 		if ((flags & VM_PROT_ALL) & ~prot)
 			panic("pmap_enter: access_type exceeds prot");
 #endif
 		/*
 		 * If we don't have the traphandler do it,
 		 * set the ref/mod bits now.
 		 */
 		if (flags & VM_PROT_ALL)
 			pvh->pv_va |= PV_REF;
 		if (flags & VM_PROT_WRITE)
 			pvh->pv_va |= PV_MOD;
 		/*
 		 * make sure we have a pv entry ready if we need one.
 		 */
 		if (pvh->pv_pmap == NULL || (wasmapped && opa == pa)) {
 			if (npv != NULL) {
 				/* free it */
 				npv->pv_next = freepv;
 				freepv = npv;
 				npv = NULL;
+			}
 			if (wasmapped && opa == pa) {
 				dopv = FALSE;
+			}
 		} else if (npv == NULL) {
 			/* use the pre-allocated pv */
 			npv = freepv;
 			freepv = freepv->pv_next;
+		}
 		ENTER_STAT(managed);
 	} else {
 		ENTER_STAT(unmanaged);
 		dopv = FALSE;
 		if (npv != NULL) {
 			/* free it */
 			npv->pv_next = freepv;
 			freepv = npv;
 			npv = NULL;
+		}
+	}
 #ifndef NO_VCACHE
 	if (pa & PMAP_NVC)
 #endif
 		uncached = 1;
 	if (uncached) {
 		ENTER_STAT(ci);
+	}
 	tte.data = TSB_DATA(0, size, pa, pm == pmap_kernel(),
 		flags & VM_PROT_WRITE, !(pa & PMAP_NC),
 		uncached, 1, pa & PMAP_LITTLE);
 #ifdef HWREF
 	if (prot & VM_PROT_WRITE)
 		tte.data |= TLB_REAL_W;
 	if (prot & VM_PROT_EXECUTE)
 		tte.data |= TLB_EXEC;
 #else
 	/* If it needs ref accounting do nothing. */
 	if (!(flags & VM_PROT_READ)) {
 		mutex_exit(&pmap_lock);
 		goto out;
+	}
 #endif
 	if (flags & VM_PROT_EXECUTE) {
 		if ((flags & (VM_PROT_READ|VM_PROT_WRITE)) == 0)
 			tte.data |= TLB_EXEC_ONLY|TLB_EXEC;
 		else
 			tte.data |= TLB_EXEC;
+	}
 	if (wired)
 		tte.data |= TLB_TSB_LOCK;
 	ptp = 0;
  retry:
 	i = pseg_set(pm, va, tte.data, ptp);
 	if (i == -2) {
 		if (flags & PMAP_CANFAIL)
 			return (ENOMEM);
 		panic("pmap_enter: invalid VA (inside hole)");
+	}
 	if (i & 4) {
 		/* ptp used as L3 */
 		KASSERT(ptp != 0);
 		KASSERT((i & 3) == 0);
 		ptpg = PHYS_TO_VM_PAGE(ptp);
 		if (ptpg) {
 			ptpg->offset = (uint64_t)va & (0xfffffLL << 23);
 			TAILQ_INSERT_TAIL(&pm->pm_obj.memq, ptpg, listq.queue);
 		} else {
 			KASSERT(pm == pmap_kernel());
+		}
+	}
 	if (i & 2) {
 		/* ptp used as L2 */
 		KASSERT(ptp != 0);
 		KASSERT((i & 4) == 0);
 		ptpg = PHYS_TO_VM_PAGE(ptp);
 		if (ptpg) {
 			ptpg->offset = (((uint64_t)va >> 43) & 0x3ffLL) << 13;
 			TAILQ_INSERT_TAIL(&pm->pm_obj.memq, ptpg, listq.queue);
 		} else {
 			KASSERT(pm == pmap_kernel());
+		}
+	}
 	if (i & 1) {
 		KASSERT((i & 4) == 0);
 		ptp = 0;
 		if (!pmap_get_page(&ptp)) {
 			mutex_exit(&pmap_lock);
 			if (flags & PMAP_CANFAIL) {
 				if (npv != NULL) {
 					/* free it */
 					npv->pv_next = freepv;
 					freepv = npv;
+				}
 				error = ENOMEM;
 				goto out;
 			} else {
 				panic("pmap_enter: no pages");
+			}
+		}
 		ENTER_STAT(ptpneeded);
 		goto retry;
+	}
 	if (ptp && i == 0) {
 		/* We allocated a spare page but didn't use it.  Free it. */
 		printf("pmap_enter: freeing unused page %llx\n",
 		       (long long)ptp);
 		pmap_free_page_noflush(ptp);
+	}
 	if (dopv) {
 		pmap_enter_pv(pm, va, pa, pg, npv);
+	}
 	mutex_exit(&pmap_lock);
 #ifdef PMAP_DEBUG
 	i = ptelookup_va(va);
 	if (pmapdebug & PDB_ENTER)
 		prom_printf("pmap_enter: va=%08x data=%08x:%08x "
 			"tsb_dmmu[%d]=%08x\n", va, (int)(tte.data>>32),
 			(int)tte.data, i, &curcpu()->ci_tsb_dmmu[i]);
 	if (pmapdebug & PDB_MMU_STEAL && curcpu()->ci_tsb_dmmu[i].data) {
 		prom_printf("pmap_enter: evicting entry tag=%x:%08x "
 			"data=%08x:%08x tsb_dmmu[%d]=%08x\n",
 			(int)(curcpu()->ci_tsb_dmmu[i].tag>>32), (int)curcpu()->ci_tsb_dmmu[i].tag,
 			(int)(curcpu()->ci_tsb_dmmu[i].data>>32), (int)curcpu()->ci_tsb_dmmu[i].data, i,
 			&curcpu()->ci_tsb_dmmu[i]);
 		prom_printf("with va=%08x data=%08x:%08x tsb_dmmu[%d]=%08x\n",
 			va, (int)(tte.data>>32), (int)tte.data, i,
 			&curcpu()->ci_tsb_dmmu[i]);
+	}
 #endif
 	if (flags & (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE)) {
 		/*
 		 * preload the TSB with the new entry,
 		 * since we're going to need it immediately anyway.
 		 */
 		KASSERT(pmap_ctx(pm)>=0);
 		i = ptelookup_va(va);
 		tte.tag = TSB_TAG(0, pmap_ctx(pm), va);
 		s = splhigh();
 		if (wasmapped && pmap_is_on_mmu(pm)) {
 			tsb_invalidate(va, pm);
+		}
 		if (flags & (VM_PROT_READ | VM_PROT_WRITE)) {
 			curcpu()->ci_tsb_dmmu[i].tag = tte.tag;
 			__asm volatile("" : : : "memory");
 			curcpu()->ci_tsb_dmmu[i].data = tte.data;
+		}
 		if (flags & VM_PROT_EXECUTE) {
 			curcpu()->ci_tsb_immu[i].tag = tte.tag;
 			__asm volatile("" : : : "memory");
 			curcpu()->ci_tsb_immu[i].data = tte.data;
+		}
 		/*
 		 * it's only necessary to flush the TLB if this page was
 		 * previously mapped, but for some reason it's a lot faster
 		 * for the fork+exit microbenchmark if we always do it.
 		 */
 		KASSERT(pmap_ctx(pm)>=0);
 #ifdef MULTIPROCESSOR
 		if (wasmapped && pmap_is_on_mmu(pm))
 			tlb_flush_pte(va, pm);
 		else
 			sp_tlb_flush_pte(va, pmap_ctx(pm));
 #else
 		tlb_flush_pte(va, pm);
 #endif
 		splx(s);
 	} else if (wasmapped && pmap_is_on_mmu(pm)) {
 		/* Force reload -- protections may be changed */
 		KASSERT(pmap_ctx(pm)>=0);
 		tsb_invalidate(va, pm);
 		tlb_flush_pte(va, pm);
+	}
 	/* We will let the fast mmu miss interrupt load the new translation */
 	pv_check();
  out:
 	/* Catch up on deferred frees. */
 	for (; freepv != NULL; freepv = npv) {
 		npv = freepv->pv_next;
 		pool_cache_put(&pmap_pv_cache, freepv);
+	}
 	return error;
+}
 void
 pmap_remove_all(struct pmap *pm)
+{
 #ifdef MULTIPROCESSOR
 	struct cpu_info *ci;
 	sparc64_cpuset_t pmap_cpus_active;
 #endif
 	if (pm == pmap_kernel()) {
 		return;
+	}
 	write_user_windows();
 	pm->pm_refs = 0;
 	/*
 	 * XXXMRG: pmap_destroy() does exactly the same dance here.
 	 * surely one of them isn't necessary?
 	 */
 #ifdef MULTIPROCESSOR
 	CPUSET_CLEAR(pmap_cpus_active);
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		/* XXXMRG: Move the lock inside one or both tests? */
 		mutex_enter(&ci->ci_ctx_lock);
 		if (CPUSET_HAS(cpus_active, ci->ci_index)) {
 			if (pm->pm_ctx[ci->ci_index] > 0) {
 				CPUSET_ADD(pmap_cpus_active, ci->ci_index);
 				ctx_free(pm, ci);
+			}
+		}
 		mutex_exit(&ci->ci_ctx_lock);
+	}
 #else
 	if (pmap_ctx(pm)) {
 		mutex_enter(&curcpu()->ci_ctx_lock);
 		ctx_free(pm, curcpu());
 		mutex_exit(&curcpu()->ci_ctx_lock);
+	}
 #endif
 	REMOVE_STAT(flushes);
 	/*
 	 * XXXMRG: couldn't we do something less severe here, and
 	 * only flush the right context on each CPU?
 	 */
 	blast_dcache();
+}
 /*
  * Remove the given range of mapping entries.
  */
 void
 pmap_remove(struct pmap *pm, vaddr_t va, vaddr_t endva)
+{
 	int64_t data;
 	paddr_t pa;
 	struct vm_page *pg;
 	pv_entry_t pv, freepv = NULL;
 	int rv;
 	bool flush = FALSE;
 	/*
 	 * In here we should check each pseg and if there are no more entries,
 	 * free it.  It's just that linear scans of 8K pages gets expensive.
 	 */
 	KASSERT(pm != pmap_kernel() || endva < INTSTACK || va > EINTSTACK);
 	KASSERT(pm != pmap_kernel() || endva < kdata || va > ekdata);
 	mutex_enter(&pmap_lock);
 	DPRINTF(PDB_REMOVE, ("pmap_remove(pm=%p, va=%p, endva=%p):", pm,
 			     (void *)(u_long)va, (void *)(u_long)endva));
 	REMOVE_STAT(calls);
 	/* Now do the real work */
 	for (; va < endva; va += PAGE_SIZE) {
 #ifdef DIAGNOSTIC
 		/*
 		 * Is this part of the permanent 4MB mapping?
 		 */
 		if (pm == pmap_kernel() && va >= ktext &&
 			va < roundup(ekdata, 4*MEG))
 			panic("pmap_remove: va=%08llx in locked TLB",
 			      (long long)va);
 #endif
 		data = pseg_get(pm, va);
 		if ((data & TLB_V) == 0) {
 			continue;
+		}
 		flush = TRUE;
 		/* First remove the pv entry, if there is one */
 		pa = data & TLB_PA_MASK;
 		pg = PHYS_TO_VM_PAGE(pa);
 		if (pg) {
 			pv = pmap_remove_pv(pm, va, pg);
 			if (pv != NULL) {
 				/* free it */
 				pv->pv_next = freepv;
 				freepv = pv;
+			}
+		}
 		/*
 		 * We need to flip the valid bit and
 		 * clear the access statistics.
 		 */
 		rv = pseg_set(pm, va, 0, 0);
 		if (rv & 1)
 			panic("pmap_remove: pseg_set needed spare, rv=%d!\n",
 			    rv);
 		DPRINTF(PDB_REMOVE, (" clearing seg %x pte %x\n",
 				     (int)va_to_seg(va), (int)va_to_pte(va)));
 		REMOVE_STAT(removes);
 		if (pm != pmap_kernel() && !pmap_has_ctx(pm))
 			continue;
 		/*
 		 * if the pmap is being torn down, don't bother flushing,
 		 * we already have done so.
 		 */
 		if (!pm->pm_refs)
 			continue;
 		/*
 		 * Here we assume nothing can get into the TLB
 		 * unless it has a PTE.
 		 */
 		KASSERT(pmap_ctx(pm)>=0);
 		tsb_invalidate(va, pm);
 		REMOVE_STAT(tflushes);
 		tlb_flush_pte(va, pm);
 		dcache_flush_page_all(pa);
+	}
 	if (flush && pm->pm_refs)
 		REMOVE_STAT(flushes);
 	DPRINTF(PDB_REMOVE, ("\n"));
 	pv_check();
 	mutex_exit(&pmap_lock);
 	/* Catch up on deferred frees. */
 	for (; freepv != NULL; freepv = pv) {
 		pv = freepv->pv_next;
 		pool_cache_put(&pmap_pv_cache, freepv);
+	}
+}
 /*
  * Change the protection on the specified range of this pmap.