| @@ -1,827 +1,838 @@ | | | @@ -1,827 +1,838 @@ |
1 | /* $NetBSD: armreg.h,v 1.84 2013/12/27 12:16:01 matt Exp $ */ | | 1 | /* $NetBSD: armreg.h,v 1.85 2014/01/10 17:48:11 matt Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 1998, 2001 Ben Harris | | 4 | * Copyright (c) 1998, 2001 Ben Harris |
5 | * Copyright (c) 1994-1996 Mark Brinicombe. | | 5 | * Copyright (c) 1994-1996 Mark Brinicombe. |
6 | * Copyright (c) 1994 Brini. | | 6 | * Copyright (c) 1994 Brini. |
7 | * All rights reserved. | | 7 | * All rights reserved. |
8 | * | | 8 | * |
9 | * This code is derived from software written for Brini by Mark Brinicombe | | 9 | * This code is derived from software written for Brini by Mark Brinicombe |
10 | * | | 10 | * |
11 | * Redistribution and use in source and binary forms, with or without | | 11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions | | 12 | * modification, are permitted provided that the following conditions |
13 | * are met: | | 13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright | | 14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. | | 15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright | | 16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the | | 17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. | | 18 | * documentation and/or other materials provided with the distribution. |
19 | * 3. All advertising materials mentioning features or use of this software | | 19 | * 3. All advertising materials mentioning features or use of this software |
20 | * must display the following acknowledgement: | | 20 | * must display the following acknowledgement: |
21 | * This product includes software developed by Brini. | | 21 | * This product includes software developed by Brini. |
22 | * 4. The name of the company nor the name of the author may be used to | | 22 | * 4. The name of the company nor the name of the author may be used to |
23 | * endorse or promote products derived from this software without specific | | 23 | * endorse or promote products derived from this software without specific |
24 | * prior written permission. | | 24 | * prior written permission. |
25 | * | | 25 | * |
26 | * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED | | 26 | * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED |
27 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | | 27 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
28 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | | 28 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
29 | * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, | | 29 | * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
30 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | | 30 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
31 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | | 31 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
32 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 32 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
33 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | | 33 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
34 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | | 34 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
35 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | | 35 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
36 | * SUCH DAMAGE. | | 36 | * SUCH DAMAGE. |
37 | */ | | 37 | */ |
38 | | | 38 | |
39 | #ifndef _ARM_ARMREG_H | | 39 | #ifndef _ARM_ARMREG_H |
40 | #define _ARM_ARMREG_H | | 40 | #define _ARM_ARMREG_H |
41 | | | 41 | |
42 | /* | | 42 | /* |
43 | * ARM Process Status Register | | 43 | * ARM Process Status Register |
44 | * | | 44 | * |
45 | * The picture in the ARM manuals looks like this: | | 45 | * The picture in the ARM manuals looks like this: |
46 | * 3 3 2 2 2 2 | | 46 | * 3 3 2 2 2 2 |
47 | * 1 0 9 8 7 6 8 7 6 5 4 0 | | 47 | * 1 0 9 8 7 6 8 7 6 5 4 0 |
48 | * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ | | 48 | * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ |
49 | * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| | | 49 | * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| |
50 | * | | | | | | | | | |4 3 2 1 0| | | 50 | * | | | | | | | | | |4 3 2 1 0| |
51 | * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ | | 51 | * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ |
52 | */ | | 52 | */ |
53 | | | 53 | |
54 | #define PSR_FLAGS 0xf0000000 /* flags */ | | 54 | #define PSR_FLAGS 0xf0000000 /* flags */ |
55 | #define PSR_N_bit (1 << 31) /* negative */ | | 55 | #define PSR_N_bit (1 << 31) /* negative */ |
56 | #define PSR_Z_bit (1 << 30) /* zero */ | | 56 | #define PSR_Z_bit (1 << 30) /* zero */ |
57 | #define PSR_C_bit (1 << 29) /* carry */ | | 57 | #define PSR_C_bit (1 << 29) /* carry */ |
58 | #define PSR_V_bit (1 << 28) /* overflow */ | | 58 | #define PSR_V_bit (1 << 28) /* overflow */ |
59 | | | 59 | |
60 | #define PSR_Q_bit (1 << 27) /* saturation */ | | 60 | #define PSR_Q_bit (1 << 27) /* saturation */ |
| | | 61 | #define PSR_IT1_bit (1 << 26) |
| | | 62 | #define PSR_IT0_bit (1 << 25) |
| | | 63 | #define PSR_J_bit (1 << 24) /* Jazelle mode */ |
| | | 64 | #define PSR_GE_bits (15 << 16) /* SIMD GE bits */ |
| | | 65 | #define PSR_IT7_bit (1 << 15) |
| | | 66 | #define PSR_IT6_bit (1 << 14) |
| | | 67 | #define PSR_IT5_bit (1 << 13) |
| | | 68 | #define PSR_IT4_bit (1 << 12) |
| | | 69 | #define PSR_IT3_bit (1 << 11) |
| | | 70 | #define PSR_IT2_bit (1 << 10) |
| | | 71 | #define PSR_E_BIT (1 << 9) /* Endian state */ |
| | | 72 | #define PSR_A_BIT (1 << 8) /* Async abort disable */ |
61 | | | 73 | |
62 | #define I32_bit (1 << 7) /* IRQ disable */ | | 74 | #define I32_bit (1 << 7) /* IRQ disable */ |
63 | #define F32_bit (1 << 6) /* FIQ disable */ | | 75 | #define F32_bit (1 << 6) /* FIQ disable */ |
64 | #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ | | 76 | #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ |
65 | | | 77 | |
66 | #define PSR_T_bit (1 << 5) /* Thumb state */ | | 78 | #define PSR_T_bit (1 << 5) /* Thumb state */ |
67 | #define PSR_J_bit (1 << 24) /* Java mode */ | | | |
68 | | | 79 | |
69 | #define PSR_MODE 0x0000001f /* mode mask */ | | 80 | #define PSR_MODE 0x0000001f /* mode mask */ |
70 | #define PSR_USR26_MODE 0x00000000 | | 81 | #define PSR_USR26_MODE 0x00000000 |
71 | #define PSR_FIQ26_MODE 0x00000001 | | 82 | #define PSR_FIQ26_MODE 0x00000001 |
72 | #define PSR_IRQ26_MODE 0x00000002 | | 83 | #define PSR_IRQ26_MODE 0x00000002 |
73 | #define PSR_SVC26_MODE 0x00000003 | | 84 | #define PSR_SVC26_MODE 0x00000003 |
74 | #define PSR_USR32_MODE 0x00000010 | | 85 | #define PSR_USR32_MODE 0x00000010 |
75 | #define PSR_FIQ32_MODE 0x00000011 | | 86 | #define PSR_FIQ32_MODE 0x00000011 |
76 | #define PSR_IRQ32_MODE 0x00000012 | | 87 | #define PSR_IRQ32_MODE 0x00000012 |
77 | #define PSR_SVC32_MODE 0x00000013 | | 88 | #define PSR_SVC32_MODE 0x00000013 |
78 | #define PSR_MON32_MODE 0x00000016 | | 89 | #define PSR_MON32_MODE 0x00000016 |
79 | #define PSR_ABT32_MODE 0x00000017 | | 90 | #define PSR_ABT32_MODE 0x00000017 |
80 | #define PSR_HYP32_MODE 0x0000001a | | 91 | #define PSR_HYP32_MODE 0x0000001a |
81 | #define PSR_UND32_MODE 0x0000001b | | 92 | #define PSR_UND32_MODE 0x0000001b |
82 | #define PSR_SYS32_MODE 0x0000001f | | 93 | #define PSR_SYS32_MODE 0x0000001f |
83 | #define PSR_32_MODE 0x00000010 | | 94 | #define PSR_32_MODE 0x00000010 |
84 | | | 95 | |
85 | #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ | | 96 | #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ |
86 | #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) | | 97 | #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) |
87 | | | 98 | |
88 | /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ | | 99 | /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ |
89 | | | 100 | |
90 | #define R15_MODE 0x00000003 | | 101 | #define R15_MODE 0x00000003 |
91 | #define R15_MODE_USR 0x00000000 | | 102 | #define R15_MODE_USR 0x00000000 |
92 | #define R15_MODE_FIQ 0x00000001 | | 103 | #define R15_MODE_FIQ 0x00000001 |
93 | #define R15_MODE_IRQ 0x00000002 | | 104 | #define R15_MODE_IRQ 0x00000002 |
94 | #define R15_MODE_SVC 0x00000003 | | 105 | #define R15_MODE_SVC 0x00000003 |
95 | | | 106 | |
96 | #define R15_PC 0x03fffffc | | 107 | #define R15_PC 0x03fffffc |
97 | | | 108 | |
98 | #define R15_FIQ_DISABLE 0x04000000 | | 109 | #define R15_FIQ_DISABLE 0x04000000 |
99 | #define R15_IRQ_DISABLE 0x08000000 | | 110 | #define R15_IRQ_DISABLE 0x08000000 |
100 | | | 111 | |
101 | #define R15_FLAGS 0xf0000000 | | 112 | #define R15_FLAGS 0xf0000000 |
102 | #define R15_FLAG_N 0x80000000 | | 113 | #define R15_FLAG_N 0x80000000 |
103 | #define R15_FLAG_Z 0x40000000 | | 114 | #define R15_FLAG_Z 0x40000000 |
104 | #define R15_FLAG_C 0x20000000 | | 115 | #define R15_FLAG_C 0x20000000 |
105 | #define R15_FLAG_V 0x10000000 | | 116 | #define R15_FLAG_V 0x10000000 |
106 | | | 117 | |
107 | /* | | 118 | /* |
108 | * Co-processor 15: The system control co-processor. | | 119 | * Co-processor 15: The system control co-processor. |
109 | */ | | 120 | */ |
110 | | | 121 | |
111 | #define ARM_CP15_CPU_ID 0 | | 122 | #define ARM_CP15_CPU_ID 0 |
112 | | | 123 | |
113 | /* | | 124 | /* |
114 | * The CPU ID register is theoretically structured, but the definitions of | | 125 | * The CPU ID register is theoretically structured, but the definitions of |
115 | * the fields keep changing. | | 126 | * the fields keep changing. |
116 | */ | | 127 | */ |
117 | | | 128 | |
118 | /* The high-order byte is always the implementor */ | | 129 | /* The high-order byte is always the implementor */ |
119 | #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 | | 130 | #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 |
120 | #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ | | 131 | #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ |
121 | #define CPU_ID_DEC 0x44000000 /* 'D' */ | | 132 | #define CPU_ID_DEC 0x44000000 /* 'D' */ |
122 | #define CPU_ID_INTEL 0x69000000 /* 'i' */ | | 133 | #define CPU_ID_INTEL 0x69000000 /* 'i' */ |
123 | #define CPU_ID_TI 0x54000000 /* 'T' */ | | 134 | #define CPU_ID_TI 0x54000000 /* 'T' */ |
124 | #define CPU_ID_MARVELL 0x56000000 /* 'V' */ | | 135 | #define CPU_ID_MARVELL 0x56000000 /* 'V' */ |
125 | #define CPU_ID_FARADAY 0x66000000 /* 'f' */ | | 136 | #define CPU_ID_FARADAY 0x66000000 /* 'f' */ |
126 | | | 137 | |
127 | /* How to decide what format the CPUID is in. */ | | 138 | /* How to decide what format the CPUID is in. */ |
128 | #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) | | 139 | #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) |
129 | #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) | | 140 | #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) |
130 | #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) | | 141 | #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) |
131 | | | 142 | |
132 | /* On ARM3 and ARM6, this byte holds the foundry ID. */ | | 143 | /* On ARM3 and ARM6, this byte holds the foundry ID. */ |
133 | #define CPU_ID_FOUNDRY_MASK 0x00ff0000 | | 144 | #define CPU_ID_FOUNDRY_MASK 0x00ff0000 |
134 | #define CPU_ID_FOUNDRY_VLSI 0x00560000 | | 145 | #define CPU_ID_FOUNDRY_VLSI 0x00560000 |
135 | | | 146 | |
136 | /* On ARM7 it holds the architecture and variant (sub-model) */ | | 147 | /* On ARM7 it holds the architecture and variant (sub-model) */ |
137 | #define CPU_ID_7ARCH_MASK 0x00800000 | | 148 | #define CPU_ID_7ARCH_MASK 0x00800000 |
138 | #define CPU_ID_7ARCH_V3 0x00000000 | | 149 | #define CPU_ID_7ARCH_V3 0x00000000 |
139 | #define CPU_ID_7ARCH_V4T 0x00800000 | | 150 | #define CPU_ID_7ARCH_V4T 0x00800000 |
140 | #define CPU_ID_7VARIANT_MASK 0x007f0000 | | 151 | #define CPU_ID_7VARIANT_MASK 0x007f0000 |
141 | | | 152 | |
142 | /* On more recent ARMs, it does the same, but in a different format */ | | 153 | /* On more recent ARMs, it does the same, but in a different format */ |
143 | #define CPU_ID_ARCH_MASK 0x000f0000 | | 154 | #define CPU_ID_ARCH_MASK 0x000f0000 |
144 | #define CPU_ID_ARCH_V3 0x00000000 | | 155 | #define CPU_ID_ARCH_V3 0x00000000 |
145 | #define CPU_ID_ARCH_V4 0x00010000 | | 156 | #define CPU_ID_ARCH_V4 0x00010000 |
146 | #define CPU_ID_ARCH_V4T 0x00020000 | | 157 | #define CPU_ID_ARCH_V4T 0x00020000 |
147 | #define CPU_ID_ARCH_V5 0x00030000 | | 158 | #define CPU_ID_ARCH_V5 0x00030000 |
148 | #define CPU_ID_ARCH_V5T 0x00040000 | | 159 | #define CPU_ID_ARCH_V5T 0x00040000 |
149 | #define CPU_ID_ARCH_V5TE 0x00050000 | | 160 | #define CPU_ID_ARCH_V5TE 0x00050000 |
150 | #define CPU_ID_ARCH_V5TEJ 0x00060000 | | 161 | #define CPU_ID_ARCH_V5TEJ 0x00060000 |
151 | #define CPU_ID_ARCH_V6 0x00070000 | | 162 | #define CPU_ID_ARCH_V6 0x00070000 |
152 | #define CPU_ID_VARIANT_MASK 0x00f00000 | | 163 | #define CPU_ID_VARIANT_MASK 0x00f00000 |
153 | | | 164 | |
154 | /* Next three nybbles are part number */ | | 165 | /* Next three nybbles are part number */ |
155 | #define CPU_ID_PARTNO_MASK 0x0000fff0 | | 166 | #define CPU_ID_PARTNO_MASK 0x0000fff0 |
156 | | | 167 | |
157 | /* Intel XScale has sub fields in part number */ | | 168 | /* Intel XScale has sub fields in part number */ |
158 | #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ | | 169 | #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ |
159 | #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ | | 170 | #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ |
160 | #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ | | 171 | #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ |
161 | | | 172 | |
162 | /* And finally, the revision number. */ | | 173 | /* And finally, the revision number. */ |
163 | #define CPU_ID_REVISION_MASK 0x0000000f | | 174 | #define CPU_ID_REVISION_MASK 0x0000000f |
164 | | | 175 | |
165 | /* Individual CPUs are probably best IDed by everything but the revision. */ | | 176 | /* Individual CPUs are probably best IDed by everything but the revision. */ |
166 | #define CPU_ID_CPU_MASK 0xfffffff0 | | 177 | #define CPU_ID_CPU_MASK 0xfffffff0 |
167 | | | 178 | |
168 | /* Fake CPU IDs for ARMs without CP15 */ | | 179 | /* Fake CPU IDs for ARMs without CP15 */ |
169 | #define CPU_ID_ARM2 0x41560200 | | 180 | #define CPU_ID_ARM2 0x41560200 |
170 | #define CPU_ID_ARM250 0x41560250 | | 181 | #define CPU_ID_ARM250 0x41560250 |
171 | | | 182 | |
172 | /* Pre-ARM7 CPUs -- [15:12] == 0 */ | | 183 | /* Pre-ARM7 CPUs -- [15:12] == 0 */ |
173 | #define CPU_ID_ARM3 0x41560300 | | 184 | #define CPU_ID_ARM3 0x41560300 |
174 | #define CPU_ID_ARM600 0x41560600 | | 185 | #define CPU_ID_ARM600 0x41560600 |
175 | #define CPU_ID_ARM610 0x41560610 | | 186 | #define CPU_ID_ARM610 0x41560610 |
176 | #define CPU_ID_ARM620 0x41560620 | | 187 | #define CPU_ID_ARM620 0x41560620 |
177 | | | 188 | |
178 | /* ARM7 CPUs -- [15:12] == 7 */ | | 189 | /* ARM7 CPUs -- [15:12] == 7 */ |
179 | #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ | | 190 | #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ |
180 | #define CPU_ID_ARM710 0x41007100 | | 191 | #define CPU_ID_ARM710 0x41007100 |
181 | #define CPU_ID_ARM7500 0x41027100 | | 192 | #define CPU_ID_ARM7500 0x41027100 |
182 | #define CPU_ID_ARM710A 0x41067100 | | 193 | #define CPU_ID_ARM710A 0x41067100 |
183 | #define CPU_ID_ARM7500FE 0x41077100 | | 194 | #define CPU_ID_ARM7500FE 0x41077100 |
184 | #define CPU_ID_ARM710T 0x41807100 | | 195 | #define CPU_ID_ARM710T 0x41807100 |
185 | #define CPU_ID_ARM720T 0x41807200 | | 196 | #define CPU_ID_ARM720T 0x41807200 |
186 | #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ | | 197 | #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ |
187 | #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ | | 198 | #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ |
188 | | | 199 | |
189 | /* Post-ARM7 CPUs */ | | 200 | /* Post-ARM7 CPUs */ |
190 | #define CPU_ID_ARM810 0x41018100 | | 201 | #define CPU_ID_ARM810 0x41018100 |
191 | #define CPU_ID_ARM920T 0x41129200 | | 202 | #define CPU_ID_ARM920T 0x41129200 |
192 | #define CPU_ID_ARM922T 0x41029220 | | 203 | #define CPU_ID_ARM922T 0x41029220 |
193 | #define CPU_ID_ARM926EJS 0x41069260 | | 204 | #define CPU_ID_ARM926EJS 0x41069260 |
194 | #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ | | 205 | #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ |
195 | #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ | | 206 | #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ |
196 | #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ | | 207 | #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ |
197 | #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ | | 208 | #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ |
198 | #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ | | 209 | #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ |
199 | #define CPU_ID_ARM1022ES 0x4105a220 | | 210 | #define CPU_ID_ARM1022ES 0x4105a220 |
200 | #define CPU_ID_ARM1026EJS 0x4106a260 | | 211 | #define CPU_ID_ARM1026EJS 0x4106a260 |
201 | #define CPU_ID_ARM11MPCORE 0x410fb020 | | 212 | #define CPU_ID_ARM11MPCORE 0x410fb020 |
202 | #define CPU_ID_ARM1136JS 0x4107b360 | | 213 | #define CPU_ID_ARM1136JS 0x4107b360 |
203 | #define CPU_ID_ARM1136JSR1 0x4117b360 | | 214 | #define CPU_ID_ARM1136JSR1 0x4117b360 |
204 | #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ | | 215 | #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ |
205 | #define CPU_ID_ARM1176JZS 0x410fb760 | | 216 | #define CPU_ID_ARM1176JZS 0x410fb760 |
206 | #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) | | 217 | #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) |
207 | #define CPU_ID_CORTEXA5R0 0x410fc050 | | 218 | #define CPU_ID_CORTEXA5R0 0x410fc050 |
208 | #define CPU_ID_CORTEXA7R0 0x410fc070 | | 219 | #define CPU_ID_CORTEXA7R0 0x410fc070 |
209 | #define CPU_ID_CORTEXA8R1 0x411fc080 | | 220 | #define CPU_ID_CORTEXA8R1 0x411fc080 |
210 | #define CPU_ID_CORTEXA8R2 0x412fc080 | | 221 | #define CPU_ID_CORTEXA8R2 0x412fc080 |
211 | #define CPU_ID_CORTEXA8R3 0x413fc080 | | 222 | #define CPU_ID_CORTEXA8R3 0x413fc080 |
212 | #define CPU_ID_CORTEXA9R2 0x411fc090 | | 223 | #define CPU_ID_CORTEXA9R2 0x411fc090 |
213 | #define CPU_ID_CORTEXA9R3 0x412fc090 | | 224 | #define CPU_ID_CORTEXA9R3 0x412fc090 |
214 | #define CPU_ID_CORTEXA9R4 0x413fc090 | | 225 | #define CPU_ID_CORTEXA9R4 0x413fc090 |
215 | #define CPU_ID_CORTEXA15R2 0x412fc0f0 | | 226 | #define CPU_ID_CORTEXA15R2 0x412fc0f0 |
216 | #define CPU_ID_CORTEXA15R3 0x413fc0f0 | | 227 | #define CPU_ID_CORTEXA15R3 0x413fc0f0 |
217 | #define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000) | | 228 | #define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000) |
218 | #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) | | 229 | #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) |
219 | #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) | | 230 | #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) |
220 | #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) | | 231 | #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) |
221 | #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) | | 232 | #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) |
222 | #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) | | 233 | #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) |
223 | #define CPU_ID_SA110 0x4401a100 | | 234 | #define CPU_ID_SA110 0x4401a100 |
224 | #define CPU_ID_SA1100 0x4401a110 | | 235 | #define CPU_ID_SA1100 0x4401a110 |
225 | #define CPU_ID_TI925T 0x54029250 | | 236 | #define CPU_ID_TI925T 0x54029250 |
226 | #define CPU_ID_MV88FR571_VD 0x56155710 | | 237 | #define CPU_ID_MV88FR571_VD 0x56155710 |
227 | #define CPU_ID_MV88SV131 0x56251310 | | 238 | #define CPU_ID_MV88SV131 0x56251310 |
228 | #define CPU_ID_FA526 0x66015260 | | 239 | #define CPU_ID_FA526 0x66015260 |
229 | #define CPU_ID_SA1110 0x6901b110 | | 240 | #define CPU_ID_SA1110 0x6901b110 |
230 | #define CPU_ID_IXP1200 0x6901c120 | | 241 | #define CPU_ID_IXP1200 0x6901c120 |
231 | #define CPU_ID_80200 0x69052000 | | 242 | #define CPU_ID_80200 0x69052000 |
232 | #define CPU_ID_PXA250 0x69052100 /* sans core revision */ | | 243 | #define CPU_ID_PXA250 0x69052100 /* sans core revision */ |
233 | #define CPU_ID_PXA210 0x69052120 | | 244 | #define CPU_ID_PXA210 0x69052120 |
234 | #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ | | 245 | #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ |
235 | #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ | | 246 | #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ |
236 | #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ | | 247 | #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ |
237 | #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ | | 248 | #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ |
238 | #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ | | 249 | #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ |
239 | #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ | | 250 | #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ |
240 | #define CPU_ID_PXA27X 0x69054110 | | 251 | #define CPU_ID_PXA27X 0x69054110 |
241 | #define CPU_ID_80321_400 0x69052420 | | 252 | #define CPU_ID_80321_400 0x69052420 |
242 | #define CPU_ID_80321_600 0x69052430 | | 253 | #define CPU_ID_80321_600 0x69052430 |
243 | #define CPU_ID_80321_400_B0 0x69052c20 | | 254 | #define CPU_ID_80321_400_B0 0x69052c20 |
244 | #define CPU_ID_80321_600_B0 0x69052c30 | | 255 | #define CPU_ID_80321_600_B0 0x69052c30 |
245 | #define CPU_ID_80219_400 0x69052e20 | | 256 | #define CPU_ID_80219_400 0x69052e20 |
246 | #define CPU_ID_80219_600 0x69052e30 | | 257 | #define CPU_ID_80219_600 0x69052e30 |
247 | #define CPU_ID_IXP425_533 0x690541c0 | | 258 | #define CPU_ID_IXP425_533 0x690541c0 |
248 | #define CPU_ID_IXP425_400 0x690541d0 | | 259 | #define CPU_ID_IXP425_400 0x690541d0 |
249 | #define CPU_ID_IXP425_266 0x690541f0 | | 260 | #define CPU_ID_IXP425_266 0x690541f0 |
250 | #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) | | 261 | #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) |
251 | #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ | | 262 | #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ |
252 | #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ | | 263 | #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ |
253 | #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ | | 264 | #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ |
254 | #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ | | 265 | #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ |
255 | /* Marvell's CPUIDs with ARM ID in implementor field */ | | 266 | /* Marvell's CPUIDs with ARM ID in implementor field */ |
256 | #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ | | 267 | #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ |
257 | #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ | | 268 | #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ |
258 | #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ | | 269 | #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ |
259 | | | 270 | |
260 | /* CPUID registers */ | | 271 | /* CPUID registers */ |
261 | #define ARM_PFR0_THUMBEE_MASK 0x0000f000 | | 272 | #define ARM_PFR0_THUMBEE_MASK 0x0000f000 |
262 | #define ARM_PFR1_GTIMER_MASK 0x000f0000 | | 273 | #define ARM_PFR1_GTIMER_MASK 0x000f0000 |
263 | #define ARM_PFR1_VIRT_MASK 0x0000f000 | | 274 | #define ARM_PFR1_VIRT_MASK 0x0000f000 |
264 | #define ARM_PFR1_SEC_MASK 0x000000f0 | | 275 | #define ARM_PFR1_SEC_MASK 0x000000f0 |
265 | | | 276 | |
266 | /* Media and VFP Feature registers */ | | 277 | /* Media and VFP Feature registers */ |
267 | #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 | | 278 | #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 |
268 | #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 | | 279 | #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 |
269 | #define ARM_MVFR0_SQRT_MASK 0x00f00000 | | 280 | #define ARM_MVFR0_SQRT_MASK 0x00f00000 |
270 | #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 | | 281 | #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 |
271 | #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 | | 282 | #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 |
272 | #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 | | 283 | #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 |
273 | #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 | | 284 | #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 |
274 | #define ARM_MVFR0_ASIMD_MASK 0x0000000f | | 285 | #define ARM_MVFR0_ASIMD_MASK 0x0000000f |
275 | #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 | | 286 | #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 |
276 | #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 | | 287 | #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 |
277 | #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 | | 288 | #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 |
278 | #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 | | 289 | #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 |
279 | #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 | | 290 | #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 |
280 | #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 | | 291 | #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 |
281 | #define ARM_MVFR1_D_NAN_MASK 0x000000f0 | | 292 | #define ARM_MVFR1_D_NAN_MASK 0x000000f0 |
282 | #define ARM_MVFR1_FTZ_MASK 0x0000000f | | 293 | #define ARM_MVFR1_FTZ_MASK 0x0000000f |
283 | | | 294 | |
284 | /* ARM3-specific coprocessor 15 registers */ | | 295 | /* ARM3-specific coprocessor 15 registers */ |
285 | #define ARM3_CP15_FLUSH 1 | | 296 | #define ARM3_CP15_FLUSH 1 |
286 | #define ARM3_CP15_CONTROL 2 | | 297 | #define ARM3_CP15_CONTROL 2 |
287 | #define ARM3_CP15_CACHEABLE 3 | | 298 | #define ARM3_CP15_CACHEABLE 3 |
288 | #define ARM3_CP15_UPDATEABLE 4 | | 299 | #define ARM3_CP15_UPDATEABLE 4 |
289 | #define ARM3_CP15_DISRUPTIVE 5 | | 300 | #define ARM3_CP15_DISRUPTIVE 5 |
290 | | | 301 | |
291 | /* ARM3 Control register bits */ | | 302 | /* ARM3 Control register bits */ |
292 | #define ARM3_CTL_CACHE_ON 0x00000001 | | 303 | #define ARM3_CTL_CACHE_ON 0x00000001 |
293 | #define ARM3_CTL_SHARED 0x00000002 | | 304 | #define ARM3_CTL_SHARED 0x00000002 |
294 | #define ARM3_CTL_MONITOR 0x00000004 | | 305 | #define ARM3_CTL_MONITOR 0x00000004 |
295 | | | 306 | |
296 | /* | | 307 | /* |
297 | * Post-ARM3 CP15 registers: | | 308 | * Post-ARM3 CP15 registers: |
298 | * | | 309 | * |
299 | * 1 Control register | | 310 | * 1 Control register |
300 | * | | 311 | * |
301 | * 2 Translation Table Base | | 312 | * 2 Translation Table Base |
302 | * | | 313 | * |
303 | * 3 Domain Access Control | | 314 | * 3 Domain Access Control |
304 | * | | 315 | * |
305 | * 4 Reserved | | 316 | * 4 Reserved |
306 | * | | 317 | * |
307 | * 5 Fault Status | | 318 | * 5 Fault Status |
308 | * | | 319 | * |
309 | * 6 Fault Address | | 320 | * 6 Fault Address |
310 | * | | 321 | * |
311 | * 7 Cache/write-buffer Control | | 322 | * 7 Cache/write-buffer Control |
312 | * | | 323 | * |
313 | * 8 TLB Control | | 324 | * 8 TLB Control |
314 | * | | 325 | * |
315 | * 9 Cache Lockdown | | 326 | * 9 Cache Lockdown |
316 | * | | 327 | * |
317 | * 10 TLB Lockdown | | 328 | * 10 TLB Lockdown |
318 | * | | 329 | * |
319 | * 11 Reserved | | 330 | * 11 Reserved |
320 | * | | 331 | * |
321 | * 12 Reserved | | 332 | * 12 Reserved |
322 | * | | 333 | * |
323 | * 13 Process ID (for FCSE) | | 334 | * 13 Process ID (for FCSE) |
324 | * | | 335 | * |
325 | * 14 Reserved | | 336 | * 14 Reserved |
326 | * | | 337 | * |
327 | * 15 Implementation Dependent | | 338 | * 15 Implementation Dependent |
328 | */ | | 339 | */ |
329 | | | 340 | |
330 | /* Some of the definitions below need cleaning up for V3/V4 architectures */ | | 341 | /* Some of the definitions below need cleaning up for V3/V4 architectures */ |
331 | | | 342 | |
332 | /* CPU control register (CP15 register 1) */ | | 343 | /* CPU control register (CP15 register 1) */ |
333 | #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ | | 344 | #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ |
334 | #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ | | 345 | #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ |
335 | #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ | | 346 | #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ |
336 | #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ | | 347 | #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ |
337 | #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ | | 348 | #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ |
338 | #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ | | 349 | #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ |
339 | #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ | | 350 | #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ |
340 | #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ | | 351 | #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ |
341 | #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ | | 352 | #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ |
342 | #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ | | 353 | #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ |
343 | #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ | | 354 | #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ |
344 | #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ | | 355 | #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ |
345 | #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ | | 356 | #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ |
346 | #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ | | 357 | #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ |
347 | #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ | | 358 | #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ |
348 | #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ | | 359 | #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ |
349 | #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ | | 360 | #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ |
350 | #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ | | 361 | #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ |
351 | #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ | | 362 | #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ |
352 | #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ | | 363 | #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ |
353 | #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ | | 364 | #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ |
354 | #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ | | 365 | #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ |
355 | #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ | | 366 | #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ |
356 | #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ | | 367 | #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ |
357 | #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ | | 368 | #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ |
358 | #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ | | 369 | #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ |
359 | | | 370 | |
360 | #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE | | 371 | #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE |
361 | | | 372 | |
362 | /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ | | 373 | /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ |
363 | #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ | | 374 | #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ |
364 | #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ | | 375 | #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ |
365 | #define CPACR_CPn(n) (3 << (2*n)) | | 376 | #define CPACR_CPn(n) (3 << (2*n)) |
366 | #define CPACR_NOACCESS 0 /* reset value */ | | 377 | #define CPACR_NOACCESS 0 /* reset value */ |
367 | #define CPACR_PRIVED 1 /* Privileged mode access */ | | 378 | #define CPACR_PRIVED 1 /* Privileged mode access */ |
368 | #define CPACR_RESERVED 2 | | 379 | #define CPACR_RESERVED 2 |
369 | #define CPACR_ALL 3 /* Privileged and User mode access */ | | 380 | #define CPACR_ALL 3 /* Privileged and User mode access */ |
370 | | | 381 | |
371 | /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 382 | /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
372 | #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ | | 383 | #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ |
373 | #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ | | 384 | #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ |
374 | #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ | | 385 | #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ |
375 | #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ | | 386 | #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ |
376 | #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ | | 387 | #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ |
377 | #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ | | 388 | #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ |
378 | #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ | | 389 | #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ |
379 | #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ | | 390 | #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ |
380 | | | 391 | |
381 | /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 392 | /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
382 | #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ | | 393 | #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ |
383 | /* This is an undocumented flag | | 394 | /* This is an undocumented flag |
384 | * used to work around a cache bug | | 395 | * used to work around a cache bug |
385 | * in r0 steppings. See errata | | 396 | * in r0 steppings. See errata |
386 | * 364296. | | 397 | * 364296. |
387 | */ | | 398 | */ |
388 | /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 399 | /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
389 | #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ | | 400 | #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ |
390 | #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ | | 401 | #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ |
391 | #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ | | 402 | #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ |
392 | #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ | | 403 | #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ |
393 | | | 404 | |
394 | /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 405 | /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
395 | #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */ | | 406 | #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */ |
396 | #define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */ | | 407 | #define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */ |
397 | #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */ | | 408 | #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */ |
398 | #define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */ | | 409 | #define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */ |
399 | #define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */ | | 410 | #define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */ |
400 | #define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */ | | 411 | #define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */ |
401 | #define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */ | | 412 | #define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */ |
402 | #define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */ | | 413 | #define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */ |
403 | | | 414 | |
404 | /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 415 | /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
405 | #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ | | 416 | #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ |
406 | #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ | | 417 | #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ |
407 | #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ | | 418 | #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ |
408 | #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ | | 419 | #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ |
409 | #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ | | 420 | #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ |
410 | #define XSCALE_AUXCTL_MD_MASK 0x00000030 | | 421 | #define XSCALE_AUXCTL_MD_MASK 0x00000030 |
411 | | | 422 | |
412 | /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ | | 423 | /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ |
413 | #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ | | 424 | #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ |
414 | #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ | | 425 | #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ |
415 | #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ | | 426 | #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ |
416 | #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ | | 427 | #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ |
417 | #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ | | 428 | #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ |
418 | #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ | | 429 | #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ |
419 | | | 430 | |
420 | /* Marvell PJ4B Auxillary Control Register */ | | 431 | /* Marvell PJ4B Auxillary Control Register */ |
421 | #define PJ4B_AUXCTL_SMPNAMP 0x00000040 /* SMP/AMP */ | | 432 | #define PJ4B_AUXCTL_SMPNAMP 0x00000040 /* SMP/AMP */ |
422 | | | 433 | |
423 | /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ | | 434 | /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ |
424 | #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ | | 435 | #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ |
425 | #define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */ | | 436 | #define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */ |
426 | #define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */ | | 437 | #define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */ |
427 | #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ | | 438 | #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ |
428 | #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ | | 439 | #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ |
429 | #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ | | 440 | #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ |
430 | #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ | | 441 | #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ |
431 | #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ | | 442 | #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ |
432 | | | 443 | |
433 | /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ | | 444 | /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ |
434 | #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ | | 445 | #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ |
435 | #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ | | 446 | #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ |
436 | #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ | | 447 | #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ |
437 | #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ | | 448 | #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ |
438 | #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ | | 449 | #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ |
439 | #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ | | 450 | #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ |
440 | #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ | | 451 | #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ |
441 | #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ | | 452 | #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ |
442 | #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ | | 453 | #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ |
443 | #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ | | 454 | #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ |
444 | | | 455 | |
445 | /* Cache type register definitions 0 */ | | 456 | /* Cache type register definitions 0 */ |
446 | #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ | | 457 | #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ |
447 | #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ | | 458 | #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ |
448 | #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ | | 459 | #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ |
449 | #define CPU_CT_S (1U << 24) /* split cache */ | | 460 | #define CPU_CT_S (1U << 24) /* split cache */ |
450 | #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ | | 461 | #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ |
451 | | | 462 | |
452 | #define CPU_CT_CTYPE_WT 0 /* write-through */ | | 463 | #define CPU_CT_CTYPE_WT 0 /* write-through */ |
453 | #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ | | 464 | #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ |
454 | #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ | | 465 | #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ |
455 | #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ | | 466 | #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ |
456 | #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ | | 467 | #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ |
457 | #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ | | 468 | #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ |
458 | | | 469 | |
459 | #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ | | 470 | #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ |
460 | #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ | | 471 | #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ |
461 | #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ | | 472 | #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ |
462 | #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ | | 473 | #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ |
463 | #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ | | 474 | #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ |
464 | | | 475 | |
465 | /* format 4 definitions */ | | 476 | /* format 4 definitions */ |
466 | #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ | | 477 | #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ |
467 | #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ | | 478 | #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ |
468 | #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ | | 479 | #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ |
469 | #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ | | 480 | #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ |
470 | #define CPU_CT4_L1_VIPT 2 /* VIPT */ | | 481 | #define CPU_CT4_L1_VIPT 2 /* VIPT */ |
471 | #define CPU_CT4_L1_PIPT 3 /* PIPT */ | | 482 | #define CPU_CT4_L1_PIPT 3 /* PIPT */ |
472 | #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ | | 483 | #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ |
473 | #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ | | 484 | #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ |
474 | | | 485 | |
475 | /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ | | 486 | /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ |
476 | #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ | | 487 | #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ |
477 | #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ | | 488 | #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ |
478 | #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ | | 489 | #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ |
479 | #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ | | 490 | #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ |
480 | #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) | | 491 | #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) |
481 | #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) | | 492 | #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) |
482 | #define CPU_CSID_LEN(x) ((x) & 0x07) | | 493 | #define CPU_CSID_LEN(x) ((x) & 0x07) |
483 | | | 494 | |
484 | /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ | | 495 | /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ |
485 | #define CPU_CSSR_L2 0x00000002 | | 496 | #define CPU_CSSR_L2 0x00000002 |
486 | #define CPU_CSSR_L1 0x00000000 | | 497 | #define CPU_CSSR_L1 0x00000000 |
487 | #define CPU_CSSR_InD 0x00000001 | | 498 | #define CPU_CSSR_InD 0x00000001 |
488 | | | 499 | |
489 | /* ARMv7A CP15 Global Timer definitions */ | | 500 | /* ARMv7A CP15 Global Timer definitions */ |
490 | #define CNTKCTL_PL0PTEN 0x00000200 /* PL0 Physical Timer Enable */ | | 501 | #define CNTKCTL_PL0PTEN 0x00000200 /* PL0 Physical Timer Enable */ |
491 | #define CNTKCTL_PL0VTEN 0x00000100 /* PL0 Virtual Timer Enable */ | | 502 | #define CNTKCTL_PL0VTEN 0x00000100 /* PL0 Virtual Timer Enable */ |
492 | #define CNTKCTL_EVNTI 0x000000f0 /* CNTVCT Event Bit Select */ | | 503 | #define CNTKCTL_EVNTI 0x000000f0 /* CNTVCT Event Bit Select */ |
493 | #define CNTKCTL_EVNTDIR 0x00000008 /* CNTVCT Event Dir (1->0) */ | | 504 | #define CNTKCTL_EVNTDIR 0x00000008 /* CNTVCT Event Dir (1->0) */ |
494 | #define CNTKCTL_EVNTEN 0x00000004 /* CNTVCT Event Enable */ | | 505 | #define CNTKCTL_EVNTEN 0x00000004 /* CNTVCT Event Enable */ |
495 | #define CNTKCTL_PL0PCTEN 0x00000200 /* PL0 Physical Counter Enable */ | | 506 | #define CNTKCTL_PL0PCTEN 0x00000200 /* PL0 Physical Counter Enable */ |
496 | #define CNTKCTL_PL0VCTEN 0x00000100 /* PL0 Virtual Counter Enable */ | | 507 | #define CNTKCTL_PL0VCTEN 0x00000100 /* PL0 Virtual Counter Enable */ |
497 | | | 508 | |
498 | #define CNT_CTL_ISTATUS 0x00000004 /* Timer is asserted */ | | 509 | #define CNT_CTL_ISTATUS 0x00000004 /* Timer is asserted */ |
499 | #define CNT_CTL_IMASK 0x00000002 /* Timer output is masked */ | | 510 | #define CNT_CTL_IMASK 0x00000002 /* Timer output is masked */ |
500 | #define CNT_CTL_ENABLE 0x00000001 /* Timer is enabled */ | | 511 | #define CNT_CTL_ENABLE 0x00000001 /* Timer is enabled */ |
501 | | | 512 | |
502 | /* Fault status register definitions */ | | 513 | /* Fault status register definitions */ |
503 | | | 514 | |
504 | #define FAULT_TYPE_MASK 0x0f | | 515 | #define FAULT_TYPE_MASK 0x0f |
505 | #define FAULT_USER 0x10 | | 516 | #define FAULT_USER 0x10 |
506 | | | 517 | |
507 | #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ | | 518 | #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ |
508 | #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ | | 519 | #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ |
509 | #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ | | 520 | #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ |
510 | #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ | | 521 | #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ |
511 | #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ | | 522 | #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ |
512 | #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ | | 523 | #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ |
513 | #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ | | 524 | #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ |
514 | #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ | | 525 | #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ |
515 | #define FAULT_ALIGN_0 0x01 /* Alignment */ | | 526 | #define FAULT_ALIGN_0 0x01 /* Alignment */ |
516 | #define FAULT_ALIGN_1 0x03 /* Alignment */ | | 527 | #define FAULT_ALIGN_1 0x03 /* Alignment */ |
517 | #define FAULT_TRANS_S 0x05 /* Translation -- Section */ | | 528 | #define FAULT_TRANS_S 0x05 /* Translation -- Section */ |
518 | #define FAULT_TRANS_P 0x07 /* Translation -- Page */ | | 529 | #define FAULT_TRANS_P 0x07 /* Translation -- Page */ |
519 | #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ | | 530 | #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ |
520 | #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ | | 531 | #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ |
521 | #define FAULT_PERM_S 0x0d /* Permission -- Section */ | | 532 | #define FAULT_PERM_S 0x0d /* Permission -- Section */ |
522 | #define FAULT_PERM_P 0x0f /* Permission -- Page */ | | 533 | #define FAULT_PERM_P 0x0f /* Permission -- Page */ |
523 | | | 534 | |
524 | #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ | | 535 | #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ |
525 | | | 536 | |
526 | /* | | 537 | /* |
527 | * Address of the vector page, low and high versions. | | 538 | * Address of the vector page, low and high versions. |
528 | */ | | 539 | */ |
529 | #define ARM_VECTORS_LOW 0x00000000U | | 540 | #define ARM_VECTORS_LOW 0x00000000U |
530 | #define ARM_VECTORS_HIGH 0xffff0000U | | 541 | #define ARM_VECTORS_HIGH 0xffff0000U |
531 | | | 542 | |
532 | /* | | 543 | /* |
533 | * ARM Instructions | | 544 | * ARM Instructions |
534 | * | | 545 | * |
535 | * 3 3 2 2 2 | | 546 | * 3 3 2 2 2 |
536 | * 1 0 9 8 7 0 | | 547 | * 1 0 9 8 7 0 |
537 | * +-------+-------------------------------------------------------+ | | 548 | * +-------+-------------------------------------------------------+ |
538 | * | cond | instruction dependent | | | 549 | * | cond | instruction dependent | |
539 | * |c c c c| | | | 550 | * |c c c c| | |
540 | * +-------+-------------------------------------------------------+ | | 551 | * +-------+-------------------------------------------------------+ |
541 | */ | | 552 | */ |
542 | | | 553 | |
543 | #define INSN_SIZE 4 /* Always 4 bytes */ | | 554 | #define INSN_SIZE 4 /* Always 4 bytes */ |
544 | #define INSN_COND_MASK 0xf0000000 /* Condition mask */ | | 555 | #define INSN_COND_MASK 0xf0000000 /* Condition mask */ |
545 | #define INSN_COND_AL 0xe0000000 /* Always condition */ | | 556 | #define INSN_COND_AL 0xe0000000 /* Always condition */ |
546 | | | 557 | |
547 | #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ | | 558 | #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ |
548 | | | 559 | |
549 | /* | | 560 | /* |
550 | * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) | | 561 | * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) |
551 | */ | | 562 | */ |
552 | #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ | | 563 | #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ |
553 | #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ | | 564 | #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ |
554 | #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ | | 565 | #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ |
555 | #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ | | 566 | #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ |
556 | #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ | | 567 | #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ |
557 | #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ | | 568 | #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ |
558 | #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ | | 569 | #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ |
559 | #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ | | 570 | #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ |
560 | #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ | | 571 | #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ |
561 | #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ | | 572 | #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ |
562 | #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ | | 573 | #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ |
563 | #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ | | 574 | #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ |
564 | #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ | | 575 | #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ |
565 | #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ | | 576 | #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ |
566 | #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ | | 577 | #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ |
567 | #define ARM11_PMCCTL_SBZ \ | | 578 | #define ARM11_PMCCTL_SBZ \ |
568 | (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) | | 579 | (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) |
569 | | | 580 | |
570 | #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ | | 581 | #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ |
571 | #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ | | 582 | #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ |
572 | #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ | | 583 | #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ |
573 | #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ | | 584 | #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ |
574 | #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ | | 585 | #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ |
575 | #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ | | 586 | #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ |
576 | #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ | | 587 | #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ |
577 | #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ | | 588 | #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ |
578 | #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ | | 589 | #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ |
579 | #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ | | 590 | #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ |
580 | #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ | | 591 | #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ |
581 | #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ | | 592 | #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ |
582 | #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ | | 593 | #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ |
583 | #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ | | 594 | #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ |
584 | #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ | | 595 | #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ |
585 | #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ | | 596 | #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ |
586 | #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ | | 597 | #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ |
587 | #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ | | 598 | #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ |
588 | #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ | | 599 | #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ |
589 | #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ | | 600 | #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ |
590 | #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ | | 601 | #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ |
591 | #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ | | 602 | #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ |
592 | #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ | | 603 | #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ |
593 | #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ | | 604 | #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ |
594 | | | 605 | |
595 | /* Defines for ARM CORTEX performance counters */ | | 606 | /* Defines for ARM CORTEX performance counters */ |
596 | #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ | | 607 | #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ |
597 | #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ | | 608 | #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ |
598 | #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ | | 609 | #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ |
599 | | | 610 | |
600 | /* Translate Table Base Control Register */ | | 611 | /* Translate Table Base Control Register */ |
601 | #define TTBCR_S_EAE __BIT(31) // Extended Address Extension | | 612 | #define TTBCR_S_EAE __BIT(31) // Extended Address Extension |
602 | #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 | | 613 | #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 |
603 | #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 | | 614 | #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 |
604 | #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 | | 615 | #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 |
605 | | | 616 | |
606 | #define TTBCR_L_EAE __BIT(31) // Extended Address Extension | | 617 | #define TTBCR_L_EAE __BIT(31) // Extended Address Extension |
607 | #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability | | 618 | #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability |
608 | #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability | | 619 | #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability |
609 | #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability | | 620 | #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability |
610 | #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 | | 621 | #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 |
611 | #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 | | 622 | #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 |
612 | #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset | | 623 | #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset |
613 | #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability | | 624 | #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability |
614 | #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability | | 625 | #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability |
615 | #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability | | 626 | #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability |
616 | #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 | | 627 | #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 |
617 | #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset | | 628 | #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset |
618 | | | 629 | |
619 | /* Defines for ARM Generic Timer */ | | 630 | /* Defines for ARM Generic Timer */ |
620 | #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled | | 631 | #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled |
621 | #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt | | 632 | #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt |
622 | #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending | | 633 | #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending |
623 | | | 634 | |
624 | #define ARM_CNTKCTL_PL0PTEN __BIT(9) | | 635 | #define ARM_CNTKCTL_PL0PTEN __BIT(9) |
625 | #define ARM_CNTKCTL_PL0VTEN __BIT(8) | | 636 | #define ARM_CNTKCTL_PL0VTEN __BIT(8) |
626 | #define ARM_CNTKCTL_EVNTI __BITS(7,4) | | 637 | #define ARM_CNTKCTL_EVNTI __BITS(7,4) |
627 | #define ARM_CNTKCTL_EVNTDIR __BIT(3) | | 638 | #define ARM_CNTKCTL_EVNTDIR __BIT(3) |
628 | #define ARM_CNTKCTL_EVNTEN __BIT(2) | | 639 | #define ARM_CNTKCTL_EVNTEN __BIT(2) |
629 | #define ARM_CNTKCTL_PL0PCTEN __BIT(1) | | 640 | #define ARM_CNTKCTL_PL0PCTEN __BIT(1) |
630 | #define ARM_CNTKCTL_PL0VCTEN __BIT(0) | | 641 | #define ARM_CNTKCTL_PL0VCTEN __BIT(0) |
631 | | | 642 | |
632 | #define ARM_CNTHCTL_EVNTI __BITS(7,4) | | 643 | #define ARM_CNTHCTL_EVNTI __BITS(7,4) |
633 | #define ARM_CNTHCTL_EVNTDIR __BIT(3) | | 644 | #define ARM_CNTHCTL_EVNTDIR __BIT(3) |
634 | #define ARM_CNTHCTL_EVNTEN __BIT(2) | | 645 | #define ARM_CNTHCTL_EVNTEN __BIT(2) |
635 | #define ARM_CNTHCTL_PL1PCTEN __BIT(1) | | 646 | #define ARM_CNTHCTL_PL1PCTEN __BIT(1) |
636 | #define ARM_CNTHCTL_PL1VCTEN __BIT(0) | | 647 | #define ARM_CNTHCTL_PL1VCTEN __BIT(0) |
637 | | | 648 | |
638 | #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) | | 649 | #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) |
639 | #define ARMREG_READ_INLINE(name, __insnstring) \ | | 650 | #define ARMREG_READ_INLINE(name, __insnstring) \ |
640 | static inline uint32_t armreg_##name##_read(void) \ | | 651 | static inline uint32_t armreg_##name##_read(void) \ |
641 | { \ | | 652 | { \ |
642 | uint32_t __rv; \ | | 653 | uint32_t __rv; \ |
643 | __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ | | 654 | __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ |
644 | return __rv; \ | | 655 | return __rv; \ |
645 | } | | 656 | } |
646 | | | 657 | |
647 | #define ARMREG_WRITE_INLINE(name, __insnstring) \ | | 658 | #define ARMREG_WRITE_INLINE(name, __insnstring) \ |
648 | static inline void armreg_##name##_write(uint32_t __val) \ | | 659 | static inline void armreg_##name##_write(uint32_t __val) \ |
649 | { \ | | 660 | { \ |
650 | __asm __volatile("mcr " __insnstring :: "r"(__val)); \ | | 661 | __asm __volatile("mcr " __insnstring :: "r"(__val)); \ |
651 | } | | 662 | } |
652 | | | 663 | |
653 | #define ARMREG_READ_INLINE2(name, __insnstring) \ | | 664 | #define ARMREG_READ_INLINE2(name, __insnstring) \ |
654 | static inline uint32_t armreg_##name##_read(void) \ | | 665 | static inline uint32_t armreg_##name##_read(void) \ |
655 | { \ | | 666 | { \ |
656 | uint32_t __rv; \ | | 667 | uint32_t __rv; \ |
657 | __asm __volatile(__insnstring : "=r"(__rv)); \ | | 668 | __asm __volatile(__insnstring : "=r"(__rv)); \ |
658 | return __rv; \ | | 669 | return __rv; \ |
659 | } | | 670 | } |
660 | | | 671 | |
661 | #define ARMREG_WRITE_INLINE2(name, __insnstring) \ | | 672 | #define ARMREG_WRITE_INLINE2(name, __insnstring) \ |
662 | static inline void armreg_##name##_write(uint32_t __val) \ | | 673 | static inline void armreg_##name##_write(uint32_t __val) \ |
663 | { \ | | 674 | { \ |
664 | __asm __volatile(__insnstring :: "r"(__val)); \ | | 675 | __asm __volatile(__insnstring :: "r"(__val)); \ |
665 | } | | 676 | } |
666 | | | 677 | |
667 | #define ARMREG_READ64_INLINE(name, __insnstring) \ | | 678 | #define ARMREG_READ64_INLINE(name, __insnstring) \ |
668 | static inline uint64_t armreg_##name##_read(void) \ | | 679 | static inline uint64_t armreg_##name##_read(void) \ |
669 | { \ | | 680 | { \ |
670 | uint64_t __rv; \ | | 681 | uint64_t __rv; \ |
671 | __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ | | 682 | __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ |
672 | return __rv; \ | | 683 | return __rv; \ |
673 | } | | 684 | } |
674 | | | 685 | |
675 | #define ARMREG_WRITE64_INLINE(name, __insnstring) \ | | 686 | #define ARMREG_WRITE64_INLINE(name, __insnstring) \ |
676 | static inline void armreg_##name##_write(uint64_t __val) \ | | 687 | static inline void armreg_##name##_write(uint64_t __val) \ |
677 | { \ | | 688 | { \ |
678 | __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ | | 689 | __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ |
679 | } | | 690 | } |
680 | | | 691 | |
681 | /* cp10 registers */ | | 692 | /* cp10 registers */ |
682 | ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */ | | 693 | ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */ |
683 | ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */ | | 694 | ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */ |
684 | ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */ | | 695 | ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */ |
685 | ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */ | | 696 | ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */ |
686 | ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */ | | 697 | ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */ |
687 | ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */ | | 698 | ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */ |
688 | ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */ | | 699 | ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */ |
689 | ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */ | | 700 | ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */ |
690 | ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */ | | 701 | ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */ |
691 | ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */ | | 702 | ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */ |
692 | ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */ | | 703 | ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */ |
693 | | | 704 | |
694 | /* cp15 c0 registers */ | | 705 | /* cp15 c0 registers */ |
695 | ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ | | 706 | ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ |
696 | ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ | | 707 | ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ |
697 | ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ | | 708 | ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ |
698 | ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ | | 709 | ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ |
699 | ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ | | 710 | ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ |
700 | ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ | | 711 | ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ |
701 | ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ | | 712 | ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ |
702 | ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ | | 713 | ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ |
703 | ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ | | 714 | ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ |
704 | ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ | | 715 | ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ |
705 | ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ | | 716 | ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ |
706 | ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ | | 717 | ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ |
707 | ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ | | 718 | ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ |
708 | ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ | | 719 | ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ |
709 | ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ | | 720 | ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ |
710 | ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ | | 721 | ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ |
711 | ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ | | 722 | ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ |
712 | ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ | | 723 | ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ |
713 | ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ | | 724 | ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ |
714 | /* cp15 c1 registers */ | | 725 | /* cp15 c1 registers */ |
715 | ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ | | 726 | ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ |
716 | ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ | | 727 | ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ |
717 | ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ | | 728 | ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ |
718 | ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ | | 729 | ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ |
719 | ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ | | 730 | ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ |
720 | ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ | | 731 | ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ |
721 | /* cp15 c2 registers */ | | 732 | /* cp15 c2 registers */ |
722 | ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ | | 733 | ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ |
723 | ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ | | 734 | ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ |
724 | ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ | | 735 | ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ |
725 | ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ | | 736 | ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ |
726 | ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ | | 737 | ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ |
727 | ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ | | 738 | ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ |
728 | /* cp15 c5 registers */ | | 739 | /* cp15 c5 registers */ |
729 | ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ | | 740 | ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ |
730 | ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ | | 741 | ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ |
731 | /* cp15 c6 registers */ | | 742 | /* cp15 c6 registers */ |
732 | ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ | | 743 | ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ |
733 | ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ | | 744 | ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ |
734 | /* cp15 c7 registers */ | | 745 | /* cp15 c7 registers */ |
735 | ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ | | 746 | ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ |
736 | ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */ | | 747 | ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */ |
737 | ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ | | 748 | ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ |
738 | ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ | | 749 | ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ |
739 | ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ | | 750 | ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ |
740 | ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ | | 751 | ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ |
741 | ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */ | | 752 | ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */ |
742 | ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ | | 753 | ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ |
743 | ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ | | 754 | ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ |
744 | ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ | | 755 | ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ |
745 | ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ | | 756 | ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ |
746 | ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ | | 757 | ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ |
747 | ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ | | 758 | ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ |
748 | ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ | | 759 | ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ |
749 | ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */ | | 760 | ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */ |
750 | ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ | | 761 | ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ |
751 | ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ | | 762 | ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ |
752 | /* cp15 c8 registers */ | | 763 | /* cp15 c8 registers */ |
753 | ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ | | 764 | ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ |
754 | ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ | | 765 | ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ |
755 | ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ | | 766 | ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ |
756 | ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ | | 767 | ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ |
757 | ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ | | 768 | ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ |
758 | ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ | | 769 | ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ |
759 | ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ | | 770 | ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ |
760 | ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ | | 771 | ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ |
761 | ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ | | 772 | ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ |
762 | ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ | | 773 | ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ |
763 | ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ | | 774 | ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ |
764 | ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ | | 775 | ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ |
765 | ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ | | 776 | ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ |
766 | ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ | | 777 | ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ |
767 | /* cp15 c9 registers */ | | 778 | /* cp15 c9 registers */ |
768 | ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ | | 779 | ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ |
769 | ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ | | 780 | ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ |
770 | ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ | | 781 | ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ |
771 | ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ | | 782 | ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ |
772 | ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ | | 783 | ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ |
773 | ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ | | 784 | ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ |
774 | ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ | | 785 | ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ |
775 | ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ | | 786 | ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ |
776 | ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ | | 787 | ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ |
777 | ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ | | 788 | ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ |
778 | ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ | | 789 | ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ |
779 | ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ | | 790 | ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ |
780 | /* cp15 c13 registers */ | | 791 | /* cp15 c13 registers */ |
781 | ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ | | 792 | ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ |
782 | ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ | | 793 | ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ |
783 | ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ | | 794 | ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ |
784 | ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ | | 795 | ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ |
785 | /* cp14 c12 registers */ | | 796 | /* cp14 c12 registers */ |
786 | ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ | | 797 | ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ |
787 | ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ | | 798 | ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ |
788 | /* cp15 c14 registers */ | | 799 | /* cp15 c14 registers */ |
789 | /* cp15 Global Timer Registers */ | | 800 | /* cp15 Global Timer Registers */ |
790 | ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ | | 801 | ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ |
791 | ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ | | 802 | ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ |
792 | ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ | | 803 | ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ |
793 | ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ | | 804 | ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ |
794 | ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ | | 805 | ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ |
795 | ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ | | 806 | ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ |
796 | ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ | | 807 | ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ |
797 | ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ | | 808 | ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ |
798 | ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ | | 809 | ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ |
799 | ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ | | 810 | ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ |
800 | ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ | | 811 | ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ |
801 | ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ | | 812 | ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ |
802 | ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ | | 813 | ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ |
803 | ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ | | 814 | ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ |
804 | ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ | | 815 | ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ |
805 | ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ | | 816 | ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ |
806 | ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ | | 817 | ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ |
807 | ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ | | 818 | ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ |
808 | ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ | | 819 | ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ |
809 | ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ | | 820 | ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ |
810 | /* cp15 c15 registers */ | | 821 | /* cp15 c15 registers */ |
811 | ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ | | 822 | ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ |
812 | ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ | | 823 | ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ |
813 | ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ | | 824 | ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ |
814 | ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ | | 825 | ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ |
815 | ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ | | 826 | ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ |
816 | | | 827 | |
817 | #endif /* !__ASSEMBLER__ */ | | 828 | #endif /* !__ASSEMBLER__ */ |
818 | | | 829 | |
819 | | | 830 | |
820 | #define MPIDR_31 0x80000000 | | 831 | #define MPIDR_31 0x80000000 |
821 | #define MPIDR_U 0x40000000 // 1 = Uniprocessor | | 832 | #define MPIDR_U 0x40000000 // 1 = Uniprocessor |
822 | #define MPIDR_MT 0x01000000 // AFF0 for SMT | | 833 | #define MPIDR_MT 0x01000000 // AFF0 for SMT |
823 | #define MPIDR_AFF2 0x00ff0000 | | 834 | #define MPIDR_AFF2 0x00ff0000 |
824 | #define MPIDR_AFF1 0x0000ff00 | | 835 | #define MPIDR_AFF1 0x0000ff00 |
825 | #define MPIDR_AFF0 0x000000ff | | 836 | #define MPIDR_AFF0 0x000000ff |
826 | | | 837 | |
827 | #endif /* _ARM_ARMREG_H */ | | 838 | #endif /* _ARM_ARMREG_H */ |