Sun Jan 12 12:35:39 2014 UTC ()

Pull up following revision(s) (requested by martin in ticket #1006):
	external/gpl3/gcc/dist/gcc/config/sparc/constraints.md: revision 1.2
	external/gpl3/gcc/dist/gcc/config/sparc/predicates.md: revision 1.2
	external/gpl3/gcc/dist/gcc/config/sparc/sync.md: revision 1.2
Port from newer gcc:
Add a "mem_noofs_operand" predicate and corresponding "w" constraint.
Use those instead of "memory_reg_operand"/"m" for some atomic instrinsic
patterns: casx (and friends) do not accept an offset from the pointer
register (they are synthetic instructions mapping to e.g. casxa [..]
ASI_P, ... and the opcode space encoding offsets in other instructions
is needed to encode the ASI here).
This fixes the build of gtk+-3.10.6 from pkgsrc on sparc64.


(bouyer)

diff -r1.1.1.1 -r1.1.1.1.10.1 src/external/gpl3/gcc/dist/gcc/config/sparc/constraints.md
diff -r1.1.1.1 -r1.1.1.1.10.1 src/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md
diff -r1.1.1.1 -r1.1.1.1.10.1 src/external/gpl3/gcc/dist/gcc/config/sparc/sync.md

--- src/external/gpl3/gcc/dist/gcc/config/sparc/constraints.md 2011/06/21 01:22:24	1.1.1.1
+++ src/external/gpl3/gcc/dist/gcc/config/sparc/constraints.md 2014/01/12 12:35:39	1.1.1.1.10.1

 @@ -131,18 +131,22 @@
 (define_constraint "U"
  "Pseudo-register or hard even-numbered integer register"
  (and (match_test "TARGET_ARCH32")
       (match_code "reg")
       (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
 	   (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
       (match_test "register_ok_for_ldd (op)")))
 ;; Equivalent to 'T' but available in 64-bit mode
 (define_constraint "W"
  "Memory reference for 'e' constraint floating-point register"
  (and (match_code "mem,reg")
       (match_test "memory_ok_for_ldd (op)")))
 (define_memory_constraint "w"
   "A memory with only a base register"
   (match_operand 0 "mem_noofs_operand"))
 (define_constraint "Y"
  "The vector zero constant"
  (and (match_code "const_vector")
       (match_test "const_zero_operand (op, mode)")))

--- src/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md 2011/06/21 01:22:24	1.1.1.1
+++ src/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md 2014/01/12 12:35:39	1.1.1.1.10.1

 @@ -417,26 +417,29 @@
 ;; Return true if OP is an address suitable for a call insn.
 ;; Call insn on SPARC can take a PC-relative constant address
 ;; or any regular memory address.
 (define_predicate "call_address_operand"
   (ior (match_operand 0 "symbolic_operand")
        (match_test "memory_address_p (Pmode, op)")))
 ;; Return true if OP is an operand suitable for a call insn.
 (define_predicate "call_operand"
   (and (match_code "mem")
        (match_test "call_address_operand (XEXP (op, 0), mode)")))
 (define_predicate "mem_noofs_operand"
   (and (match_code "mem")
        (match_code "reg" "0")))
 ;; Predicates for operators.
 ;; Return true if OP is a comparison operator.  This allows the use of
 ;; MATCH_OPERATOR to recognize all the branch insns.
 (define_predicate "noov_compare_operator"
   (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
+{
   enum rtx_code code = GET_CODE (op);
   if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
       || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
     /* These are the only branches which work with CC_NOOVmode.  */
     return (code == EQ || code == NE || code == GE || code == LT);

--- src/external/gpl3/gcc/dist/gcc/config/sparc/sync.md 2011/06/21 01:22:25	1.1.1.1
+++ src/external/gpl3/gcc/dist/gcc/config/sparc/sync.md 2014/01/12 12:35:39	1.1.1.1.10.1

 @@ -71,39 +71,39 @@
 	     UNSPECV_CAS))])]
   "TARGET_V9"
+{
   if (! REG_P (XEXP (operands[1], 0)))
+    {
       rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
       operands[1] = replace_equiv_address (operands[1], addr);
+    }
   emit_insn (gen_memory_barrier ());
 })
 (define_insn "*sync_compare_and_swap<mode>"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
-	(match_operand:I48MODE 1 "memory_reg_operand" "+m"))
+	(match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
    (set (match_dup 1)
 	(unspec_volatile:I48MODE
 	  [(match_operand:I48MODE 2 "register_operand" "r")
 	   (match_operand:I48MODE 3 "register_operand" "0")]
 	  UNSPECV_CAS))]
   "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
   "cas<modesuffix>\t%1, %2, %0"
   [(set_attr "type" "multi")])
 (define_insn "*sync_compare_and_swapdi_v8plus"
   [(set (match_operand:DI 0 "register_operand" "=h")
-	(match_operand:DI 1 "memory_reg_operand" "+m"))
+	(match_operand:DI 1 "mem_noofs_operand" "+w"))
    (set (match_dup 1)
 	(unspec_volatile:DI
 	  [(match_operand:DI 2 "register_operand" "h")
 	   (match_operand:DI 3 "register_operand" "0")]
 	  UNSPECV_CAS))]
   "TARGET_V8PLUS"
+{
   if (sparc_check_64 (operands[3], insn) <= 0)
     output_asm_insn ("srl\t%L3, 0, %L3", operands);
   output_asm_insn ("sllx\t%H3, 32, %H3", operands);
   output_asm_insn ("or\t%L3, %H3, %L3", operands);
   if (sparc_check_64 (operands[2], insn) <= 0)
     output_asm_insn ("srl\t%L2, 0, %L2", operands);