 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc_asm_arm11.S,v 1.10 2013/08/18 06:28:18 matt Exp $	*/
+/*	$NetBSD: cpufunc_asm_arm11.S,v 1.11 2014/02/20 17:27:46 matt Exp $	*/
 /*
  * Copyright (c) 2002, 2005 ARM Limited
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -47,92 +47,113 @@
 ENTRY(arm11_setttb)
 #ifdef PMAP_CACHE_VIVT
 #error arm11 does not have a VIVT cache.
 #endif
 	mcr	p15, 0, r0, c2, c0, 0	/* load new TTB */
 	cmp	r1, #0
 	mcrne	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLBs */
 	mcrne	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_setttb)
 /*
  * TLB functions
  */
 ENTRY(arm11_tlb_flushID_SE)
 	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
 	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushID_SE)
 ENTRY(arm11_tlb_flushI_SE)
 	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushI_SE)
 /*
  * Context switch.
+ *
  * These are the CPU-specific parts of the context switcher cpu_switchto()
  * These functions actually perform the TTB reload.
  */
 ENTRY(arm11_context_switch)
 	/*
 	 * We can assume that the caches will only contain kernel addresses
 	 * at this point.  So no need to flush them again.
 	 */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
 	mcr	p15, 0, r0, c2, c0, 0	/* set the new TTB */
 	mcr	p15, 0, r0, c8, c7, 0	/* and flush the I+D tlbs */
 	/* Paranoia -- make sure the pipeline is empty. */
 	nop
 	nop
 	nop
 	RET
 END(arm11_context_switch)
 /*
  * TLB functions
  */
 ENTRY(arm11_tlb_flushID)
 	mcr	p15, 0, r0, c8, c7, 0	/* flush I+D tlb */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushID)
 ENTRY(arm11_tlb_flushI)
 	mov	r0, #0
 	mcr	p15, 0, r0, c8, c5, 0	/* flush I tlb */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushI)
 ENTRY(arm11_tlb_flushI_SE)
 #ifdef ARM_MMU_EXTENDED
 	orr	r0, r0, r1		/* insert ASID into MVA */
 #endif
 	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushI_SE)
 ENTRY(arm11_tlb_flushD)
 	mov	r0, #0
 	mcr	p15, 0, r0, c8, c6, 0	/* flush D tlb */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushD)
 ENTRY(arm11_tlb_flushD_SE)
 #ifdef ARM_MMU_EXTENDED
 	orr	r0, r0, r1		/* insert ASID into MVA */
 #endif
 	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushD_SE)
 ENTRY(arm11_tlb_flushID)
 	mov	r0, #0
 	mcr	p15, 0, r0, c8, c7, 0	/* flush I+D tlb */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushID)
 ENTRY(arm11_tlb_flushID_SE)
 #ifdef ARM_MMU_EXTENDED
 	orr	r0, r0, r1		/* insert ASID into MVA */
 #endif
 	mcr	p15, 0, r0, c8, c7, 1	/* flush I+D tlb single entry */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushID_SE)
 #ifdef ARM_MMU_EXTENDED
 ENTRY(arm11_tlb_flushID_ASID)
 	mcr	p15, 0, r0, c8, c7, 2	/* flush I+D tlb */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_tlb_flushID_ASID)
 #endif
 /*
  * Other functions
  */
 ENTRY(arm11_drain_writebuf)
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	RET
 END(arm11_drain_writebuf)
 ENTRY_NP(arm11_sleep)
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c0, 4	/* wait for interrupt */
 	RET
 END(arm11_sleep)