Thu Feb 20 17:38:11 2014 UTC ()
Add armv7 versions of tlb routines.


(matt)
diff -r1.13 -r1.14 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs diff -r1.13 -r1.14 src/sys/arch/arm/arm/cpufunc_asm_armv7.S (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S 2014/02/20 15:52:30 1.13
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S 2014/02/20 17:38:11 1.14
@@ -36,56 +36,91 @@ @@ -36,56 +36,91 @@
36ENTRY(armv7_cpu_sleep) 36ENTRY(armv7_cpu_sleep)
37 wfi @ wait for an interrupt 37 wfi @ wait for an interrupt
38 b irq_idle_entry @ assume we got an interrupt 38 b irq_idle_entry @ assume we got an interrupt
39END(armv7_cpu_sleep) 39END(armv7_cpu_sleep)
40 40
41ENTRY(armv7_wait) 41ENTRY(armv7_wait)
42 mrc p15, 0, r0, c2, c0, 0 @ arbitrary read of CP15 42 mrc p15, 0, r0, c2, c0, 0 @ arbitrary read of CP15
43 add r0, r0, #0 @ a stall 43 add r0, r0, #0 @ a stall
44 bx lr 44 bx lr
45END(armv7_wait) 45END(armv7_wait)
46 46
47ENTRY(armv7_context_switch) 47ENTRY(armv7_context_switch)
48 dsb @ data synchronization barrier 48 dsb @ data synchronization barrier
49 mrc p15, 0, r2, c0, c0, 5 @ get MPIDR 49 mrc p15, 0, ip, c0, c0, 5 @ get MPIDR
50 cmp r2, #0 50 cmp ip, #0
51 orrlt r0, r0, #0x5b @ MP, cachable (Normal WB) 51 orrlt r0, r0, #0x5b @ MP, cachable (Normal WB)
52 orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB 52 orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB
53 mcr p15, 0, r0, c2, c0, 0 @ set the new TTB 53 mcr p15, 0, r0, c2, c0, 0 @ set the new TTB
54#ifdef MULTIPROCESSOR 54#ifdef MULTIPROCESSOR
55 mcr p15, 0, r0, c8, c3, 0 @ flush the I+D 55 mcr p15, 0, r0, c8, c3, 0 @ flush the I+D
56#else 56#else
57 mcr p15, 0, r0, c8, c7, 0 @ flush the I+D 57 mcr p15, 0, r0, c8, c7, 0 @ flush the I+D
58#endif 58#endif
59 dsb 59 dsb
60 isb 60 isb
61 bx lr 61 bx lr
62END(armv7_context_switch) 62END(armv7_context_switch)
63 63
 64#ifdef ARM_MMU_EXTENDED
 65ENTRY(armv7_tlb_flushID_ASID)
 66#ifdef MULTIPROCESSOR
 67 mcr p15, 0, r0, c8, c3, 2 @ flush I+D tlb all ASID
 68#else
 69 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID
 70#endif
 71 dsb @ data synchronization barrier
 72 isb
 73 bx lr
 74END(armv7_tlb_flushID_ASID)
 75#endif
 76
 77STRONG_ALIAS(armv7_tlb_flushD_SE, armv7_tlb_flushID_SE)
 78STRONG_ALIAS(armv7_tlb_flushI_SE, armv7_tlb_flushID_SE)
64ENTRY(armv7_tlb_flushID_SE) 79ENTRY(armv7_tlb_flushID_SE)
 80#ifdef ARM_MMU_EXTENDED
 81 bfi r0, r1, #0, #8 @ insert ASID into MVA
 82#endif
65#ifdef MULTIPROCESSOR 83#ifdef MULTIPROCESSOR
66 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry 84 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
67#else 85#else
68 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry 86 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
69#endif 87#endif
70 dsb @ data synchronization barrier 88 dsb @ data synchronization barrier
71 isb 89 isb
72 bx lr 90 bx lr
73END(armv7_tlb_flushID_SE) 91END(armv7_tlb_flushID_SE)
74 92
 93ENTRY(armv7_tlb_flushD)
 94 mov r0, #0
 95 mcr p15, 0, r0, c8, c6, 0 @ flush entire D tlb
 96 dsb @ data synchronization barrier
 97 isb
 98 bx lr
 99END(armv7_tlb_flushD)
 100
 101STRONG_ALIAS(armv7_tlb_flushI, armv7_tlb_flushID)
 102ENTRY(armv7_tlb_flushID)
 103 mov r0, #0
 104 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb
 105 dsb @ data synchronization barrier
 106 isb
 107 bx lr
 108END(armv7_tlb_flushID)
 109
75 110
76ENTRY_NP(armv7_setttb) 111ENTRY_NP(armv7_setttb)
77 mrc p15, 0, r2, c0, c0, 5 @ get MPIDR 112 mrc p15, 0, ip, c0, c0, 5 @ get MPIDR
78 cmp r2, #0 113 cmp ip, #0
79 orrlt r0, r0, #0x5b @ MP, cachable (Normal WB) 114 orrlt r0, r0, #0x5b @ MP, cachable (Normal WB)
80 orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB 115 orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB
81 mcr p15, 0, r0, c2, c0, 0 @ load new TTB 116 mcr p15, 0, r0, c2, c0, 0 @ load new TTB
82 cmp r1, #0 117 cmp r1, #0
83#ifdef MULTIPROCESSOR 118#ifdef MULTIPROCESSOR
84 mcrne p15, 0, r0, c8, c3, 0 @ invalidate all I+D TLBs 119 mcrne p15, 0, r0, c8, c3, 0 @ invalidate all I+D TLBs
85#else 120#else
86 mcrne p15, 0, r0, c8, c7, 0 @ invalidate all I+D TLBs 121 mcrne p15, 0, r0, c8, c7, 0 @ invalidate all I+D TLBs
87#endif 122#endif
88 dsb @ data synchronization barrier 123 dsb @ data synchronization barrier
89 isb 124 isb
90 bx lr 125 bx lr
91END(armv7_setttb) 126END(armv7_setttb)