| @@ -1,38 +1,45 @@ | | | @@ -1,38 +1,45 @@ |
1 | # $NetBSD: Makefile.inc,v 1.15 2014/01/27 18:05:24 matt Exp $ | | 1 | # $NetBSD: Makefile.inc,v 1.16 2014/02/21 21:54:38 martin Exp $ |
2 | | | 2 | |
3 | ARMV6= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*} | | 3 | ARMV6= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*} |
4 | ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*} | | 4 | ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*} |
5 | ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*} | | 5 | ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*} |
6 | ARMV7= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*} | | 6 | ARMV7= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*} |
7 | ARMV7+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*} | | 7 | ARMV7+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*} |
8 | ARMV7+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*} | | 8 | ARMV7+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*} |
9 | .if empty(CFLAGS:M-march=*) && empty(CFLAGS:M-mcpu=*) \ | | 9 | .if empty(CFLAGS:M-march=*) && empty(CFLAGS:M-mcpu=*) \ |
10 | && empty(CPPFLAGS:M-march=*) && empty(CPPFLAGS:M-mcpu=*) \ | | 10 | && empty(CPPFLAGS:M-march=*) && empty(CPPFLAGS:M-mcpu=*) \ |
11 | && empty(CPUFLAGS:M-march=*) && empty(CPUFLAGS:M-mcpu=*) | | 11 | && empty(CPUFLAGS:M-march=*) && empty(CPUFLAGS:M-mcpu=*) |
12 | ARMV6+= ${MACHINE_ARCH:Mearmv6*} | | 12 | ARMV6+= ${MACHINE_ARCH:Mearmv6*} |
13 | ARMV7+= ${MACHINE_ARCH:Mearmv7*} | | 13 | ARMV7+= ${MACHINE_ARCH:Mearmv7*} |
14 | .endif | | 14 | .endif |
15 | | | 15 | |
16 | .if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c" || ${LIB} == "pthread" \ | | 16 | .if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c" || ${LIB} == "pthread" \ |
17 | || ${LIB} == "rump") | | 17 | || ${LIB} == "rump") |
18 | | | 18 | |
19 | .if empty(ARMV6) && empty(ARMV7) | | 19 | .if empty(ARMV6) && empty(ARMV7) |
20 | SRCS.atomic+= atomic_add_32_cas.c atomic_add_32_nv_cas.c \ | | 20 | SRCS.atomic+= atomic_add_32_cas.c atomic_add_32_nv_cas.c \ |
21 | atomic_and_32_cas.c atomic_and_32_nv_cas.c \ | | 21 | atomic_and_32_cas.c atomic_and_32_nv_cas.c \ |
22 | atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \ | | 22 | atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \ |
23 | atomic_inc_32_cas.c atomic_inc_32_nv_cas.c \ | | 23 | atomic_inc_32_cas.c atomic_inc_32_nv_cas.c \ |
24 | atomic_or_32_cas.c atomic_or_32_nv_cas.c \ | | 24 | atomic_or_32_cas.c atomic_or_32_nv_cas.c \ |
25 | atomic_swap_32_cas.c membar_ops_nop.c | | 25 | atomic_swap_32_cas.c membar_ops_nop.c \ |
| | | 26 | atomic_xor_32_cas.c atomic_xor_16_cas.c atomic_xor_8_cas.c \ |
| | | 27 | atomic_sub_32_cas.c atomic_sub_16_cas.c atomic_sub_8_cas.c \ |
| | | 28 | atomic_nand_32_cas.c atomic_nand_16_cas.c atomic_nand_8_cas.c \ |
| | | 29 | atomic_or_16_cas.c atomic_or_8_cas.c \ |
| | | 30 | atomic_and_16_cas.c atomic_and_8_cas.c \ |
| | | 31 | atomic_add_16_cas.c atomic_add_8_cas.c \ |
| | | 32 | atomic_swap_16_cas.c atomic_swap_8_cas.c |
26 | .else | | 33 | .else |
27 | .for op in add and cas nand or xor | | 34 | .for op in add and cas nand or xor |
28 | .for sz in 8 16 32 64 | | 35 | .for sz in 8 16 32 64 |
29 | SRCS.atomic+= atomic_${op}_${sz}.S | | 36 | SRCS.atomic+= atomic_${op}_${sz}.S |
30 | .endfor | | 37 | .endfor |
31 | .endfor | | 38 | .endfor |
32 | SRCS.atomic+= atomic_dec_32.S atomic_dec_64.S | | 39 | SRCS.atomic+= atomic_dec_32.S atomic_dec_64.S |
33 | SRCS.atomic+= atomic_inc_32.S atomic_inc_64.S | | 40 | SRCS.atomic+= atomic_inc_32.S atomic_inc_64.S |
34 | SRCS.atomic+= atomic_swap.S atomic_swap_16.S atomic_swap_64.S | | 41 | SRCS.atomic+= atomic_swap.S atomic_swap_16.S atomic_swap_64.S |
35 | SRCS.atomic+= membar_ops.S | | 42 | SRCS.atomic+= membar_ops.S |
36 | .for op in add and nand or sub xor | | 43 | .for op in add and nand or sub xor |
37 | SRCS.atomic+= sync_fetch_and_${op}_8.S | | 44 | SRCS.atomic+= sync_fetch_and_${op}_8.S |
38 | .endfor | | 45 | .endfor |