 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.63 2014/02/20 18:14:11 dsl Exp $	*/
+/*	$NetBSD: cpu.h,v 1.64 2014/02/22 17:48:08 dsl Exp $	*/
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -140,38 +140,40 @@ struct cpu_info {
 	} ci_istate __aligned(8);
 #define ci_ipending	ci_istate.ipending
 #define	ci_ilevel	ci_istate.ilevel
 	int		ci_idepth;
 	void *		ci_intrstack;
 	uint32_t	ci_imask[NIPL];
 	uint32_t	ci_iunmask[NIPL];
 	uint32_t ci_flags;		/* flags; see below */
 	uint32_t ci_ipis;		/* interprocessor interrupts pending */
 	uint32_t sc_apic_version;	/* local APIC version */
-	uint32_t	ci_signature;	 /* X86 cpuid type */
+	uint32_t	ci_signature;	 /* X86 cpuid type (cpuid.1.%eax) */
 	uint32_t	ci_vendor[4];	 /* vendor string */
-	uint32_t	ci_cpu_serial[3]; /* PIII serial number */
+	uint32_t	_unused2;
 	uint32_t	ci_max_cpuid;	/* cpuid.0:%eax */
 	uint32_t	ci_max_ext_cpuid; /* cpuid.80000000:%eax */
 	volatile uint32_t	ci_lapic_counter;
-	uint32_t	ci_feat_val[5]; /* X86 CPUID feature bits
+	uint32_t	ci_feat_val[5]; /* X86 CPUID feature bits */
-					 *	[0] basic features %edx
+			/* [0] basic features cpuid.1:%edx
-					 *	[1] basic features %ecx
+			 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits)
-					 *	[2] extended features %edx
+			 * [2] extended features cpuid:80000001:%edx
-					 *	[3] extended features %ecx
+			 * [3] extended features cpuid:80000001:%ecx
-					 *	[4] VIA padlock features
+			 * [4] VIA padlock features
-					 */
+			 */
 	const struct cpu_functions *ci_func;  /* start/stop functions */
 	struct trapframe *ci_ddb_regs;
 	u_int ci_cflush_lsize;	/* CFLUSH insn line size */
 	struct x86_cache_info ci_cinfo[CAI_COUNT];
 	union descriptor *ci_gdt;
 #ifdef i386
 	struct i386tss	ci_doubleflt_tss;
 	struct i386tss	ci_ddbipi_tss;
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu_topology.c,v 1.8 2013/11/15 08:47:55 msaitoh Exp $	*/
+/*	$NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $	*/
 /*-
  * Copyright (c) 2009 Mindaugas Rasiukevicius <rmind at NetBSD org>,
  * Copyright (c) 2008 YAMAMOTO Takashi,
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -26,105 +26,95 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * x86 CPU topology detection.
+ *
  * References:
  * - 53668.pdf (7.10.2), 276613.pdf
  * - 31116.pdf, 41256.pdf, 25481.pdf
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.8 2013/11/15 08:47:55 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $");
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <machine/specialreg.h>
 #include <machine/cpu.h>
 #include <x86/cpufunc.h>
 #include <x86/cputypes.h>
 #include <x86/cpuvar.h>
 void
 x86_cpu_topology(struct cpu_info *ci)
+{
 	u_int lp_max;		/* Logical processors per package (node) */
 	u_int core_max;		/* Core per package */
 	int n, cpu_family, apic_id, smt_bits, core_bits = 0;
-	uint32_t descs[4], lextmode;
+	uint32_t descs[4];
 	apic_id = ci->ci_initapicid;
 	cpu_family = CPUID_TO_FAMILY(ci->ci_signature);
 	/* Initial values. */
 	ci->ci_package_id = apic_id;
 	ci->ci_core_id = 0;
 	ci->ci_smt_id = 0;
 	switch (cpu_vendor) {
 	case CPUVENDOR_INTEL:
 		if (cpu_family < 6)
 			return;
 		break;
 	case CPUVENDOR_AMD:
 		if (cpu_family < 0xf)
 			return;
 		break;
 	default:
 		return;
+	}
 	/* Determine the extended feature flags. */
 	x86_cpuid(0x80000000, descs);
 	lextmode = descs[0];
 	if (lextmode >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] = descs[3]; /* edx */
 		ci->ci_feat_val[3] = descs[2]; /* ecx */
 	/* Check for HTT support.  See notes below regarding AMD. */
 	if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
 		/* Maximum number of LPs sharing a cache (ebx[23:16]). */
 		x86_cpuid(1, descs);
 		lp_max = (descs[1] >> 16) & 0xff;
 	} else {
 		lp_max = 1;
+	}
 	switch (cpu_vendor) {
 	case CPUVENDOR_INTEL:
 		/* Check for leaf 4 support. */
-		x86_cpuid(0, descs);
+		if (ci->ci_max_cpuid >= 4) {
 		if (descs[0] >= 4) {
 			/* Maximum number of Cores per package (eax[31:26]). */
 			x86_cpuid2(4, 0, descs);
 			core_max = (descs[0] >> 26) + 1;
 		} else {
 			core_max = 1;
+		}
 		break;
 	case CPUVENDOR_AMD:
 		/* In a case of AMD, HTT flag means CMP support. */
 		if ((ci->ci_feat_val[0] & CPUID_HTT) == 0) {
 			core_max = 1;
 			break;
+		}
 		/* Legacy Method, LPs represent Cores. */
-		if (cpu_family < 0x10 || lextmode < 0x80000008) {
+		if (cpu_family < 0x10 || ci->ci_max_ext_cpuid < 0x80000008) {
 			core_max = lp_max;
 			break;
+		}
 		/* Number of Cores (NC) per package (ecx[7:0]). */
 		x86_cpuid(0x80000008, descs);
 		core_max = (descs[2] & 0xff) + 1;
 		/* Amount of bits representing Core ID (ecx[15:12]). */
 		n = (descs[2] >> 12) & 0x0f;
 		if (n != 0) {
 			/*
 			 * Extended Method.
 			 * core_bits = 2 ^ n (power of two)
 			 */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: identcpu.c,v 1.39 2013/12/23 11:40:57 msaitoh Exp $	*/
+/*	$NetBSD: identcpu.c,v 1.40 2014/02/22 17:48:08 dsl Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.39 2013/12/23 11:40:57 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.40 2014/02/22 17:48:08 dsl Exp $");
 #include "opt_xen.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <machine/specialreg.h>
 #include <machine/pio.h>
 #include <machine/cpu.h>
 @@ -125,27 +125,27 @@ cpu_probe_intel_cache(struct cpu_info *c
 						ci->ci_cinfo[cai->cai_index] =
 						    *cai;
+					}
+				}
+			}
+		}
+	}
 	if (cpuid_level >= 4) {
 		int type, level;
 		int ways, partitions, linesize, sets;
 		int caitype = -1;
 		int totalsize;
 		/* Parse the cache info from `cpuid leaf 4', if we have it. */
 		for (i = 0; ; i++) {
 			x86_cpuid2(4, i, descs);
 			type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
 			if (type == CPUID_DCP_CACHETYPE_N)
 				break;
 			level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
 			switch (level) {
 			case 1:
 				if (type == CPUID_DCP_CACHETYPE_I)
 					caitype = CAI_ICACHE;
 				else if (type == CPUID_DCP_CACHETYPE_D)
 					caitype = CAI_DCACHE;
 @@ -349,40 +349,31 @@ cpu_probe_k5(struct cpu_info *ci)
 		 */
 		flag = ci->ci_feat_val[0];
 		if ((flag & CPUID_APIC) != 0)
 			flag = (flag & ~CPUID_APIC) | CPUID_PGE;
 		ci->ci_feat_val[0] = flag;
+	}
 	cpu_probe_amd_cache(ci);
+}
 static void
 cpu_probe_k678(struct cpu_info *ci)
+{
 	uint32_t descs[4];
 	if (cpu_vendor != CPUVENDOR_AMD ||
 	    CPUID_TO_FAMILY(ci->ci_signature) < 6)
 		return;
 	/* Determine the extended feature flags. */
 	x86_cpuid(0x80000000, descs);
 	if (descs[0] >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[3] = descs[2]; /* %ecx */
 		ci->ci_feat_val[2] = descs[3]; /* %edx */
 	cpu_probe_amd_cache(ci);
+}
 static inline uint8_t
 cyrix_read_reg(uint8_t reg)
+{
 	outb(0x22, reg);
 	return inb(0x23);
+}
 static inline void
 cyrix_write_reg(uint8_t reg, uint8_t data)
 @@ -505,32 +496,26 @@ cpu_probe_c3(struct cpu_info *ci)
 	if (cpu_vendor != CPUVENDOR_IDT ||
 	    CPUID_TO_FAMILY(ci->ci_signature) < 6)
 	    	return;
 	family = CPUID_TO_FAMILY(ci->ci_signature);
 	model = CPUID_TO_MODEL(ci->ci_signature);
 	stepping = CPUID_TO_STEPPING(ci->ci_signature);
 	/* Determine the largest extended function value. */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	/* Determine the extended feature flags. */
 	if (lfunc >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] = descs[3];
 	if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) {
 		/* Nehemiah or Esther */
 		x86_cpuid(0xc0000000, descs);
 		lfunc = descs[0];
 		if (lfunc >= 0xc0000001) {	/* has ACE, RNG */
 		    int rng_enable = 0, ace_enable = 0;
 		    x86_cpuid(0xc0000001, descs);
 		    lfunc = descs[3];
 		    ci->ci_feat_val[4] = lfunc;
 		    /* Check for and enable RNG */
 		    if (lfunc & CPUID_VIA_HAS_RNG) {
 		    	if (!(lfunc & CPUID_VIA_DO_RNG)) {
 			    rng_enable++;
 @@ -565,27 +550,27 @@ cpu_probe_c3(struct cpu_info *ci)
 			    ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM;
+			}
+		    }
 		    /* Actually do the enables. */
 		    if (rng_enable) {
 			msr = rdmsr(MSR_VIA_RNG);
 			wrmsr(MSR_VIA_RNG, msr | MSR_VIA_RNG_ENABLE);
+		    }
 		    if (ace_enable) {
 			msr = rdmsr(MSR_VIA_ACE);
 			wrmsr(MSR_VIA_ACE, msr | MSR_VIA_ACE_ENABLE);
+		    }
+		}
+	}
 	/*
 	 * Determine L1 cache/TLB info.
 	 */
 	if (lfunc < 0x80000005) {
 		/* No L1 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000005, descs);
 @@ -606,27 +591,27 @@ cpu_probe_c3(struct cpu_info *ci)
 	if (family == 6 && model == 9 && stepping == 8) {
 		/* Erratum: stepping 8 reports 4 when it should be 2 */
 		cai->cai_associativity = 2;
+	}
 	cai = &ci->ci_cinfo[CAI_ICACHE];
 	cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]);
 	cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]);
 	cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]);
 	if (family == 6 && model == 9 && stepping == 8) {
 		/* Erratum: stepping 8 reports 4 when it should be 2 */
 		cai->cai_associativity = 2;
+	}
 	/*
 	 * Determine L2 cache/TLB info.
 	 */
 	if (lfunc < 0x80000006) {
 		/* No L2 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000006, descs);
 	cai = &ci->ci_cinfo[CAI_L2CACHE];
 	if (family > 6 || model >= 9) {
 		cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]);
 @@ -702,79 +687,99 @@ cpu_probe(struct cpu_info *ci)
 	cpu_vendor = i386_nocpuid_cpus[cputype << 1];
 	cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1];
 	if (cpuid_level < 0)
 		return;
 	for (i = 0; i < __arraycount(ci->ci_feat_val); i++) {
 		ci->ci_feat_val[i] = 0;
+	}
 	x86_cpuid(0, descs);
 	cpuid_level = descs[0];
 	ci->ci_max_cpuid = descs[0];
 	ci->ci_vendor[0] = descs[1];
 	ci->ci_vendor[2] = descs[2];
 	ci->ci_vendor[1] = descs[3];
 	ci->ci_vendor[3] = 0;
 	if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0)
 		cpu_vendor = CPUVENDOR_INTEL;
 	else if (memcmp(ci->ci_vendor,  "AuthenticAMD", 12) == 0)
 		cpu_vendor = CPUVENDOR_AMD;
 	else if (memcmp(ci->ci_vendor,  "CyrixInstead", 12) == 0)
 		cpu_vendor = CPUVENDOR_CYRIX;
 	else if (memcmp(ci->ci_vendor,  "Geode by NSC", 12) == 0)
 		cpu_vendor = CPUVENDOR_CYRIX;
 	else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0)
 		cpu_vendor = CPUVENDOR_IDT;
 	else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0)
 		cpu_vendor = CPUVENDOR_TRANSMETA;
 	else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0)
 		cpu_vendor = CPUVENDOR_VORTEX86;
 	else
 		cpu_vendor = CPUVENDOR_UNKNOWN;
 	x86_cpuid(0x80000000, brand);
 	if (brand[0] >= 0x80000004) {
 		x86_cpuid(0x80000002, brand);
 		x86_cpuid(0x80000003, brand + 4);
 		x86_cpuid(0x80000004, brand + 8);
 		for (i = 0; i < 48; i++) {
 			if (((char *) brand)[i] != ' ')
 				break;
 		memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i);
 	if (cpuid_level >= 1) {
 		x86_cpuid(1, descs);
 		ci->ci_signature = descs[0];
 		miscbytes = descs[1];
 		ci->ci_feat_val[1] = descs[2];
 		ci->ci_feat_val[0] = descs[3];
 		/* Determine family + class. */
 		cpu_class = CPUID_TO_FAMILY(ci->ci_signature)
 		    + (CPUCLASS_386 - 3);
 		if (cpu_class > CPUCLASS_686)
 			cpu_class = CPUCLASS_686;
 		/* CLFLUSH line size is next 8 bits */
 		if (ci->ci_feat_val[0] & CPUID_CFLUSH)
 			ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3;
 		ci->ci_initapicid = (miscbytes >> 24) & 0xff;
+	}
 	/*
 	 * Get the basic information from the extended cpuid leafs.
 	 * These were first implemented by amd, but most of the values
 	 * match with those generated by modern intel cpus.
 	 */
 	x86_cpuid(0x80000000, descs);
 	if (descs[0] == 0x80000000)
 		ci->ci_max_ext_cpuid = descs[0];
 	else
 		ci->ci_max_ext_cpuid = 0;
 	if (ci->ci_max_ext_cpuid >= 0x80000001) {
 		/* Determine the extended feature flags. */
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[3] = descs[2]; /* %ecx */
 		ci->ci_feat_val[2] = descs[3]; /* %edx */
+	}
 	if (ci->ci_max_ext_cpuid >= 0x80000004) {
 		x86_cpuid(0x80000002, brand);
 		x86_cpuid(0x80000003, brand + 4);
 		x86_cpuid(0x80000004, brand + 8);
 		/* Skip leading spaces on brand */
 		for (i = 0; i < 48; i++) {
 			if (((char *) brand)[i] != ' ')
 				break;
+		}
 		memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i);
+	}
 	cpu_probe_intel(ci);
 	cpu_probe_k5(ci);
 	cpu_probe_k678(ci);
 	cpu_probe_cyrix(ci);
 	cpu_probe_winchip(ci);
 	cpu_probe_c3(ci);
 	cpu_probe_geode(ci);
 	cpu_probe_vortex86(ci);
 	x86_cpu_topology(ci);
 	if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) &&
 	    (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) {
 @@ -863,17 +868,23 @@ cpu_identify(struct cpu_info *ci)
+	}
 	/* If we have FXSAVE/FXRESTOR, use them. */
 	if (cpu_feature[0] & CPUID_FXSR) {
 		i386_use_fxsave = 1;
 		/*
 		 * If we have SSE/SSE2, enable XMM exceptions, and
 		 * notify userland.
 		 */
 		if (cpu_feature[0] & CPUID_SSE)
 			i386_has_sse = 1;
 		if (cpu_feature[0] & CPUID_SSE2)
 			i386_has_sse2 = 1;
-	} else
+	} else {
 		i386_use_fxsave = 0;
+	}
 #else
 	/*
 	 * i386_use_fxsave, i386_has_sse and i386_has_sse2 are
 	 * #defined to 1.
 	 */
 #endif	/* i386 */
+}