Wed Mar 19 18:04:32 2014 UTC ()
Fix uninitialized variable wait in intel_ddi_prepare_link_retrain.

Move a line around, too, to avoid merge conflicts with upstream.

Noted by maxv@.


(riastradh)
diff -r1.2 -r1.3 src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c
cvs diff -r1.2 -r1.3 src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_ddi.c (expand / switch to unified diff)

--- src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_ddi.c 2014/03/18 18:20:42 1.2
+++ src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_ddi.c 2014/03/19 18:04:32 1.3
@@ -1347,28 +1347,28 @@ void intel_ddi_pll_init(struct drm_devic @@ -1347,28 +1347,28 @@ void intel_ddi_pll_init(struct drm_devic
1347 if (val & LCPLL_CD_SOURCE_FCLK) 1347 if (val & LCPLL_CD_SOURCE_FCLK)
1348 DRM_ERROR("CDCLK source is not LCPLL\n"); 1348 DRM_ERROR("CDCLK source is not LCPLL\n");
1349 1349
1350 if (val & LCPLL_PLL_DISABLE) 1350 if (val & LCPLL_PLL_DISABLE)
1351 DRM_ERROR("LCPLL is disabled\n"); 1351 DRM_ERROR("LCPLL is disabled\n");
1352} 1352}
1353 1353
1354void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1354void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1355{ 1355{
1356 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1356 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1357 struct intel_dp *intel_dp = &intel_dig_port->dp; 1357 struct intel_dp *intel_dp = &intel_dig_port->dp;
1358 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1358 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1359 enum port port = intel_dig_port->port; 1359 enum port port = intel_dig_port->port;
1360 bool wait; 
1361 uint32_t val; 1360 uint32_t val;
 1361 bool wait = false;
1362 1362
1363 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1363 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1364 val = I915_READ(DDI_BUF_CTL(port)); 1364 val = I915_READ(DDI_BUF_CTL(port));
1365 if (val & DDI_BUF_CTL_ENABLE) { 1365 if (val & DDI_BUF_CTL_ENABLE) {
1366 val &= ~DDI_BUF_CTL_ENABLE; 1366 val &= ~DDI_BUF_CTL_ENABLE;
1367 I915_WRITE(DDI_BUF_CTL(port), val); 1367 I915_WRITE(DDI_BUF_CTL(port), val);
1368 wait = true; 1368 wait = true;
1369 } 1369 }
1370 1370
1371 val = I915_READ(DP_TP_CTL(port)); 1371 val = I915_READ(DP_TP_CTL(port));
1372 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1372 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1373 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1373 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1374 I915_WRITE(DP_TP_CTL(port), val); 1374 I915_WRITE(DP_TP_CTL(port), val);