Wed Mar 26 01:59:08 2014 UTC ()
Let bus_space so the endian conversion if needed


(matt)
diff -r1.5.2.2 -r1.5.2.3 src/sys/arch/arm/cortex/gic.c
cvs diff -r1.5.2.2 -r1.5.2.3 src/sys/arch/arm/cortex/gic.c (expand / switch to unified diff)

--- src/sys/arch/arm/cortex/gic.c 2014/02/15 16:18:36 1.5.2.2
+++ src/sys/arch/arm/cortex/gic.c 2014/03/26 01:59:08 1.5.2.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: gic.c,v 1.5.2.2 2014/02/15 16:18:36 matt Exp $ */ 1/* $NetBSD: gic.c,v 1.5.2.3 2014/03/26 01:59:08 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -21,27 +21,27 @@ @@ -21,27 +21,27 @@
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#define _INTR_PRIVATE 31#define _INTR_PRIVATE
32 32
33#include <sys/cdefs.h> 33#include <sys/cdefs.h>
34__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.5.2.2 2014/02/15 16:18:36 matt Exp $"); 34__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.5.2.3 2014/03/26 01:59:08 matt Exp $");
35 35
36#include <sys/param.h> 36#include <sys/param.h>
37#include <sys/bus.h> 37#include <sys/bus.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/evcnt.h> 39#include <sys/evcnt.h>
40#include <sys/intr.h> 40#include <sys/intr.h>
41#include <sys/proc.h> 41#include <sys/proc.h>
42#include <sys/xcall.h> /* for xc_ipi_handler */ 42#include <sys/xcall.h> /* for xc_ipi_handler */
43 43
44#include <arm/armreg.h> 44#include <arm/armreg.h>
45#include <arm/cpufunc.h> 45#include <arm/cpufunc.h>
46#include <arm/atomic.h> 46#include <arm/atomic.h>
47 47
@@ -99,48 +99,44 @@ static struct armgic_softc { @@ -99,48 +99,44 @@ static struct armgic_softc {
99 }, 99 },
100}; 100};
101 101
102static struct intrsource armgic_dummy_source; 102static struct intrsource armgic_dummy_source;
103 103
104__CTASSERT(NIPL == 8); 104__CTASSERT(NIPL == 8);
105 105
106/* 106/*
107 * GIC register are always in little-endian. 107 * GIC register are always in little-endian.
108 */ 108 */
109static inline uint32_t 109static inline uint32_t
110gicc_read(struct armgic_softc *sc, bus_size_t o) 110gicc_read(struct armgic_softc *sc, bus_size_t o)
111{ 111{
112 uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_gicch, o); 112 return bus_space_read_4(sc->sc_memt, sc->sc_gicch, o);
113 return le32toh(v); 
114} 113}
115 114
116static inline void 115static inline void
117gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 116gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
118{ 117{
119 v = htole32(v); 
120 bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v); 118 bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v);
121} 119}
122 120
123static inline uint32_t 121static inline uint32_t
124gicd_read(struct armgic_softc *sc, bus_size_t o) 122gicd_read(struct armgic_softc *sc, bus_size_t o)
125{ 123{
126 uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o); 124 return bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o);
127 return le32toh(v); 
128} 125}
129 126
130static inline void 127static inline void
131gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 128gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
132{ 129{
133 v = htole32(v); 
134 bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v); 130 bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v);
135} 131}
136 132
137/* 133/*
138 * In the GIC prioritization scheme, lower numbers have higher priority. 134 * In the GIC prioritization scheme, lower numbers have higher priority.
139 */ 135 */
140static inline uint32_t 136static inline uint32_t
141armgic_ipl_to_priority(int ipl) 137armgic_ipl_to_priority(int ipl)
142{ 138{
143 return (IPL_HIGH - ipl) * GICC_PMR_PRIORITIES / NIPL; 139 return (IPL_HIGH - ipl) * GICC_PMR_PRIORITIES / NIPL;
144} 140}
145 141
146#if 0 142#if 0