Wed Mar 26 02:00:46 2014 UTC ()

For armv7, enable BE properly.  Make sure UNAL is always set.


(matt)

diff -r1.89.10.1 -r1.89.10.2 src/sys/arch/arm/arm/cpufunc.c

--- src/sys/arch/arm/arm/cpufunc.c 2014/02/15 16:18:35	1.89.10.1
+++ src/sys/arch/arm/arm/cpufunc.c 2014/03/26 02:00:45	1.89.10.2

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.c,v 1.89.10.1 2014/02/15 16:18:35 matt Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.89.10.2 2014/03/26 02:00:45 matt Exp $	*/
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
  * arm8 support code Copyright (c) 1997 ARM Limited
  * arm8 support code Copyright (c) 1997 Causality Limited
  * arm9 support code Copyright (C) 2001 ARM Ltd
  * arm11 support code Copyright (c) 2007 Microsoft
  * cortexa8 support code Copyright (c) 2008 3am Software Foundry
  * cortexa8 improvements Copyright (c) Goeran Weinholt
  * Copyright (c) 1997 Mark Brinicombe.
  * Copyright (c) 1997 Causality Limited
  * All rights reserved.
+ *
 @@ -39,27 +39,27 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * RiscBSD kernel project
+ *
  * cpufuncs.c
+ *
  * C functions for supporting CPU / MMU / TLB specific operations.
+ *
  * Created	: 30/01/97
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.89.10.1 2014/02/15 16:18:35 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.89.10.2 2014/03/26 02:00:45 matt Exp $");
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
 #include "opt_perfctrs.h"
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/pmc.h>
 #include <sys/systm.h>
 #include <machine/cpu.h>
 #include <machine/bootconfig.h>
 #include <arch/arm/arm/disassem.h>
 @@ -3043,54 +3043,49 @@ struct cpu_option armv7_options[] = {
     { "cpu.nocache",    OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
     { "armv7.cache",    BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
     { "armv7.icache",   BIC, OR,  CPU_CONTROL_IC_ENABLE },
     { "armv7.dcache",   BIC, OR,  CPU_CONTROL_DC_ENABLE },
 	{ NULL, 			IGN, IGN, 0}
 };
 void
 armv7_setup(char *args)
+{
 	int cpuctrl;
 	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE
-	    | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_BPRD_ENABLE ;
+	    | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_BPRD_ENABLE
-#if 0
+#ifdef __ARMEB__
-	int cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_EX_BEND
 	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
 	    | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
 	    | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
 	    | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
 #endif
 #ifdef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_UNAL_ENABLE;
+	    | CPU_CONTROL_AFLT_ENABLE
 #else
 	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
 #endif
 	    | CPU_CONTROL_UNAL_ENABLE;
 	const int cpuctrlmask = cpuctrl | CPU_CONTROL_AFLT_ENABLE;
 	cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl);
 #ifndef ARM_HAS_VBAR
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
 #endif
 	/* Clear out the cache */
 	cpu_idcache_wbinv_all();
 	/* Set the control register */
 	curcpu()->ci_ctrl = cpuctrl;
-	cpu_control(0xffffffff, cpuctrl);
+	cpu_control(cpuctrlmask, cpuctrl);
+}
 #endif /* CPU_CORTEX */
 #if defined(CPU_ARM1136) || defined(CPU_ARM1176)
 void
 arm11x6_setup(char *args)
+{
 	int cpuctrl, cpuctrl_wax;
 	uint32_t auxctrl, auxctrl_wax;
 	uint32_t tmp, tmp2;
 	uint32_t sbz=0;
 	uint32_t cpuid;