Sat Apr 5 22:41:50 2014 UTC ()
Initialize cpu_cc_freq with our CPU speed.


(matt)
diff -r1.7 -r1.8 src/sys/arch/arm/marvell/armadaxp.c
cvs diff -r1.7 -r1.8 src/sys/arch/arm/marvell/armadaxp.c (expand / switch to unified diff)

--- src/sys/arch/arm/marvell/armadaxp.c 2014/03/15 10:54:40 1.7
+++ src/sys/arch/arm/marvell/armadaxp.c 2014/04/05 22:41:50 1.8
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armadaxp.c,v 1.7 2014/03/15 10:54:40 kiyohara Exp $ */ 1/* $NetBSD: armadaxp.c,v 1.8 2014/04/05 22:41:50 matt Exp $ */
2/******************************************************************************* 2/*******************************************************************************
3Copyright (C) Marvell International Ltd. and its affiliates 3Copyright (C) Marvell International Ltd. and its affiliates
4 4
5Developed by Semihalf 5Developed by Semihalf
6 6
7******************************************************************************** 7********************************************************************************
8Marvell BSD License 8Marvell BSD License
9 9
10If you received this File from Marvell, you may opt to use, redistribute and/or 10If you received this File from Marvell, you may opt to use, redistribute and/or
11modify this File under the following licensing terms. 11modify this File under the following licensing terms.
12Redistribution and use in source and binary forms, with or without modification, 12Redistribution and use in source and binary forms, with or without modification,
13are permitted provided that the following conditions are met: 13are permitted provided that the following conditions are met:
14 14
@@ -27,27 +27,27 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIG @@ -27,27 +27,27 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIG
27ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 29DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
30ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 36
37*******************************************************************************/ 37*******************************************************************************/
38 38
39#include <sys/cdefs.h> 39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.7 2014/03/15 10:54:40 kiyohara Exp $"); 40__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.8 2014/04/05 22:41:50 matt Exp $");
41 41
42#define _INTR_PRIVATE 42#define _INTR_PRIVATE
43 43
44#include "opt_mvsoc.h" 44#include "opt_mvsoc.h"
45 45
46#include <sys/param.h> 46#include <sys/param.h>
47#include <sys/bus.h> 47#include <sys/bus.h>
48 48
49#include <machine/intr.h> 49#include <machine/intr.h>
50 50
51#include <arm/pic/picvar.h> 51#include <arm/pic/picvar.h>
52#include <arm/pic/picvar.h> 52#include <arm/pic/picvar.h>
53 53
@@ -359,26 +359,28 @@ armadaxp_getclks(void) @@ -359,26 +359,28 @@ armadaxp_getclks(void)
359 mvPclk = clock_table_xp[sar_cpu_freq] * 359 mvPclk = clock_table_xp[sar_cpu_freq] *
360 freq_conf_table[sar_fab_freq].vco_cpu; 360 freq_conf_table[sar_fab_freq].vco_cpu;
361 361
362 /* Get L2CLK clock frequency and use as system clock (mvSysclk) */ 362 /* Get L2CLK clock frequency and use as system clock (mvSysclk) */
363 mvSysclk = mvPclk / freq_conf_table[sar_fab_freq].vco_l2c; 363 mvSysclk = mvPclk / freq_conf_table[sar_fab_freq].vco_l2c;
364 364
365 /* Round mvSysclk value to integer MHz */ 365 /* Round mvSysclk value to integer MHz */
366 if (((mvPclk % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 366 if (((mvPclk % freq_conf_table[sar_fab_freq].vco_l2c) * 10 /
367 freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 367 freq_conf_table[sar_fab_freq].vco_l2c) >= 5)
368 mvSysclk++; 368 mvSysclk++;
369 369
370 mvPclk *= 1000000; 370 mvPclk *= 1000000;
371 mvSysclk *= 1000000; 371 mvSysclk *= 1000000;
 372
 373 curcpu()->ci_data.cpu_cc_freq = mvPclk;
372} 374}
373 375
374void 376void
375armada370_getclks(void) 377armada370_getclks(void)
376{ 378{
377 uint32_t sar; 379 uint32_t sar;
378 uint8_t cpu_freq, fab_freq; 380 uint8_t cpu_freq, fab_freq;
379 381
380 sar = read_miscreg(ARMADAXP_MISC_SAR_LO); 382 sar = read_miscreg(ARMADAXP_MISC_SAR_LO);
381 if (sar & 0x00100000) 383 if (sar & 0x00100000)
382 mvTclk = 200000000; /* 200 MHz */ 384 mvTclk = 200000000; /* 200 MHz */
383 else 385 else
384 mvTclk = 166666667; /* 166 MHz */ 386 mvTclk = 166666667; /* 166 MHz */