Wed Jul 30 07:20:34 2014 UTC ()
Fixup some comments.


(skrll)
diff -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
cvs diff -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S 2014/07/30 07:11:57 1.5
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S 2014/07/30 07:20:34 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $ */ 1/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.6 2014/07/30 07:20:34 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007 Microsoft 4 * Copyright (c) 2007 Microsoft
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -53,27 +53,27 @@ @@ -53,27 +53,27 @@
53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE. 58 * POSSIBILITY OF SUCH DAMAGE.
59 */ 59 */
60 60
61 61
62#include "assym.h" 62#include "assym.h"
63#include <machine/asm.h> 63#include <machine/asm.h>
64#include <arm/locore.h> 64#include <arm/locore.h>
65 65
66RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $") 66RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.6 2014/07/30 07:20:34 skrll Exp $")
67 67
68#if 0 68#if 0
69#define Invalidate_I_cache(Rtmp1, Rtmp2) \ 69#define Invalidate_I_cache(Rtmp1, Rtmp2) \
70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ 70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
71#else 71#else
72/* 72/*
73 * Workaround for 73 * Workaround for
74 * 74 *
75 * Erratum 411920 in ARM1136 (fixed in r1p4) 75 * Erratum 411920 in ARM1136 (fixed in r1p4)
76 * Erratum 415045 in ARM1176 (fixed in r0p5?) 76 * Erratum 415045 in ARM1176 (fixed in r0p5?)
77 * 77 *
78 * - value of arg 'reg' Should Be Zero 78 * - value of arg 'reg' Should Be Zero
79 */ 79 */
@@ -130,54 +130,54 @@ ENTRY_NP(arm11x6_icache_sync_all) @@ -130,54 +130,54 @@ ENTRY_NP(arm11x6_icache_sync_all)
130 Invalidate_I_cache(r0, r1) 130 Invalidate_I_cache(r0, r1)
131 RET 131 RET
132END(arm11x6_icache_sync_all) 132END(arm11x6_icache_sync_all)
133 133
134ENTRY_NP(arm11x6_flush_prefetchbuf) 134ENTRY_NP(arm11x6_flush_prefetchbuf)
135 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */ 135 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
136 RET 136 RET
137END(arm11x6_flush_prefetchbuf) 137END(arm11x6_flush_prefetchbuf)
138 138
139ENTRY_NP(arm11x6_icache_sync_range) 139ENTRY_NP(arm11x6_icache_sync_range)
140 add r1, r1, r0 140 add r1, r1, r0
141 sub r1, r1, #1 141 sub r1, r1, #1
142 /* Erratum ARM1136 371025, workaround #2 */ 142 /* Erratum ARM1136 371025, workaround #2 */
143 /* Erratum ARM1176 371367 */ 143 /* Erratum ARM1176 371367, workaround #2 */
144 mrs r2, cpsr /* save the CPSR */ 144 mrs r2, cpsr /* save the CPSR */
145 cpsid ifa /* disable interrupts (irq,fiq,abort) */ 145 cpsid ifa /* disable interrupts (irq,fiq,abort) */
146 mov r3, #0 146 mov r3, #0
147 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ 147 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
148 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ 148 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
149 add r3, pc, #0x24 149 add r3, pc, #0x24
150 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ 150 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
151 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ 151 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
152 msr cpsr_cx, r2 /* local_irq_restore */ 152 msr cpsr_cx, r2 /* local_irq_restore */
153 nop 153 nop
154 nop 154 nop
155 nop 155 nop
156 nop 156 nop
157 nop 157 nop
158 nop 158 nop
159 nop 159 nop
160 160
161 mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */ 161 mcrr p15, 0, r1, r0, c12 /* clean D cache range */
162 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 162 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
163 RET 163 RET
164END(arm11x6_icache_sync_range) 164END(arm11x6_icache_sync_range)
165 165
166ENTRY_NP(arm11x6_idcache_wbinv_range) 166ENTRY_NP(arm11x6_idcache_wbinv_range)
167 add r1, r1, r0 167 add r1, r1, r0
168 sub r1, r1, #1 168 sub r1, r1, #1
169 /* Erratum ARM1136 371025, workaround #2 */ 169 /* Erratum ARM1136 371025, workaround #2 */
170 /* Erratum ARM1176 371367 */ 170 /* Erratum ARM1176 371367, workaround #2 */
171 mrs r2, cpsr /* save the CPSR */ 171 mrs r2, cpsr /* save the CPSR */
172 cpsid ifa /* disable interrupts (irq,fiq,abort) */ 172 cpsid ifa /* disable interrupts (irq,fiq,abort) */
173 mov r3, #0 173 mov r3, #0
174 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ 174 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
175 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ 175 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
176 add r3, pc, #0x24 176 add r3, pc, #0x24
177 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ 177 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
178 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ 178 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
179 msr cpsr_cx, r2 /* local_irq_restore */ 179 msr cpsr_cx, r2 /* local_irq_restore */
180 nop 180 nop
181 nop 181 nop
182 nop 182 nop
183 nop 183 nop