Sat Sep 13 17:48:00 2014 UTC ()
add some more usb regs


(jmcneill)
diff -r1.24 -r1.25 src/sys/arch/arm/allwinner/awin_reg.h
diff -r1.12 -r1.13 src/sys/arch/arm/allwinner/awin_usb.c
cvs diff -r1.24 -r1.25 src/sys/arch/arm/allwinner/Attic/awin_reg.h (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_reg.h 2014/09/11 00:50:39 1.24
+++ src/sys/arch/arm/allwinner/Attic/awin_reg.h 2014/09/13 17:48:00 1.25
@@ -150,26 +150,29 @@ @@ -150,26 +150,29 @@
150#define AWIN_DE_BE1_OFFSET 0x00240000 150#define AWIN_DE_BE1_OFFSET 0x00240000
151#define AWIN_DE_BE0_OFFSET 0x00260000 151#define AWIN_DE_BE0_OFFSET 0x00260000
152#define AWIN_MP_OFFSET 0x00280000 152#define AWIN_MP_OFFSET 0x00280000
153#define AWIN_AVG_OFFSET 0x002A0000 153#define AWIN_AVG_OFFSET 0x002A0000
154#define AWIN_SDRAM_PBASE 0x40000000 154#define AWIN_SDRAM_PBASE 0x40000000
155 155
156/* A10/A20 SRAM Controller */ 156/* A10/A20 SRAM Controller */
157#define AWIN_SRAM_CTL0_REG 0x0000 157#define AWIN_SRAM_CTL0_REG 0x0000
158#define AWIN_SRAM_CTL1_REG 0x0004 158#define AWIN_SRAM_CTL1_REG 0x0004
159#define AWIN_SRAM_VER_REG 0x0024 159#define AWIN_SRAM_VER_REG 0x0024
160 160
161#define AWIN_SRAM_CTL1_A3_A4 __BITS(5,4) 161#define AWIN_SRAM_CTL1_A3_A4 __BITS(5,4)
162#define AWIN_SRAM_CTL1_A3_A4_EMAC 1 162#define AWIN_SRAM_CTL1_A3_A4_EMAC 1
 163#define AWIN_SRAM_CTL1_SRAMD_MAP __BIT(0)
 164#define AWIN_SRAM_CTL1_SRAMD_MAP_CPUDMA 0
 165#define AWIN_SRAM_CTL1_SRAMD_MAP_USB0 1
163 166
164#define AWIN_SRAM_VER_KEY_FIELD __BITS(31,16) 167#define AWIN_SRAM_VER_KEY_FIELD __BITS(31,16)
165#define AWIN_SRAM_VER_R_EN __BIT(15) 168#define AWIN_SRAM_VER_R_EN __BIT(15)
166#define AWIN_SRAM_VER_BOOT_SEL_PAD_STA __BIT(8) 169#define AWIN_SRAM_VER_BOOT_SEL_PAD_STA __BIT(8)
167#define AWIN_SRAM_VER_BITS __BITS(7,0) 170#define AWIN_SRAM_VER_BITS __BITS(7,0)
168 171
169/* A10/A20 DRAM Controller */ 172/* A10/A20 DRAM Controller */
170#define AWIN_DRAM_CCR_REG 0x0000 173#define AWIN_DRAM_CCR_REG 0x0000
171#define AWIN_DRAM_DCR_REG 0x0004 174#define AWIN_DRAM_DCR_REG 0x0004
172#define AWIN_DRAM_IOCR_REG 0x0008 175#define AWIN_DRAM_IOCR_REG 0x0008
173#define AWIN_DRAM_CSR_REG 0x000C 176#define AWIN_DRAM_CSR_REG 0x000C
174#define AWIN_DRAM_DRR_REG 0x0010 177#define AWIN_DRAM_DRR_REG 0x0010
175#define AWIN_DRAM_TPR0_REG 0x0014 178#define AWIN_DRAM_TPR0_REG 0x0014
@@ -1015,38 +1018,64 @@ struct awin_mmc_idma_descriptor { @@ -1015,38 +1018,64 @@ struct awin_mmc_idma_descriptor {
1015#define AWIN_HDMI_CLK_SRC_SEL_PLL3_2X 2 1018#define AWIN_HDMI_CLK_SRC_SEL_PLL3_2X 2
1016#define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X 3 1019#define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X 3
1017#define AWIN_HDMI_CLK_DIV_RATIO_M __BITS(3,0) 1020#define AWIN_HDMI_CLK_DIV_RATIO_M __BITS(3,0)
1018 1021
1019#define AWIN_CLK_OUT_ENABLE __BIT(31) 1022#define AWIN_CLK_OUT_ENABLE __BIT(31)
1020#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24) 1023#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
1021#define AWIN_CLK_OUT_SRC_SEL_32K 0 1024#define AWIN_CLK_OUT_SRC_SEL_32K 0
1022#define AWIN_CLK_OUT_SRC_SEL_LOSC 1 1025#define AWIN_CLK_OUT_SRC_SEL_LOSC 1
1023#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2 1026#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2
1024#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20) 1027#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20)
1025#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8) 1028#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8)
1026 1029
1027/* USB device offsets */ 1030/* USB device offsets */
1028#define AWIN_USB0_PHY_CSR_REG 0x0404 1031#define AWIN_USB0_PHY_CSR_REG 0x0400
 1032#define AWIN_USB0_PHY_CTL_REG 0x0404
1029#define AWIN_EHCI_OFFSET 0x0000 1033#define AWIN_EHCI_OFFSET 0x0000
1030#define AWIN_EHCI_SIZE 0x0400 1034#define AWIN_EHCI_SIZE 0x0400
1031#define AWIN_OHCI_OFFSET 0x0400 1035#define AWIN_OHCI_OFFSET 0x0400
1032#define AWIN_OHCI_SIZE 0x0400 1036#define AWIN_OHCI_SIZE 0x0400
1033#define AWIN_USB_PMU_IRQ_REG 0x0800 1037#define AWIN_USB_PMU_IRQ_REG 0x0800
1034 1038
1035#define AWIN_USB0_PHY_CSR_ADDR __BITS(15,8) 1039#define AWIN_USB0_PHY_CSR_VBUS_VALID_DATA __BIT(30)
1036#define AWIN_USB0_PHY_CSR_DAT __BIT(7) 1040#define AWIN_USB0_PHY_CSR_VBUS_VALID_VBUS __BIT(29)
1037#define AWIN_USB0_PHY_CSR_CLK2 __BIT(2) 1041#define AWIN_USB0_PHY_CSR_EXT_ID_STATUS __BIT(28)
1038#define AWIN_USB0_PHY_CSR_CLK1 __BIT(1) 1042#define AWIN_USB0_PHY_CSR_EXT_DM_STATUS __BIT(27)
1039#define AWIN_USB0_PHY_CSR_CLK0 __BIT(0) 1043#define AWIN_USB0_PHY_CSR_EXT_DP_STATUS __BIT(26)
 1044#define AWIN_USB0_PHY_CSR_MERGED_VBUS_STATUS __BIT(25)
 1045#define AWIN_USB0_PHY_CSR_MERGED_ID_STATUS __BIT(24)
 1046#define AWIN_USB0_PHY_CSR_ID_PULLUP_EN __BIT(17)
 1047#define AWIN_USB0_PHY_CSR_DPDM_PULLUP_EN __BIT(16)
 1048#define AWIN_USB0_PHY_CSR_FORCE_ID __BITS(15,14)
 1049#define AWIN_USB0_PHY_CSR_FORCE_ID_LOW 2
 1050#define AWIN_USB0_PHY_CSR_FORCE_ID_HIGH 3
 1051#define AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID __BITS(13,12)
 1052#define AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID_LOW 2
 1053#define AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID_HIGH 3
 1054#define AWIN_USB0_PHY_CSR_VBUS_VALID_SRC __BITS(11,10)
 1055#define AWIN_USB0_PHY_CSR_HOSC_EN __BIT(7)
 1056#define AWIN_USB0_PHY_CSR_VBUS_CHANGE_DET __BIT(6)
 1057#define AWIN_USB0_PHY_CSR_ID_CHANGE_DET __BIT(5)
 1058#define AWIN_USB0_PHY_CSR_DPDM_CHANGE_DET __BIT(4)
 1059#define AWIN_USB0_PHY_CSR_IRQ_EN __BIT(3)
 1060#define AWIN_USB0_PHY_CSR_VBUS_CHANGE_DET_EN __BIT(2)
 1061#define AWIN_USB0_PHY_CSR_ID_CHANGE_DET_EN __BIT(1)
 1062#define AWIN_USB0_PHY_CSR_DPDM_CHANGE_DET_EN __BIT(0)
 1063
 1064#define AWIN_USB0_PHY_CTL_ADDR __BITS(15,8)
 1065#define AWIN_USB0_PHY_CTL_DAT __BIT(7)
 1066#define AWIN_USB0_PHY_CTL_CLK2 __BIT(2)
 1067#define AWIN_USB0_PHY_CTL_CLK1 __BIT(1)
 1068#define AWIN_USB0_PHY_CTL_CLK0 __BIT(0)
1040 1069
1041#define AWIN_USB_PMU_IRQ_AHB_INCR8 __BIT(10) 1070#define AWIN_USB_PMU_IRQ_AHB_INCR8 __BIT(10)
1042#define AWIN_USB_PMU_IRQ_AHB_INCR4 __BIT(9) 1071#define AWIN_USB_PMU_IRQ_AHB_INCR4 __BIT(9)
1043#define AWIN_USB_PMU_IRQ_AHB_INCRX __BIT(8) 1072#define AWIN_USB_PMU_IRQ_AHB_INCRX __BIT(8)
1044#define AWIN_USB_PMU_IRQ_ULPI_BYPASS __BIT(0) 1073#define AWIN_USB_PMU_IRQ_ULPI_BYPASS __BIT(0)
1045 1074
1046/* PATA Definitions */ 1075/* PATA Definitions */
1047#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */ 1076#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */
1048 1077
1049/* A10 Interrupt Register Definitions */ 1078/* A10 Interrupt Register Definitions */
1050#define AWIN_INTC_VECTOR_REG 0x0000 1079#define AWIN_INTC_VECTOR_REG 0x0000
1051#define AWIN_INTC_BASE_ADDR_REG 0x0004 1080#define AWIN_INTC_BASE_ADDR_REG 0x0004
1052#define AWIN_NMI_INT_CTRL_REG 0x000C 1081#define AWIN_NMI_INT_CTRL_REG 0x000C
cvs diff -r1.12 -r1.13 src/sys/arch/arm/allwinner/Attic/awin_usb.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_usb.c 2014/06/24 05:07:31 1.12
+++ src/sys/arch/arm/allwinner/Attic/awin_usb.c 2014/09/13 17:48:00 1.13
@@ -24,27 +24,27 @@ @@ -24,27 +24,27 @@
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29#define USBH_PRIVATE 29#define USBH_PRIVATE
30 30
31#include "locators.h" 31#include "locators.h"
32#include "ohci.h" 32#include "ohci.h"
33#include "ehci.h" 33#include "ehci.h"
34 34
35#include <sys/cdefs.h> 35#include <sys/cdefs.h>
36 36
37__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.12 2014/06/24 05:07:31 skrll Exp $"); 37__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.13 2014/09/13 17:48:00 jmcneill Exp $");
38 38
39#include <sys/param.h> 39#include <sys/param.h>
40#include <sys/bus.h> 40#include <sys/bus.h>
41#include <sys/device.h> 41#include <sys/device.h>
42#include <sys/intr.h> 42#include <sys/intr.h>
43#include <sys/systm.h> 43#include <sys/systm.h>
44 44
45#include <arm/allwinner/awin_reg.h> 45#include <arm/allwinner/awin_reg.h>
46#include <arm/allwinner/awin_var.h> 46#include <arm/allwinner/awin_var.h>
47 47
48#include <dev/usb/usb.h> 48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h> 49#include <dev/usb/usbdi.h>
50#include <dev/usb/usbdivar.h> 50#include <dev/usb/usbdivar.h>
@@ -226,53 +226,53 @@ ehci_awinusb_attach(device_t parent, dev @@ -226,53 +226,53 @@ ehci_awinusb_attach(device_t parent, dev
226 irq); 226 irq);
227 return; 227 return;
228 } 228 }
229 aprint_normal_dev(self, "interrupting on irq %d\n", irq); 229 aprint_normal_dev(self, "interrupting on irq %d\n", irq);
230} 230}
231#endif /* NEHCI > 0 */ 231#endif /* NEHCI > 0 */
232 232
233static void 233static void
234awin_usb_phy_write(struct awinusb_softc *usbsc, u_int bit_addr, u_int bits, 234awin_usb_phy_write(struct awinusb_softc *usbsc, u_int bit_addr, u_int bits,
235 u_int len) 235 u_int len)
236{ 236{
237 bus_space_tag_t bst = usbsc->usbsc_bst; 237 bus_space_tag_t bst = usbsc->usbsc_bst;
238 bus_space_handle_t bsh = usbsc->usbsc_usb0_phy_csr_bsh; 238 bus_space_handle_t bsh = usbsc->usbsc_usb0_phy_csr_bsh;
239 uint32_t clk = AWIN_USB0_PHY_CSR_CLK0 << usbsc->usbsc_number; 239 uint32_t clk = AWIN_USB0_PHY_CTL_CLK0 << usbsc->usbsc_number;
240 240
241 uint32_t v = bus_space_read_4(bst, bsh, 0); 241 uint32_t v = bus_space_read_4(bst, bsh, 0);
242 242
243 KASSERT((v & AWIN_USB0_PHY_CSR_CLK0) == 0); 243 KASSERT((v & AWIN_USB0_PHY_CTL_CLK0) == 0);
244 KASSERT((v & AWIN_USB0_PHY_CSR_CLK1) == 0); 244 KASSERT((v & AWIN_USB0_PHY_CTL_CLK1) == 0);
245 KASSERT((v & AWIN_USB0_PHY_CSR_CLK2) == 0); 245 KASSERT((v & AWIN_USB0_PHY_CTL_CLK2) == 0);
246 246
247 v &= ~AWIN_USB0_PHY_CSR_ADDR; 247 v &= ~AWIN_USB0_PHY_CTL_ADDR;
248 v &= ~AWIN_USB0_PHY_CSR_DAT; 248 v &= ~AWIN_USB0_PHY_CTL_DAT;
249 249
250 v |= __SHIFTIN(bit_addr, AWIN_USB0_PHY_CSR_ADDR); 250 v |= __SHIFTIN(bit_addr, AWIN_USB0_PHY_CTL_ADDR);
251 251
252 /* 252 /*
253 * Bitbang the data to the phy, bit by bit, incrementing bit address 253 * Bitbang the data to the phy, bit by bit, incrementing bit address
254 * as we go. 254 * as we go.
255 */ 255 */
256 for (; len > 0; bit_addr++, bits >>= 1, len--) { 256 for (; len > 0; bit_addr++, bits >>= 1, len--) {
257 v |= __SHIFTIN(bits & 1, AWIN_USB0_PHY_CSR_DAT); 257 v |= __SHIFTIN(bits & 1, AWIN_USB0_PHY_CTL_DAT);
258 bus_space_write_4(bst, bsh, 0, v); 258 bus_space_write_4(bst, bsh, 0, v);
259 delay(1); 259 delay(1);
260 bus_space_write_4(bst, bsh, 0, v | clk); 260 bus_space_write_4(bst, bsh, 0, v | clk);
261 delay(1); 261 delay(1);
262 bus_space_write_4(bst, bsh, 0, v); 262 bus_space_write_4(bst, bsh, 0, v);
263 delay(1); 263 delay(1);
264 v += __LOWEST_SET_BIT(AWIN_USB0_PHY_CSR_ADDR); 264 v += __LOWEST_SET_BIT(AWIN_USB0_PHY_CTL_ADDR);
265 v &= ~AWIN_USB0_PHY_CSR_DAT; 265 v &= ~AWIN_USB0_PHY_CTL_DAT;
266 } 266 }
267} 267}
268 268
269static int awinusb_match(device_t, cfdata_t, void *); 269static int awinusb_match(device_t, cfdata_t, void *);
270static void awinusb_attach(device_t, device_t, void *); 270static void awinusb_attach(device_t, device_t, void *);
271 271
272CFATTACH_DECL_NEW(awin_usb, sizeof(struct awinusb_softc), 272CFATTACH_DECL_NEW(awin_usb, sizeof(struct awinusb_softc),
273 awinusb_match, awinusb_attach, NULL, NULL); 273 awinusb_match, awinusb_attach, NULL, NULL);
274 274
275static int awinusb_ports; 275static int awinusb_ports;
276 276
277static const char awinusb_drvpin_names[2][8] = { "usb1drv", "usb2drv" }; 277static const char awinusb_drvpin_names[2][8] = { "usb1drv", "usb2drv" };
278static const bus_size_t awinusb_dram_hpcr_regs[2] = { 278static const bus_size_t awinusb_dram_hpcr_regs[2] = {
@@ -325,27 +325,27 @@ awinusb_attach(device_t parent, device_t @@ -325,27 +325,27 @@ awinusb_attach(device_t parent, device_t
325 awinusb_ports |= __BIT(loc->loc_port); 325 awinusb_ports |= __BIT(loc->loc_port);
326 326
327 usbsc->usbsc_bst = aio->aio_core_bst; 327 usbsc->usbsc_bst = aio->aio_core_bst;
328 usbsc->usbsc_dmat = aio->aio_dmat; 328 usbsc->usbsc_dmat = aio->aio_dmat;
329 usbsc->usbsc_number = loc->loc_port + 1; 329 usbsc->usbsc_number = loc->loc_port + 1;
330 330
331 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh, 331 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh,
332 loc->loc_offset + AWIN_EHCI_OFFSET, AWIN_EHCI_SIZE, 332 loc->loc_offset + AWIN_EHCI_OFFSET, AWIN_EHCI_SIZE,
333 &usbsc->usbsc_ehci_bsh); 333 &usbsc->usbsc_ehci_bsh);
334 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh, 334 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh,
335 loc->loc_offset + AWIN_OHCI_OFFSET, AWIN_OHCI_SIZE, 335 loc->loc_offset + AWIN_OHCI_OFFSET, AWIN_OHCI_SIZE,
336 &usbsc->usbsc_ohci_bsh); 336 &usbsc->usbsc_ohci_bsh);
337 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh, 337 bus_space_subregion(usbsc->usbsc_bst, aio->aio_core_bsh,
338 AWIN_USB0_OFFSET + AWIN_USB0_PHY_CSR_REG, 4, 338 AWIN_USB0_OFFSET + AWIN_USB0_PHY_CTL_REG, 4,
339 &usbsc->usbsc_usb0_phy_csr_bsh); 339 &usbsc->usbsc_usb0_phy_csr_bsh);
340 340
341 aprint_naive("\n"); 341 aprint_naive("\n");
342 aprint_normal("\n"); 342 aprint_normal("\n");
343 343
344 /* 344 /*
345 * Access to the USB phy is off USB0 so make sure it's on. 345 * Access to the USB phy is off USB0 so make sure it's on.
346 */ 346 */
347 awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh, 347 awin_reg_set_clear(usbsc->usbsc_bst, aio->aio_ccm_bsh,
348 AWIN_AHB_GATING0_REG, 348 AWIN_AHB_GATING0_REG,
349 AWIN_AHB_GATING0_USB0 | awinusb_ahb_gating[loc->loc_port], 0); 349 AWIN_AHB_GATING0_USB0 | awinusb_ahb_gating[loc->loc_port], 0);
350 350
351 351