Sun Sep 14 09:32:11 2014 UTC ()
fix some more registers


(jmcneill)
diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/awin_otgreg.h
cvs diff -r1.2 -r1.3 src/sys/arch/arm/allwinner/Attic/awin_otgreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_otgreg.h 2014/09/13 17:48:52 1.2
+++ src/sys/arch/arm/allwinner/Attic/awin_otgreg.h 2014/09/14 09:32:11 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: awin_otgreg.h,v 1.2 2014/09/13 17:48:52 jmcneill Exp $ */ 1/* $NetBSD: awin_otgreg.h,v 1.3 2014/09/14 09:32:11 jmcneill Exp $ */
2/* FreeBSD: head/sys/dev/usb/controller/musb_otg.h 267122 2014-06-05 18:23:51Z hselasky */ 2/* FreeBSD: head/sys/dev/usb/controller/musb_otg.h 267122 2014-06-05 18:23:51Z hselasky */
3/*- 3/*-
4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
@@ -268,27 +268,27 @@ @@ -268,27 +268,27 @@
268 268
269#if 0 269#if 0
270#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n)) 270#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n))
271#define MUSB2_REG_RXDBDIS 0x0340 271#define MUSB2_REG_RXDBDIS 0x0340
272#define MUSB2_REG_TXDBDIS 0x0342 272#define MUSB2_REG_TXDBDIS 0x0342
273#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */ 273#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */
274 274
275#define MUSB2_REG_CHIRPTO 0x0344 275#define MUSB2_REG_CHIRPTO 0x0344
276#define MUSB2_REG_HSRESUM 0x0346 276#define MUSB2_REG_HSRESUM 0x0346
277#endif 277#endif
278 278
279/* Host Mode only registers */ 279/* Host Mode only registers */
280 280
281#define MUSB2_REG_TXFADDR(n) (0x0098 + (8*(n))) 281#define MUSB2_REG_TXFADDR(n) 0x0098
282#define MUSB2_REG_TXHADDR(n) (0x009a + (8*(n))) 282#define MUSB2_REG_TXHADDR(n) 0x009a
283#define MUSB2_REG_TXHUBPORT(n) (0x009b + (8*(n))) 283#define MUSB2_REG_TXHUBPORT(n) 0x009b
284#define MUSB2_REG_RXFADDR(n) (0x009c + (8*(n))) 284#define MUSB2_REG_RXFADDR(n) 0x009c
285#define MUSB2_REG_RXHADDR(n) (0x009e + (8*(n))) 285#define MUSB2_REG_RXHADDR(n) 0x009e
286#define MUSB2_REG_RXHUBPORT(n) (0x009f + (8*(n))) 286#define MUSB2_REG_RXHUBPORT(n) 0x009f
287 287
288#define MUSB2_EP_MAX 16 /* maximum number of endpoints */ 288#define MUSB2_EP_MAX 16 /* maximum number of endpoints */
289 289
290#define MUSB2_REG_AWIN_VEND0 0x0043 290#define MUSB2_REG_AWIN_VEND0 0x0043
291#define MUSB2_REG_AWIN_VEND1 0x007d 291#define MUSB2_REG_AWIN_VEND1 0x007d
292#define MUSB2_REG_AWIN_VEND3 0x007e 292#define MUSB2_REG_AWIN_VEND3 0x007e
293 293
294#endif /* _MUSB2_OTG_H_ */ 294#endif /* _MUSB2_OTG_H_ */