Sun Oct 19 13:15:23 2014 UTC ()
only set PR bit in frame filter if IFF_PROMISC is set, and set PM bit if IFF_ALLMULTI is set


(jmcneill)
diff -r1.12 -r1.13 src/sys/dev/ic/dwc_gmac.c
cvs diff -r1.12 -r1.13 src/sys/dev/ic/dwc_gmac.c (expand / switch to unified diff)

--- src/sys/dev/ic/dwc_gmac.c 2014/10/19 13:04:24 1.12
+++ src/sys/dev/ic/dwc_gmac.c 2014/10/19 13:15:23 1.13
@@ -29,27 +29,27 @@ @@ -29,27 +29,27 @@
29 29
30/* 30/*
31 * This driver supports the Synopsis Designware GMAC core, as found 31 * This driver supports the Synopsis Designware GMAC core, as found
32 * on Allwinner A20 cores and others. 32 * on Allwinner A20 cores and others.
33 * 33 *
34 * Real documentation seems to not be available, the marketing product 34 * Real documentation seems to not be available, the marketing product
35 * documents could be found here: 35 * documents could be found here:
36 * 36 *
37 * http://www.synopsys.com/dw/ipdir.php?ds=dwc_ether_mac10_100_1000_unive 37 * http://www.synopsys.com/dw/ipdir.php?ds=dwc_ether_mac10_100_1000_unive
38 */ 38 */
39 39
40#include <sys/cdefs.h> 40#include <sys/cdefs.h>
41 41
42__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.12 2014/10/19 13:04:24 jmcneill Exp $"); 42__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.13 2014/10/19 13:15:23 jmcneill Exp $");
43 43
44/* #define DWC_GMAC_DEBUG 1 */ 44/* #define DWC_GMAC_DEBUG 1 */
45 45
46#include "opt_inet.h" 46#include "opt_inet.h"
47 47
48#include <sys/param.h> 48#include <sys/param.h>
49#include <sys/bus.h> 49#include <sys/bus.h>
50#include <sys/device.h> 50#include <sys/device.h>
51#include <sys/intr.h> 51#include <sys/intr.h>
52#include <sys/systm.h> 52#include <sys/systm.h>
53#include <sys/sockio.h> 53#include <sys/sockio.h>
54 54
55#include <net/if.h> 55#include <net/if.h>
@@ -680,46 +680,51 @@ dwc_gmac_miibus_statchg(struct ifnet *if @@ -680,46 +680,51 @@ dwc_gmac_miibus_statchg(struct ifnet *if
680#ifdef DWC_GMAC_DEBUG 680#ifdef DWC_GMAC_DEBUG
681 aprint_normal_dev(sc->sc_dev, 681 aprint_normal_dev(sc->sc_dev,
682 "setting MAC conf register: %08x\n", conf); 682 "setting MAC conf register: %08x\n", conf);
683#endif 683#endif
684 684
685 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 685 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
686 AWIN_GMAC_MAC_CONF, conf); 686 AWIN_GMAC_MAC_CONF, conf);
687} 687}
688 688
689static int 689static int
690dwc_gmac_init(struct ifnet *ifp) 690dwc_gmac_init(struct ifnet *ifp)
691{ 691{
692 struct dwc_gmac_softc *sc = ifp->if_softc; 692 struct dwc_gmac_softc *sc = ifp->if_softc;
 693 uint32_t ffilt;
693 694
694 if (ifp->if_flags & IFF_RUNNING) 695 if (ifp->if_flags & IFF_RUNNING)
695 return 0; 696 return 0;
696 697
697 dwc_gmac_stop(ifp, 0); 698 dwc_gmac_stop(ifp, 0);
698 699
699 /* 700 /*
700 * Configure DMA burst/transfer mode and RX/TX priorities. 701 * Configure DMA burst/transfer mode and RX/TX priorities.
701 * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented. 702 * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
702 */ 703 */
703 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE, 704 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
704 GMAC_BUSMODE_FIXEDBURST | 705 GMAC_BUSMODE_FIXEDBURST |
705 __SHIFTIN(GMAC_BUSMODE_PRIORXTX_41, GMAC_BUSMODE_PRIORXTX) | 706 __SHIFTIN(GMAC_BUSMODE_PRIORXTX_41, GMAC_BUSMODE_PRIORXTX) |
706 __SHIFTIN(8, GMCA_BUSMODE_PBL)); 707 __SHIFTIN(8, GMCA_BUSMODE_PBL));
707 708
708 /* 709 /*
709 * Set up address filter (XXX for testing only: promiscous) 710 * Set up address filter
710 */ 711 */
711 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, 712 ffilt = 0;
712 AWIN_GMAC_MAC_FFILT_PR); 713 if (ifp->if_flags & IFF_PROMISC)
 714 ffilt |= AWIN_GMAC_MAC_FFILT_PR;
 715 else if (ifp->if_flags & IFF_ALLMULTI)
 716 ffilt |= AWIN_GMAC_MAC_FFILT_PM;
 717 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
713 718
714 /* 719 /*
715 * Set up dma pointer for RX and TX ring 720 * Set up dma pointer for RX and TX ring
716 */ 721 */
717 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR, 722 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
718 sc->sc_rxq.r_physaddr); 723 sc->sc_rxq.r_physaddr);
719 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR, 724 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
720 sc->sc_txq.t_physaddr); 725 sc->sc_txq.t_physaddr);
721 726
722 /* 727 /*
723 * Start RX/TX part 728 * Start RX/TX part
724 */ 729 */
725 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 730 bus_space_write_4(sc->sc_bst, sc->sc_bsh,