Thu Oct 30 10:45:17 2014 UTC ()
Part of break-before-make is to dsb after the TLB invalidation. Do it in
tlb_invalidate_addr


(skrll)
diff -r1.6 -r1.7 src/sys/arch/arm/arm32/arm32_tlb.c
cvs diff -r1.6 -r1.7 src/sys/arch/arm/arm32/arm32_tlb.c (expand / switch to unified diff)

--- src/sys/arch/arm/arm32/arm32_tlb.c 2014/10/30 10:38:57 1.6
+++ src/sys/arch/arm/arm32/arm32_tlb.c 2014/10/30 10:45:17 1.7
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include "opt_multiprocessor.h" 30#include "opt_multiprocessor.h"
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.6 2014/10/30 10:38:57 skrll Exp $"); 33__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.7 2014/10/30 10:45:17 skrll Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/types.h> 36#include <sys/types.h>
37 37
38#include <uvm/uvm.h> 38#include <uvm/uvm.h>
39 39
40#include <arm/locore.h> 40#include <arm/locore.h>
41 41
42bool arm_has_tlbiasid_p; // CPU supports TLBIASID system coprocessor op 42bool arm_has_tlbiasid_p; // CPU supports TLBIASID system coprocessor op
43 43
44tlb_asid_t 44tlb_asid_t
45tlb_get_asid(void) 45tlb_get_asid(void)
46{ 46{
@@ -112,26 +112,27 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_ @@ -112,26 +112,27 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_
112void 112void
113tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid) 113tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
114{ 114{
115 arm_dsb(); 115 arm_dsb();
116 va = trunc_page(va) | asid; 116 va = trunc_page(va) | asid;
117 for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) { 117 for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
118#ifdef MULTIPROCESSOR 118#ifdef MULTIPROCESSOR
119 armreg_tlbimvais_write(va); 119 armreg_tlbimvais_write(va);
120#else 120#else
121 armreg_tlbimva_write(va); 121 armreg_tlbimva_write(va);
122#endif 122#endif
123 //armreg_tlbiall_write(asid); 123 //armreg_tlbiall_write(asid);
124 } 124 }
 125 arm_dsb();
125 arm_isb(); 126 arm_isb();
126} 127}
127 128
128bool 129bool
129tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p) 130tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
130{ 131{
131 tlb_invalidate_addr(va, asid); 132 tlb_invalidate_addr(va, asid);
132 return true; 133 return true;
133} 134}
134 135
135#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5) 136#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
136static u_int 137static u_int
137tlb_cortex_a5_record_asids(u_long *mapp) 138tlb_cortex_a5_record_asids(u_long *mapp)