 @@ -1066,26 +1066,30 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_CLK_SRC_SEL		__BITS(25,24)
 #define AWIN_CLK_SRC_SEL_OSC24M		0
 #define AWIN_CLK_SRC_SEL_PLL6		1
 #define AWIN_CLK_SRC_SEL_PLL5		2
 #define AWIN_CLK_SRC_SEL_LOSC		3
 #define AWIN_CLK_SRC_SEL_KEYPAD_LOSC	2
 #define AWIN_CLK_SRC_SEL_SATA_PLL6	0	/* 100 MHz */
 #define AWIN_CLK_SRC_SEL_SATA_EXT	1
 #define AWIN_CLK_SRC_SEL_DE_PLL3	0
 #define AWIN_CLK_SRC_SEL_DE_PLL7	1
 #define AWIN_CLK_SRC_SEL_DE_PLL5	2
 #define AWIN_CLK_SRC_SEL_CIR_LOSC	0
 #define AWIN_CLK_SRC_SEL_CIR_HOSC	1
 #define AWIN_CLK_SRC_SEL_MP_PLL3	0
 #define AWIN_CLK_SRC_SEL_MP_PLL7	1
 #define AWIN_CLK_SRC_SEL_MP_PLL9	2
 #define AWIN_CLK_SRC_SEL_MP_PLL10	3
 #define AWIN_CLK_DIV_RATIO_N		__BITS(17,16)
 #define AWIN_CLK_DIV_RATIO_M		__BITS(3,0)
 #define AWIN_ISS_CLK_SRC_SEL		__BITS(17,16)
 #define AWIN_USB_CLK_USBPHY_ENABLE	__BIT(8)
 #define AWIN_USB_CLK_OHCI1_ENABLE	__BIT(7)
 #define AWIN_USB_CLK_OHCI0_ENABLE	__BIT(6)
 #define AWIN_USB_CLK_PHY2_ENABLE	__BIT(2)
 #define AWIN_USB_CLK_PHY1_ENABLE	__BIT(1)
 #define AWIN_USB_CLK_PHY0_ENABLE	__BIT(0)
 #define AWIN_DRAM_CLK_ACE_DCLK_ENABLE	__BIT(29)
 @@ -1131,28 +1135,33 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL3_2X 2
 #define AWIN_LCDx_CHx_CLK_SRC_SEL_PLL6_2 3
 #define AWIN_LCDx_CH1_SCLK1_GATING	__BIT(15)
 #define AWIN_LCDx_CH1_SCLK1_SRC_SEL	__BIT(11)
 #define AWIN_LCDx_CH1_CLK_DIV_RATIO_M	__BITS(3,0)
 #define AWIN_HDMI_CLK_SRC_SEL		__BITS(25,24)
 #define AWIN_HDMI_CLK_SRC_SEL_PLL3	0
 #define AWIN_HDMI_CLK_SRC_SEL_PLL7	1
 #define AWIN_HDMI_CLK_SRC_SEL_PLL3_2X	2
 #define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X	3
 #define AWIN_HDMI_CLK_DIV_RATIO_M	__BITS(3,0)
 #define AWIN_SD_CLK_SRC_SEL		__BITS(25,24)
 #define AWIN_SD_CLK_SRC_SEL_OSC24M	0
 #define AWIN_SD_CLK_SRC_SEL_PLL6	1
 #define AWIN_SD_CLK_PHASE_CTR		__BITS(22,20)
 #define AWIN_SD_CLK_DIV_RATIO_N		__BITS(17,16)
 #define AWIN_SD_CLK_OUTPUT_PHASE_CTR	__BITS(10,8)
 #define AWIN_SD_CLK_DIV_RATIO_M		__BITS(3,0)
 #define AWIN_CLK_OUT_ENABLE		__BIT(31)
 #define AWIN_CLK_OUT_SRC_SEL		__BITS(25,24)
 #define AWIN_CLK_OUT_SRC_SEL_32K	0
 #define AWIN_CLK_OUT_SRC_SEL_LOSC	1
 #define AWIN_CLK_OUT_SRC_SEL_OSC24M	2
 #define AWIN_CLK_OUT_SRC_FACTOR_N	__BITS(21,20)
 #define AWIN_CLK_OUT_SRC_FACTOR_M	__BITS(12,8)
 /* USB device offsets */
 #define AWIN_USB0_PHY_CSR_REG		0x0400
 #define AWIN_USB0_PHY_CTL_REG		0x0404
 #define AWIN_EHCI_OFFSET		0x0000
 @@ -2014,27 +2023,27 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOWRITE 2
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOWRITE 3
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD	4
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOREAD	5
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_EOEDDCREAD 6
 #define AWIN_HDMI_DDC_COMMAND_ACCESS_CMD_IOEDDCREAD 7
 #define AWIN_HDMI_DDC_CLOCK_M		__BITS(6,3)
 #define AWIN_HDMI_DDC_CLOCK_N		__BITS(2,0)
 /* Mixer processor */
 #define AWIN_MP_CTL_REG				0x0000
 #define AWIN_MP_STS_REG				0x0004
-#define AWIN_MP_IDMAGBLCTL_REG			0x0008
+#define AWIN_MP_IDMAGLBCTL_REG			0x0008
 #define AWIN_MP_IDMA_H4ADD_REG			0x000C
 #define AWIN_MP_IDMA_L32ADD_REG(n)		(0x0010 + ((n) * 4))
 #define AWIN_MP_IDMALINEWIDTH_REG(n)		(0x0020 + ((n) * 4))
 #define AWIN_MP_IDMASIZE_REG(n)			(0x0030 + ((n) * 4))
 #define AWIN_MP_IDMACOOR_REG(n)			(0x0040 + ((n) * 4))
 #define AWIN_MP_IDMASET_REG(n)			(0x0050 + ((n) * 4))
 #define AWIN_MP_IDMAFILLCOLOR_REG(n)		(0x0060 + ((n) * 4))
 #define AWIN_MP_CSC0CTL_REG			0x0074
 #define AWIN_MP_CSC1CTL_REG			0x0078
 #define AWIN_MP_SCACTL_REG			0x0080
 #define AWIN_MP_SCAOUTSIZE_REG			0x0084
 #define AWIN_MP_SCAHORFCT_REG			0x0088
 #define AWIN_MP_SCAVERFCT_REG			0x008c
 @@ -2101,29 +2110,29 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_MP_IDMACOOR_YCOOR			__BITS(31,16)
 #define AWIN_MP_IDMACOOR_XCOOR			__BITS(15,0)
 #define AWIN_MP_IDMASET_IDMA_GLBALPHA		__BITS(31,24)
 #define AWIN_MP_IDMASET_MBFMT			__BIT(22)
 #define AWIN_MP_IDMASET_MBSIZE			__BITS(21,20)
 #define AWIN_MP_IDMASET_MBSIZE_16X16		0
 #define AWIN_MP_IDMASET_MBSIZE_32X32		1
 #define AWIN_MP_IDMASET_MBSIZE_64X64		2
 #define AWIN_MP_IDMASET_MBSIZE_128X128		3
 #define AWIN_MP_IDMASET_IDMA_FCMODEN		__BIT(16)
 #define AWIN_MP_IDMASET_IDMA_PS			__BITS(15,12)
 #define AWIN_MP_IDMASET_IDMA_FMT		__BITS(11,8)
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB888	0
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB8888	0
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB444	1
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB4444	1
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB155	2
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB1555	2
 #define AWIN_MP_IDMASET_IDMA_FMT_RGB565		3
 #define AWIN_MP_IDMASET_IDMA_FMT_IYUV422	4
 #define AWIN_MP_IDMASET_IDMA_FMT_UV88		5
 #define AWIN_MP_IDMASET_IDMA_FMT_Y8		6
 #define AWIN_MP_IDMASET_IDMA_FMT_8BPP_MP	7
 #define AWIN_MP_IDMASET_IDMA_FMT_4BPP_MP	8
 #define AWIN_MP_IDMASET_IDMA_FMT_2BPP_MP	9
 #define AWIN_MP_IDMASET_IDMA_FMT_1BPP_MP	10
 #define AWIN_MP_IDMASET_IDMA_ROPMIRCTL		__BITS(7,4)
 #define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_NORMAL	0
 #define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_X	1
 #define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_Y	2
 #define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_XY	3
 @@ -2287,26 +2296,28 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_A31_PLL2_CFG_PLL_SDM_EN	__BIT(24)
 #define AWIN_A31_PLL2_CFG_POSTDIV_P	__BITS(19,16)
 #define AWIN_A31_PLL2_CFG_FACTOR_N	__BITS(14,8)
 #define AWIN_A31_PLL2_CFG_PREVDIV_M	__BITS(4,0)
 #define AWIN_A31_PLL3_CFG_MODE		__BIT(30)
 #define AWIN_A31_PLL3_CFG_LOCK		__BIT(28)
 #define AWIN_A31_PLL3_CFG_FRAC_CLK_OUT	__BIT(25)
 #define AWIN_A31_PLL3_CFG_MODE_SEL	__BIT(24)
 #define AWIN_A31_PLL3_CFG_SDM_EN	__BIT(20)
 #define AWIN_A31_PLL3_CFG_FACTOR_N	__BITS(14,8)
 #define AWIN_A31_PLL3_CFG_PREDIV_M	__BITS(3,0)
 #define AWIN_A31_PLL6_CFG_LOCK		__BIT(28)
 #define AWIN_A31_PLL7_CFG_MODE		__BIT(30)
 #define AWIN_A31_PLL7_CFG_LOCK		__BIT(28)
 #define AWIN_A31_PLL7_CFG_FRAC_CLK_OUT	__BIT(25)
 #define AWIN_A31_PLL7_CFG_MODE_SEL	__BIT(24)
 #define AWIN_A31_PLL7_CFG_SDM_EN	__BIT(20)
 #define AWIN_A31_PLL7_CFG_FACTOR_N	__BITS(14,8)
 #define AWIN_A31_PLL7_CFG_PREDIV_M	__BITS(3,0)
 #define AWIN_A31_PLL10_CFG_MODE		__BIT(30)
 #define AWIN_A31_PLL10_CFG_LOCK		__BIT(28)
 #define AWIN_A31_PLL10_CFG_FRAC_CLK_OUT	__BIT(25)
 #define AWIN_A31_PLL10_CFG_MODE_SEL	__BIT(24)
 #define AWIN_A31_PLL10_CFG_SDM_EN	__BIT(20)