Mon Dec 22 21:15:48 2014 UTC ()
Apply a fix, extracted from the UCB RISC-V gcc sources, for the (known)
problems with compiling atomics for the riscv64 target with gcc.  Remove
the now-unneeded workarounds for the 2 files in libasan that were formerly
failing to compile with the optimizer turned on.


(dennis)
diff -r1.1 -r1.2 src/external/gpl3/gcc/dist/gcc/config/riscv/sync.md
diff -r1.8 -r1.9 src/external/gpl3/gcc/lib/libasan/Makefile
cvs diff -r1.1 -r1.2 src/external/gpl3/gcc/dist/gcc/config/riscv/sync.md (expand / switch to unified diff)

--- src/external/gpl3/gcc/dist/gcc/config/riscv/sync.md 2014/09/19 17:20:29 1.1
+++ src/external/gpl3/gcc/dist/gcc/config/riscv/sync.md 2014/12/22 21:15:48 1.2
@@ -156,27 +156,27 @@ @@ -156,27 +156,27 @@
156}) 156})
157 157
158(define_expand "atomic_test_and_set" 158(define_expand "atomic_test_and_set"
159 [(match_operand:QI 0 "register_operand" "") ;; bool output 159 [(match_operand:QI 0 "register_operand" "") ;; bool output
160 (match_operand:QI 1 "memory_operand" "+YR") ;; memory 160 (match_operand:QI 1 "memory_operand" "+YR") ;; memory
161 (match_operand:SI 2 "const_int_operand" "")] ;; model 161 (match_operand:SI 2 "const_int_operand" "")] ;; model
162 "TARGET_ATOMIC" 162 "TARGET_ATOMIC"
163{ 163{
164 /* We have no QImode atomics, so use the address LSBs to form a mask, 164 /* We have no QImode atomics, so use the address LSBs to form a mask,
165 then use an aligned SImode atomic. */ 165 then use an aligned SImode atomic. */
166 rtx result = operands[0]; 166 rtx result = operands[0];
167 rtx mem = operands[1]; 167 rtx mem = operands[1];
168 rtx model = operands[2]; 168 rtx model = operands[2];
169 rtx addr = XEXP (mem, 0); 169 rtx addr = force_reg (Pmode, XEXP (mem, 0));
170 170
171 rtx aligned_addr = gen_reg_rtx (Pmode); 171 rtx aligned_addr = gen_reg_rtx (Pmode);
172 emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4))); 172 emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));
173 173
174 rtx aligned_mem = change_address (mem, SImode, aligned_addr); 174 rtx aligned_mem = change_address (mem, SImode, aligned_addr);
175 set_mem_alias_set (aligned_mem, 0); 175 set_mem_alias_set (aligned_mem, 0);
176 176
177 rtx offset = gen_reg_rtx (SImode); 177 rtx offset = gen_reg_rtx (SImode);
178 emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr), 178 emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
179 GEN_INT (3))); 179 GEN_INT (3)));
180 180
181 rtx tmp = gen_reg_rtx (SImode); 181 rtx tmp = gen_reg_rtx (SImode);
182 emit_move_insn (tmp, GEN_INT (1)); 182 emit_move_insn (tmp, GEN_INT (1));
cvs diff -r1.8 -r1.9 src/external/gpl3/gcc/lib/libasan/Makefile (expand / switch to unified diff)

--- src/external/gpl3/gcc/lib/libasan/Makefile 2014/12/02 03:20:39 1.8
+++ src/external/gpl3/gcc/lib/libasan/Makefile 2014/12/22 21:15:48 1.9
@@ -46,20 +46,14 @@ SANITIZER_SRCS= \ @@ -46,20 +46,14 @@ SANITIZER_SRCS= \
46 sanitizer_win.cc 46 sanitizer_win.cc
47 47
48# The linux build does this to avoid preinit sections on shared libraries 48# The linux build does this to avoid preinit sections on shared libraries
49CSHLIBFLAGS+= -DPIC 49CSHLIBFLAGS+= -DPIC
50 50
51LIB= asan 51LIB= asan
52SRCS= ${ASAN_SRCS} ${INTERCEPTION_SRCS} ${SANITIZER_SRCS} 52SRCS= ${ASAN_SRCS} ${INTERCEPTION_SRCS} ${SANITIZER_SRCS}
53CPPFLAGS+=-I${ASAN}/include -I${ASAN} 53CPPFLAGS+=-I${ASAN}/include -I${ASAN}
54CPPFLAGS.sanitizer_netbsd.cc+=-I${GCCDIST}/gcc/ginclude 54CPPFLAGS.sanitizer_netbsd.cc+=-I${GCCDIST}/gcc/ginclude
55 55
56LIBDPLIBS+= stdc++ ${.CURDIR}/../libstdc++-v3 56LIBDPLIBS+= stdc++ ${.CURDIR}/../libstdc++-v3
57LIBDPLIBS+= pthread ${.CURDIR}/../../../../../lib/libpthread 57LIBDPLIBS+= pthread ${.CURDIR}/../../../../../lib/libpthread
58 58
59# Work around riscv compiler bugs in (at least) gcc 4.8.3 
60.if ${MACHINE_ARCH} == "riscv64" 
61COPTS.asan_allocator2.cc += -O0 
62COPTS.sanitizer_netbsd.cc += -O0 
63.endif 
64 
65.include <bsd.lib.mk> 59.include <bsd.lib.mk>