Tue Dec 30 21:24:36 2014 UTC ()
do armv7_dcache_inv_all before cortex_mpstart on secondaries


(jmcneill)
diff -r1.3 -r1.4 src/sys/arch/evbarm/rockchip/rockchip_start.S
cvs diff -r1.3 -r1.4 src/sys/arch/evbarm/rockchip/Attic/rockchip_start.S (expand / switch to unified diff)

--- src/sys/arch/evbarm/rockchip/Attic/rockchip_start.S 2014/12/28 21:34:33 1.3
+++ src/sys/arch/evbarm/rockchip/Attic/rockchip_start.S 2014/12/30 21:24:36 1.4
@@ -33,27 +33,27 @@ @@ -33,27 +33,27 @@
33#include "opt_cputypes.h" 33#include "opt_cputypes.h"
34#include "opt_multiprocessor.h" 34#include "opt_multiprocessor.h"
35#include "opt_arm_debug.h" 35#include "opt_arm_debug.h"
36 36
37#include <arm/asm.h> 37#include <arm/asm.h>
38#include <arm/armreg.h> 38#include <arm/armreg.h>
39#include "assym.h" 39#include "assym.h"
40 40
41#include <arm/rockchip/rockchip_reg.h> 41#include <arm/rockchip/rockchip_reg.h>
42#include <evbarm/rockchip/platform.h>  42#include <evbarm/rockchip/platform.h>
43 43
44#include <arm/cortex/scu_reg.h> 44#include <arm/cortex/scu_reg.h>
45 45
46RCSID("$NetBSD: rockchip_start.S,v 1.3 2014/12/28 21:34:33 jmcneill Exp $") 46RCSID("$NetBSD: rockchip_start.S,v 1.4 2014/12/30 21:24:36 jmcneill Exp $")
47 47
48#if defined(VERBOSE_INIT_ARM) 48#if defined(VERBOSE_INIT_ARM)
49#define XPUTC(n) mov r0, n; bl xputc 49#define XPUTC(n) mov r0, n; bl xputc
50#if KERNEL_BASE_VOFFSET == 0 50#if KERNEL_BASE_VOFFSET == 0
51#define XPUTC2(n) mov r0, n; bl xputc 51#define XPUTC2(n) mov r0, n; bl xputc
52#else 52#else
53#define XPUTC2(n) mov r0, n; blx r11 53#define XPUTC2(n) mov r0, n; blx r11
54#endif 54#endif
55#ifdef __ARMEB__ 55#ifdef __ARMEB__
56#define COM_BSWAP 56#define COM_BSWAP
57#endif 57#endif
58#define COM_MULT 4 58#define COM_MULT 4
59#define XPUTC_COM 1 59#define XPUTC_COM 1
@@ -170,45 +170,45 @@ _C_LABEL(rockchip_start): @@ -170,45 +170,45 @@ _C_LABEL(rockchip_start):
170#endif 170#endif
171 171
172#include <arm/cortex/a9_mpsubr.S> 172#include <arm/cortex/a9_mpsubr.S>
173 173
174#define PMU_PWRDN_REG 0x0008 174#define PMU_PWRDN_REG 0x0008
175#define PMU_PWRDN_SCU __BIT(4) 175#define PMU_PWRDN_SCU __BIT(4)
176 176
177#if defined(MULTIPROCESSOR) 177#if defined(MULTIPROCESSOR)
178#ifndef KERNEL_BASES_EQUAL 178#ifndef KERNEL_BASES_EQUAL
179 .pushsection .text,"ax",%progbits 179 .pushsection .text,"ax",%progbits
180#endif 180#endif
181rockchip_mptramp: 181rockchip_mptramp:
182 ldr pc, 1f 182 ldr pc, 1f
183.global cortex_mpstart_vec 183.global rockchip_mpstart_vec
184cortex_mpstart_vec: 184rockchip_mpstart_vec:
1851: .space 4 1851: .space 4
186 186
187rockchip_mpinit: 187rockchip_mpinit:
188 mov r4, lr 188 mov r4, lr
189 /* r5: SCU, r6: PMU, r7: SRAM */ 189 /* r5: SCU, r6: PMU, r7: SRAM */
190 movw r5, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET) 190 movw r5, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
191 movt r5, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET) 191 movt r5, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
192 movw r6, #:lower16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET) 192 movw r6, #:lower16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
193 movt r6, #:upper16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET) 193 movt r6, #:upper16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
194 movw r7, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET) 194 movw r7, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
195 movt r7, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET) 195 movt r7, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
196 196
197 /* Set where the other CPU(s) are going to execute */ 197 /* Set where the other CPU(s) are going to execute */
198 XPUTC2(#118) 198 XPUTC2(#118)
199 movw r1, #:lower16:cortex_mpstart 199 movw r1, #:lower16:rockchip_mpstart
200 movt r1, #:upper16:cortex_mpstart 200 movt r1, #:upper16:rockchip_mpstart
201 ldr r0, =cortex_mpstart_vec 201 ldr r0, =rockchip_mpstart_vec
202 str r1, [r0] 202 str r1, [r0]
203 ldr r0, =rockchip_mptramp 203 ldr r0, =rockchip_mptramp
204 mov r2, #0 204 mov r2, #0
2051: ldr r1, [r0, r2] 2051: ldr r1, [r0, r2]
206 str r1, [r7, r2] 206 str r1, [r7, r2]
207 add r2, r2, #4 207 add r2, r2, #4
208 cmp r2, #32 208 cmp r2, #32
209 blt 1b 209 blt 1b
210 dsb 210 dsb
211 211
212 /* Invalid SCU cache tags */ 212 /* Invalid SCU cache tags */
213 XPUTC2(#45) 213 XPUTC2(#45)
214 movw r1, #0xffff 214 movw r1, #0xffff
@@ -268,26 +268,37 @@ rockchip_mpinit: @@ -268,26 +268,37 @@ rockchip_mpinit:
268 ldr r0, [r2] 268 ldr r0, [r2]
269 cmp r0, r7 269 cmp r0, r7
270 beq .hatched 270 beq .hatched
271 subs r1, r1, #1 271 subs r1, r1, #1
272 bne 1b 272 bne 1b
273 273
274.hatched: 274.hatched:
275 bx r4 275 bx r4
276 276
277ASEND(rockchip_mpinit) 277ASEND(rockchip_mpinit)
278#ifndef KERNEL_BASES_EQUAL 278#ifndef KERNEL_BASES_EQUAL
279 .popsection 279 .popsection
280#endif 280#endif
 281
 282rockchip_mpstart:
 283 /* invalidate cache */
 284 movw ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
 285 movt ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
 286#ifndef KERNEL_BASES_EQUAL
 287 sub ip, ip, #KERNEL_BASE_VOFFSET
 288#endif
 289 blx ip
 290 b _C_LABEL(cortex_mpstart)
 291
281#endif /* MULTIPROCESSOR */ 292#endif /* MULTIPROCESSOR */
282 293
283.Lmmu_init_table: 294.Lmmu_init_table:
284 /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */ 295 /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
285 MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE, 296 MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
286 L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE) 297 L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
287 298
288#if KERNEL_BASE_VOFFSET != 0 299#if KERNEL_BASE_VOFFSET != 0
289 /* Map memory 1:1 VA to PA, write-back cacheable, shareable */ 300 /* Map memory 1:1 VA to PA, write-back cacheable, shareable */
290 MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET, 301 MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
291 KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE, 302 KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
292 L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE) 303 L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
293#endif 304#endif