 @@ -1,14 +1,14 @@
-/*	$NetBSD: identcpu.c,v 1.29.2.2 2012/05/07 16:37:19 riz Exp $	*/
+/*	$NetBSD: identcpu.c,v 1.29.2.3 2015/01/26 14:02:40 martin Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.29.2.2 2012/05/07 16:37:19 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.29.2.3 2015/01/26 14:02:40 martin Exp $");
 #include "opt_xen.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <machine/specialreg.h>
 #include <machine/pio.h>
 #include <machine/cpu.h>
 @@ -87,54 +87,143 @@ static const char cpu_vendor_names[][10]
 static const struct x86_cache_info *
 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
 	int i;
 	for (i = 0; cai[i].cai_desc != 0; i++) {
 		if (cai[i].cai_desc == desc)
 			return (&cai[i]);
+	}
 	return (NULL);
+}
 static void
 cpu_probe_intel_cache(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cai;
 	u_int descs[4];
 	int iterations, i, j;
 	uint8_t desc;
 	if (cpuid_level >= 2) {
 		/* Parse the cache info from `cpuid leaf 2', if we have it. */
 		x86_cpuid(2, descs);
 		iterations = descs[0] & 0xff;
 		while (iterations-- > 0) {
 			for (i = 0; i < 4; i++) {
 				if (descs[i] & 0x80000000)
 					continue;
 				for (j = 0; j < 4; j++) {
 					if (i == 0 && j == 0)
 						continue;
 					desc = (descs[i] >> (j * 8)) & 0xff;
 					if (desc == 0)
 						continue;
 					cai = cache_info_lookup(
 					    intel_cpuid_cache_info, desc);
 					if (cai != NULL) {
 						ci->ci_cinfo[cai->cai_index] =
 						    *cai;
+					}
+				}
+			}
+		}
+	}
 	if (cpuid_level >= 4) {
 		int type, level;
 		int ways, partitions, linesize, sets;
 		int caitype = -1;
 		int totalsize;
 		/* Parse the cache info from `cpuid leaf 4', if we have it. */
 		for (i = 0; ; i++) {
 			x86_cpuid2(4, i, descs);
 			type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
 			if (type == CPUID_DCP_CACHETYPE_N)
 				break;
 			level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
 			switch (level) {
 			case 1:
 				if (type == CPUID_DCP_CACHETYPE_I)
 					caitype = CAI_ICACHE;
 				else if (type == CPUID_DCP_CACHETYPE_D)
 					caitype = CAI_DCACHE;
 				else
 					caitype = -1;
 				break;
 			case 2:
 				if (type == CPUID_DCP_CACHETYPE_U)
 					caitype = CAI_L2CACHE;
 				else
 					caitype = -1;
 				break;
 			case 3:
 				if (type == CPUID_DCP_CACHETYPE_U)
 					caitype = CAI_L3CACHE;
 				else
 					caitype = -1;
 				break;
 			default:
 				caitype = -1;
 				break;
+			}
 			if (caitype == -1)
 				continue;
 			ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
 			partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
 			    + 1;
 			linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
 			    + 1;
 			sets = descs[2] + 1;
 			totalsize = ways * partitions * linesize * sets;
 			ci->ci_cinfo[caitype].cai_totalsize = totalsize;
 			ci->ci_cinfo[caitype].cai_associativity = ways;
 			ci->ci_cinfo[caitype].cai_linesize = linesize;
+		}
+	}
+}
 static void
 cpu_probe_intel(struct cpu_info *ci)
+{
 	if (cpu_vendor != CPUVENDOR_INTEL)
 		return;
 	cpu_probe_intel_cache(ci);
+}
 static void
 cpu_probe_amd_cache(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cp;
 	struct x86_cache_info *cai;
 	int family, model;
 	u_int descs[4];
 	u_int lfunc;
-	family = CPUID2FAMILY(ci->ci_signature);
+	family = CPUID_TO_FAMILY(ci->ci_signature);
-	model = CPUID2MODEL(ci->ci_signature);
+	model = CPUID_TO_MODEL(ci->ci_signature);
 	/*
 	 * K5 model 0 has none of this info.
 	 */
 	if (family == 5 && model == 0)
 		return;
 	/*
 	 * Get extended values for K8 and up.
 	 */
 	if (family == 0xf) {
 		family += CPUID2EXTFAMILY(ci->ci_signature);
 		model += CPUID2EXTMODEL(ci->ci_signature);
 	/*
 	 * Determine the largest extended function value.
 	 */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	/*
 	 * Determine L1 cache/TLB info.
 	 */
 	if (lfunc < 0x80000005) {
 		/* No L1 cache info available. */
 		return;
+	}
 @@ -238,52 +327,52 @@ cpu_probe_amd_cache(struct cpu_info *ci)
 	cai = &ci->ci_cinfo[CAI_L2_1GBITLB];
 	cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]);
 	cai->cai_linesize = (1 * 1024);
+}
 static void
 cpu_probe_k5(struct cpu_info *ci)
+{
 	int flag;
 	if (cpu_vendor != CPUVENDOR_AMD ||
-	    CPUID2FAMILY(ci->ci_signature) != 5)
+	    CPUID_TO_FAMILY(ci->ci_signature) != 5)
 		return;
-	if (CPUID2MODEL(ci->ci_signature) == 0) {
+	if (CPUID_TO_MODEL(ci->ci_signature) == 0) {
 		/*
 		 * According to the AMD Processor Recognition App Note,
 		 * the AMD-K5 Model 0 uses the wrong bit to indicate
 		 * support for global PTEs, instead using bit 9 (APIC)
 		 * rather than bit 13 (i.e. "0x200" vs. 0x2000".  Oops!).
 		 */
 		flag = ci->ci_feat_val[0];
 		if ((flag & CPUID_APIC) != 0)
 			flag = (flag & ~CPUID_APIC) | CPUID_PGE;
 		ci->ci_feat_val[0] = flag;
+	}
 	cpu_probe_amd_cache(ci);
+}
 static void
 cpu_probe_k678(struct cpu_info *ci)
+{
 	uint32_t descs[4];
 	if (cpu_vendor != CPUVENDOR_AMD ||
-	    CPUID2FAMILY(ci->ci_signature) < 6)
+	    CPUID_TO_FAMILY(ci->ci_signature) < 6)
 		return;
 	/* Determine the extended feature flags. */
 	x86_cpuid(0x80000000, descs);
 	if (descs[0] >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[3] = descs[2]; /* %ecx */
 		ci->ci_feat_val[2] = descs[3]; /* %edx */
+	}
 	cpu_probe_amd_cache(ci);
+}
 @@ -359,44 +448,44 @@ cpu_probe_cyrix_cmn(struct cpu_info *ci)
 	cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8);
 	cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f);
 	cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff);
 	cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87);
 	/* disable access to ccr4/ccr5 */
 	cyrix_write_reg(0xC3, c3);
+}
 static void
 cpu_probe_cyrix(struct cpu_info *ci)
+{
 	if (cpu_vendor != CPUVENDOR_CYRIX ||
-	    CPUID2FAMILY(ci->ci_signature) < 4 ||
+	    CPUID_TO_FAMILY(ci->ci_signature) < 4 ||
-	    CPUID2FAMILY(ci->ci_signature) > 6)
+	    CPUID_TO_FAMILY(ci->ci_signature) > 6)
 		return;
 	cpu_probe_cyrix_cmn(ci);
+}
 static void
 cpu_probe_winchip(struct cpu_info *ci)
+{
 	if (cpu_vendor != CPUVENDOR_IDT)
 	    	return;
-	switch (CPUID2FAMILY(ci->ci_signature)) {
+	switch (CPUID_TO_FAMILY(ci->ci_signature)) {
 	case 5:
 		/* WinChip C6 */
-		if (CPUID2MODEL(ci->ci_signature) == 4)
+		if (CPUID_TO_MODEL(ci->ci_signature) == 4)
 			ci->ci_feat_val[0] &= ~CPUID_TSC;
 		break;
 	case 6:
 		/*
 		 * VIA Eden ESP
+		 *
 		 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
 		 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
+		 *
 		 * 1. The CMPXCHG8B instruction is provided and always enabled,
 		 *    however, it appears disabled in the corresponding CPUID
 		 *    function bit 0 to avoid a bug in an early version of
 		 *    Windows NT. However, this default can be changed via a
 @@ -405,32 +494,32 @@ cpu_probe_winchip(struct cpu_info *ci)
 		ci->ci_feat_val[0] |= CPUID_CX8;
 		wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | 0x00000001);
 		break;
+	}
+}
 static void
 cpu_probe_c3(struct cpu_info *ci)
+{
 	u_int family, model, stepping, descs[4], lfunc, msr;
 	struct x86_cache_info *cai;
 	if (cpu_vendor != CPUVENDOR_IDT ||
-	    CPUID2FAMILY(ci->ci_signature) < 6)
+	    CPUID_TO_FAMILY(ci->ci_signature) < 6)
 	    	return;
-	family = CPUID2FAMILY(ci->ci_signature);
+	family = CPUID_TO_FAMILY(ci->ci_signature);
-	model = CPUID2MODEL(ci->ci_signature);
+	model = CPUID_TO_MODEL(ci->ci_signature);
-	stepping = CPUID2STEPPING(ci->ci_signature);
+	stepping = CPUID_TO_STEPPING(ci->ci_signature);
 	/* Determine the largest extended function value. */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	/* Determine the extended feature flags. */
 	if (lfunc >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] = descs[3];
+	}
 	if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) {
 		/* Nehemiah or Esther */
 @@ -545,27 +634,27 @@ cpu_probe_c3(struct cpu_info *ci)
 		cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]);
 	} else {
 		cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]);
 		cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]);
 		cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]);
+	}
+}
 static void
 cpu_probe_geode(struct cpu_info *ci)
+{
 	if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 ||
-	    CPUID2FAMILY(ci->ci_signature) != 5)
+	    CPUID_TO_FAMILY(ci->ci_signature) != 5)
 	    	return;
 	cpu_probe_cyrix_cmn(ci);
 	cpu_probe_amd_cache(ci);
+}
 static void
 cpu_probe_vortex86(struct cpu_info *ci)
+{
 #define PCI_MODE1_ADDRESS_REG	0x0cf8
 #define PCI_MODE1_DATA_REG	0x0cfc
 #define PCI_MODE1_ENABLE	0x80000000UL
 @@ -596,30 +685,28 @@ cpu_probe_vortex86(struct cpu_info *ci)
 	default:
 		strcpy(cpu_brand_string, "Unknown Vortex86");
 		break;
+	}
 #undef PCI_MODE1_ENABLE
 #undef PCI_MODE1_ADDRESS_REG
 #undef PCI_MODE1_DATA_REG
+}
 void
 cpu_probe(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cai;
 	u_int descs[4];
-	int iterations, i, j;
+	int i;
 	uint8_t desc;
 	uint32_t miscbytes;
 	uint32_t brand[12];
 	cpu_vendor = i386_nocpuid_cpus[cpu << 1];
 	cpu_class = i386_nocpuid_cpus[(cpu << 1) + 1];
 	if (cpuid_level < 0)
 		return;
 	for (i = 0; i < __arraycount(ci->ci_feat_val); i++) {
 		ci->ci_feat_val[i] = 0;
+	}
 @@ -657,61 +744,38 @@ cpu_probe(struct cpu_info *ci)
 				break;
+		}
 		memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i);
+	}
 	if (cpuid_level >= 1) {
 		x86_cpuid(1, descs);
 		ci->ci_signature = descs[0];
 		miscbytes = descs[1];
 		ci->ci_feat_val[1] = descs[2];
 		ci->ci_feat_val[0] = descs[3];
 		/* Determine family + class. */
-		cpu_class = CPUID2FAMILY(ci->ci_signature) + (CPUCLASS_386 - 3);
+		cpu_class = CPUID_TO_FAMILY(ci->ci_signature)
 		    + (CPUCLASS_386 - 3);
 		if (cpu_class > CPUCLASS_686)
 			cpu_class = CPUCLASS_686;
 		/* CLFLUSH line size is next 8 bits */
 		if (ci->ci_feat_val[0] & CPUID_CFLUSH)
 			ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3;
 		ci->ci_initapicid = (miscbytes >> 24) & 0xff;
+	}
-	if (cpuid_level >= 2) {
+	cpu_probe_intel(ci);
 		/* Parse the cache info from `cpuid', if we have it. */
 		x86_cpuid(2, descs);
 		iterations = descs[0] & 0xff;
 		while (iterations-- > 0) {
 			for (i = 0; i < 4; i++) {
 				if (descs[i] & 0x80000000)
 					continue;
 				for (j = 0; j < 4; j++) {
 					if (i == 0 && j == 0)
 						continue;
 					desc = (descs[i] >> (j * 8)) & 0xff;
 					if (desc == 0)
 						continue;
 					cai = cache_info_lookup(
 					    intel_cpuid_cache_info, desc);
 					if (cai != NULL) {
 						ci->ci_cinfo[cai->cai_index] =
 						    *cai;
 	cpu_probe_k5(ci);
 	cpu_probe_k678(ci);
 	cpu_probe_cyrix(ci);
 	cpu_probe_winchip(ci);
 	cpu_probe_c3(ci);
 	cpu_probe_geode(ci);
 	cpu_probe_vortex86(ci);
 	x86_cpu_topology(ci);
 	if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) &&
 	    (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) {
 		/* Enable thermal monitor 1. */