 @@ -1,14 +1,14 @@
-/* $NetBSD: amlogic_reg.h,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
+/* $NetBSD: amlogic_reg.h,v 1.4 2015/03/01 15:07:49 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -22,38 +22,51 @@
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #ifndef _ARM_AMLOGIC_REG_H
 #define _ARM_AMLOGIC_REG_H
 #define CONSADDR_VA	(CONSADDR - AMLOGIC_CORE_BASE + AMLOGIC_CORE_VBASE)
 #define AMLOGIC_CORE_BASE	0xc0000000
-#define AMLOGIC_CORE_SIZE	0x10200000
+#define AMLOGIC_CORE_SIZE	0x1b000000
 #define AMLOGIC_CORE_VBASE	0xe0000000
 #define AMLOGIC_CBUS_OFFSET	0x01100000
 #define AMLOGIC_UART0_OFFSET	0x01102130
 #define AMLOGIC_UART1_OFFSET	0x01102137
 #define AMLOGIC_UART2_OFFSET	0x011021c0
 #define AMLOGIC_UART0AO_OFFSET	0x081004c0
 #define AMLOGIC_UART2AO_OFFSET	0x081004e0
 #define AMLOGIC_UART_SIZE	0x20
 #define AMLOGIC_UART_FREQ	24000000
 #define AMLOGIC_MMC_OFFSET	0x01108e00
 #define AMLOGIC_MMC_SIZE	0x30
 #define AMLOGIC_PL310_OFFSET	0x04200000
 #define AMLOGIC_AOBUS_OFFSET	0x08100000
 #define AMLOGIC_GPIOAO_OFFSET	0x08100024
 #define AMLOGIC_USB0_OFFSET	0x09040000
 #define AMLOGIC_USB1_OFFSET	0x090c0000
 #define AMLOGIC_USB_SIZE	0x40000
 #define AMLOGIC_CPUCONF_OFFSET	0x1901ff80
 #define AMLOGIC_CBUS_CPU_CLK_CNTL_REG	0x419c
 #define AMLOGIC_AOBUS_PWR_CTRL0_REG	0xe0
 #define AMLOGIC_AOBUS_PWR_CTRL1_REG	0xe4
 #define AMLOGIC_AOBUS_PWR_MEM_PD0_REG	0xf4
 #define AMLOGIC_CPUCONF_CTRL_REG	0x00
 #define AMLOGIC_CPUCONF_CPU_ADDR_REG(n)	(0x04 * (n))
 #endif /* _ARM_AMLOGIC_REG_H */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amlogic_machdep.c,v 1.8 2015/02/28 18:50:15 jmcneill Exp $ */
+/*	$NetBSD: amlogic_machdep.c,v 1.9 2015/03/01 15:07:49 jmcneill Exp $ */
 /*
  * Machine dependent functions for kernel setup for TI OSK5912 board.
  * Based on lubbock_machdep.c which in turn was based on iq80310_machhdep.c
+ *
  * Copyright (c) 2002, 2003, 2005  Genetec Corporation.  All rights reserved.
  * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -115,35 +115,36 @@
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_machdep.c,v 1.8 2015/02/28 18:50:15 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_machdep.c,v 1.9 2015/03/01 15:07:49 jmcneill Exp $");
 #include "opt_machdep.h"
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_ipkdb.h"
 #include "opt_md.h"
 #include "opt_amlogic.h"
 #include "opt_arm_debug.h"
 #include "opt_multiprocessor.h"
 #include "amlogic_com.h"
 #if 0
 #include "prcm.h"
 #include "sdhc.h"
 #include "ukbd.h"
 #endif
 #include "arml2cc.h"
 #include "act8846pm.h"
 #include "ether.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 @@ -318,42 +319,44 @@ initarm(void *arg)
+{
 	psize_t ram_size = 0;
 	*(volatile int *)CONSADDR_VA  = 0x40;	/* output '@' */
 	amlogic_putchar('d');
 	pmap_devmap_register(devmap);
 	amlogic_putchar('b');
 	amlogic_bootstrap();
 	amlogic_putchar('!');
 #ifdef MULTIPROCESSOR
-	uint32_t scu_cfg = bus_space_read_4(&amlogic_bs_tag,
+	const bus_addr_t cbar = armreg_cbar_read();
-	    amlogic_core0_bsh, ROCKCHIP_SCU_OFFSET + SCU_CFG);
+	if (cbar) {
-	arm_cpu_max = (scu_cfg & SCU_CFG_CPUMAX) + 1;
+		const bus_space_handle_t scu_bsh =
-	membar_producer();
+		    cbar - AMLOGIC_CORE_BASE + AMLOGIC_CORE_VBASE;
 		uint32_t scu_cfg = bus_space_read_4(&amlogic_bs_tag, scu_bsh,
 		    SCU_CFG);
 		arm_cpu_max = (scu_cfg & SCU_CFG_CPUMAX) + 1;
 		membar_producer();
+	}
 #endif
 	/* Heads up ... Setup the CPU / MMU / TLB functions. */
 	if (set_cpufuncs())
 		panic("cpu not recognized!");
 	init_clocks();
 	consinit();
 #ifdef MULTIPROCESSOR
 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
 #endif
 #if NARML2CC > 0
         /*
          * Probe the PL310 L2CC
          */
 	printf("probe the PL310 L2CC\n");
         const bus_space_handle_t pl310_bh =
             AMLOGIC_CORE_VBASE + AMLOGIC_PL310_OFFSET;
         arml2cc_init(&amlogic_bs_tag, pl310_bh, 0);
         amlogic_putchar('l');
 #endif
 	printf("\nuboot arg = %#x, %#x, %#x, %#x\n",
 @@ -563,13 +566,130 @@ amlogic_device_register(device_t self, v
 		return;
+	}
 	if (device_is_a(self, "arml2cc")) {
 		/*
 		 * L2 cache regs are at C4200000 and A9 periph base is
 		 * at C4300000; pass as a negative offset for the benefit
 		 * of armperiph bus.
 		 */
 		prop_dictionary_set_uint32(dict, "offset", 0xfff00000);
+	}
+}
 #if defined(MULTIPROCESSOR)
 void amlogic_mpinit(uint32_t);
 static void
 amlogic_mpinit_delay(u_int n)
+{
 	for (volatile int i = 0; i < n; i++)
+		;
+}
 static void
 amlogic_mpinit_cpu(int cpu)
+{
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &amlogic_bs_tag;
 	const bus_space_handle_t scu_bsh =
 	    cbar - AMLOGIC_CORE_BASE + AMLOGIC_CORE_VBASE;
 	const bus_space_handle_t ao_bsh =
 	    AMLOGIC_CORE_VBASE + AMLOGIC_AOBUS_OFFSET;
 	const bus_space_handle_t cbus_bsh =
 	    AMLOGIC_CORE_VBASE + AMLOGIC_CBUS_OFFSET;
 	uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0;
 	pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS);
 	pwr_sts &= ~(3 << (8 * cpu));
 	bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts);
 	pwr_cntl0 = bus_space_read_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL0_REG);
 	pwr_cntl0 &= ~((3 << 18) << ((cpu - 1) * 2));
 	bus_space_write_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
 	amlogic_mpinit_delay(5000);
 	cpuclk = bus_space_read_4(bst, cbus_bsh, AMLOGIC_CBUS_CPU_CLK_CNTL_REG);
 	cpuclk |= (1 << (24 + cpu));
 	bus_space_write_4(bst, cbus_bsh, AMLOGIC_CBUS_CPU_CLK_CNTL_REG, cpuclk);
 	mempd0 = bus_space_read_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_MEM_PD0_REG);
 	mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpu - 1) * 4));
 	bus_space_write_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_MEM_PD0_REG, mempd0);
 	pwr_cntl1 = bus_space_read_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL1_REG);
 	pwr_cntl1 &= ~((3 << 4) << ((cpu - 1) * 2));
 	bus_space_write_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL1_REG, pwr_cntl1);
 	amlogic_mpinit_delay(10000);
 	for (;;) {
 		pwr_cntl1 = bus_space_read_4(bst, ao_bsh,
 		    AMLOGIC_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpu - 1));
 		if (pwr_cntl1)
 			break;
 		amlogic_mpinit_delay(10000);
+	}
 	pwr_cntl0 = bus_space_read_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL0_REG);
 	pwr_cntl0 &= ~(1 << cpu);
 	bus_space_write_4(bst, ao_bsh, AMLOGIC_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
 	cpuclk = bus_space_read_4(bst, cbus_bsh, AMLOGIC_CBUS_CPU_CLK_CNTL_REG);
 	cpuclk &= ~(1 << (24 + cpu));
 	bus_space_write_4(bst, cbus_bsh, AMLOGIC_CBUS_CPU_CLK_CNTL_REG, cpuclk);
 	bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts);
+}
 void
 amlogic_mpinit(uint32_t mpinit_vec)
+{
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &amlogic_bs_tag;
 	volatile int i;
 	uint32_t ctrl, hatched = 0;
 	int cpu;
 	if (cbar == 0)
 		return;
 	const bus_space_handle_t scu_bsh =
 	    cbar - AMLOGIC_CORE_BASE + AMLOGIC_CORE_VBASE;
 	const bus_space_handle_t cpuconf_bsh =
 	    AMLOGIC_CORE_VBASE + AMLOGIC_CPUCONF_OFFSET;
 	const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG);
 	const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1;
 	if (ncpus < 2)
 		return;
 	for (cpu = 1; cpu < ncpus; cpu++) {
 		bus_space_write_4(bst, cpuconf_bsh,
 		    AMLOGIC_CPUCONF_CPU_ADDR_REG(cpu), mpinit_vec);
 		amlogic_mpinit_cpu(cpu);
 		hatched |= __BIT(cpu);
+	}
 	ctrl = bus_space_read_4(bst, cpuconf_bsh, AMLOGIC_CPUCONF_CTRL_REG);
 	for (cpu = 0; cpu < ncpus; cpu++) {
 		ctrl |= __BIT(cpu);
+	}
 	bus_space_write_4(bst, cpuconf_bsh, AMLOGIC_CPUCONF_CTRL_REG, ctrl);
 	__asm __volatile("sev");
 	for (i = 0x10000000; i > 0; i--) {
 		__asm __volatile("dmb" ::: "memory");
 		if (arm_cpu_hatched == hatched)
 			break;
+	}
 	if (i == 0) {
 		const char *msg = "\nWARNING: Some APs failed to start\n";
 		const char *p = msg;
 		while (*p)
 			amlogic_putchar(*p++);
+	}
+}
 #endif

 @@ -33,27 +33,27 @@
 #include "opt_cputypes.h"
 #include "opt_multiprocessor.h"
 #include "opt_arm_debug.h"
 #include <arm/asm.h>
 #include <arm/armreg.h>
 #include "assym.h"
 #include <arm/amlogic/amlogic_reg.h>
 #include <evbarm/amlogic/platform.h>
 #include <arm/cortex/scu_reg.h>
-RCSID("$NetBSD: amlogic_start.S,v 1.1 2015/02/07 17:20:16 jmcneill Exp $")
+RCSID("$NetBSD: amlogic_start.S,v 1.2 2015/03/01 15:07:49 jmcneill Exp $")
 #if defined(VERBOSE_INIT_ARM)
 #define	XPUTC(n)	mov r0, n; bl xputc
 #if KERNEL_BASE_VOFFSET == 0
 #define	XPUTC2(n)	mov r0, n; bl xputc
 #else
 #define XPUTC2(n)	mov r0, n; blx r11
 #endif
 #ifdef __ARMEB__
 #define COM_BSWAP
 #endif
 #define COM_MULT	4
 #define XPUTC_COM	1
 @@ -142,152 +142,50 @@ _C_LABEL(amlogic_start):
 	b	arm_cpuinit
 	.pushsection .text,"ax",%progbits
 :
 #endif
 	XPUTC2(#90)
 #if defined(MULTIPROCESSOR)
 	// Now spin up the second processors into the same state we are now.
 	XPUTC2(#77)
 	XPUTC2(#80)
 	XPUTC2(#60)
 	// Make sure the cache is flushed out to RAM for the other CPUs
 	bl	_C_LABEL(armv7_dcache_wbinv_all)
 	bl	amlogic_mpinit
 	movw	r0, #:lower16:amlogic_mpstart
 	movt	r0, #:upper16:amlogic_mpstart
 	bl	_C_LABEL(amlogic_mpinit)
 	XPUTC2(#62)
 #endif /* MULTIPROCESSOR */
 	XPUTC2(#13)
 	XPUTC2(#10)
 	/*
 	 * Jump to start in locore.S, which in turn will call initarm and main.
 	 */
 	b	start
 	/* NOTREACHED */
 #ifndef KERNEL_BASES_EQUAL
 	.popsection
 #endif
 #include <arm/cortex/a9_mpsubr.S>
-#define PMU_PWRDN_REG	0x0008
+#ifdef MULTIPROCESSOR
 #define PMU_PWRDN_SCU	__BIT(4)
 #if defined(MULTIPROCESSOR)
 #ifndef KERNEL_BASES_EQUAL
 	.pushsection .text,"ax",%progbits
 #endif
 amlogic_mptramp:
 	ldr	pc, 1f
 .global amlogic_mpstart_vec
 amlogic_mpstart_vec:
 :	.space	4
 amlogic_mpinit:
 	mov	r4, lr
 	/* r5: SCU, r6: PMU, r7: SRAM */
 	movw	r5, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
 	movt	r5, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SCU_OFFSET)
 	movw	r6, #:lower16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
 	movt	r6, #:upper16:(ROCKCHIP_CORE1_BASE+ROCKCHIP_PMU_OFFSET)
 	movw	r7, #:lower16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
 	movt	r7, #:upper16:(ROCKCHIP_CORE0_BASE+ROCKCHIP_SRAM_OFFSET)
 	/* Set where the other CPU(s) are going to execute */
 	XPUTC2(#118)
 	movw	r1, #:lower16:amlogic_mpstart
 	movt	r1, #:upper16:amlogic_mpstart
 	ldr	r0, =amlogic_mpstart_vec
 	str	r1, [r0]
 	ldr	r0, =amlogic_mptramp
 	mov	r2, #0
 :	ldr	r1, [r0, r2]
 	str	r1, [r7, r2]
 	add	r2, r2, #4
 	cmp	r2, #32
 	blt	1b
 	dsb
 	/* Invalid SCU cache tags */
 	XPUTC2(#45)
 	movw	r1, #0xffff
 	movt	r1, #0
 	str	r1, [r5, #SCU_INV_ALL_REG]
 	/* Get CPU count */
 	ldr	r1, [r5, #SCU_CFG]
 	and	r2, r1, #SCU_CFG_CPUMAX
 	add	r2, r2, #1
 	/* Convert to CPU1..N mask */
 	mov	r7, #0
 	lsl	r7, r2, #1
 	sub	r7, r7, #1
 	and	r7, r7, #~1
 	/* Power down secondary CPUs */
 	XPUTC2(#46)
 	ldr	r1, [r6, #PMU_PWRDN_REG]
 	orr	r1, r1, r7
 	str	r1, [r6, #PMU_PWRDN_REG]
 	dsb
 	/* Power up SCU */
 	XPUTC2(#46)
 	ldr	r1, [r6, #PMU_PWRDN_REG]
 	and	r1, r1, #~PMU_PWRDN_SCU
 	str	r1, [r6, #PMU_PWRDN_REG]
 	dsb
 	/* Enable SCU */
 	XPUTC2(#46)
 	ldr	r1, [r5, #SCU_CTL]
 	orr	r1, r1, #SCU_CTL_SCU_ENA
 	str	r1, [r5, #SCU_CTL]
 	dsb
 	/* Power up secondary CPUs */
 	XPUTC2(#33)
 	ldr	r1, [r6, #PMU_PWRDN_REG]
 	and	r1, r1, r7
 	str	r1, [r6, #PMU_PWRDN_REG]
 	dsb
 	XPUTC2(#49)
 	XPUTC2(#50)
 	XPUTC2(#51)
 	//
 	// Wait up a second for CPU1 to hatch.
 	//
 	movw	r2, #:lower16:arm_cpu_hatched
 	movt	r2, #:upper16:arm_cpu_hatched
 	mov	r1, #0x10000000
 :	dmb
 	ldr	r0, [r2]
 	cmp	r0, r7
 	beq	.hatched
 	subs	r1, r1, #1
 	bne	1b
 .hatched:
 	bx	r4
 ASEND(amlogic_mpinit)
 #ifndef KERNEL_BASES_EQUAL
 	.popsection
 #endif
 amlogic_mpstart:
 	/* invalidate cache */
 	movw	ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
 	movt	ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
 #ifndef KERNEL_BASES_EQUAL
 	sub	ip, ip, #KERNEL_BASE_VOFFSET
 #endif
 	blx	ip
 	b	_C_LABEL(cortex_mpstart)
 #endif /* MULTIPROCESSOR */

 @@ -1,15 +1,15 @@
+#
-#	$NetBSD: ODROID-C1,v 1.3 2015/02/28 18:52:01 jmcneill Exp $
+#	$NetBSD: ODROID-C1,v 1.4 2015/03/01 15:07:49 jmcneill Exp $
+#
 #	Odroid-C1 (Amlogic S805) based SBC (Single Board Computer)
+#
 include	"arch/evbarm/conf/std.amlogic"
 # estimated number of users
 maxusers	32
 # Standard system options
 options 	RTC_OFFSET=0	# hardware clock is this many mins. west of GMT
 @@ -146,27 +146,27 @@ options		DDB_COMMANDONENTER="bt"
 #options 	KGDB
 makeoptions	DEBUG="-g"	# compile full symbol table
 makeoptions	COPY_SYMTAB=1
 options 	BOOT_ARGS="\"\""
 config		netbsd		root on ? type ?
 # The main bus device
 mainbus0	at root
 # The boot cpu
 cpu*		at mainbus?
-#options 	MULTIPROCESSOR
+options 	MULTIPROCESSOR
 # A5 core devices
 armperiph0	at mainbus?
 arml2cc0	at armperiph?				# L2 Cache Controller
 armgic0		at armperiph?				# Interrupt Controller
 a9tmr0		at armperiph?				# Global Timer
 a9wdt0		at armperiph?				# Watchdog
 # Specify the memory size in megabytes.
 options 	MEMSIZE=1024
 # On-board I/O
 amlogicio0	at mainbus?