 @@ -1,1055 +1,1055 @@
-/*	$NetBSD: ehci.c,v 1.234.2.37 2015/03/03 06:36:53 skrll Exp $ */
+/*	$NetBSD: ehci.c,v 1.234.2.38 2015/03/03 10:06:01 skrll Exp $ */
 /*
  * Copyright (c) 2004-2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum,
  * Jeremy Morse (jeremy.morse@gmail.com), Jared D. McNeill
  * (jmcneill@invisible.ca) and Matthew R. Green (mrg@eterna.com.au).
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
+ *
  * The EHCI 1.0 spec can be found at
  * http://www.intel.com/technology/usb/spec.htm
  * and the USB 2.0 spec at
  * http://www.usb.org/developers/docs/
+ *
  */
 /*
  * TODO:
  * 1) hold off explorations by companion controllers until ehci has started.
+ *
  * 2) The hub driver needs to handle and schedule the transaction translator,
  *    to assign place in frame where different devices get to go. See chapter
  *    on hubs in USB 2.0 for details.
+ *
  * 3) Command failures are not recovered correctly.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.37 2015/03/03 06:36:53 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.38 2015/03/03 10:06:01 skrll Exp $");
 #include "ohci.h"
 #include "uhci.h"
 #include "opt_usb.h"
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/mutex.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/select.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <machine/endian.h>
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
 #include <dev/usb/usbdivar.h>
 #include <dev/usb/usbhist.h>
 #include <dev/usb/usb_mem.h>
 #include <dev/usb/usb_quirks.h>
 #include <dev/usb/ehcireg.h>
 #include <dev/usb/ehcivar.h>
 #include <dev/usb/usbroothub.h>
 #ifdef USB_DEBUG
 #ifndef EHCI_DEBUG
 #define ehcidebug 0
 #else
 static int ehcidebug = 0;
 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup")
+{
 	int err;
 	const struct sysctlnode *rnode;
 	const struct sysctlnode *cnode;
 	err = sysctl_createv(clog, 0, NULL, &rnode,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci",
 	    SYSCTL_DESCR("ehci global controls"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	/* control debugging printfs */
 	err = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "debug", SYSCTL_DESCR("Enable debugging output"),
 	    NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	return;
 fail:
 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
+}
 #endif /* EHCI_DEBUG */
 #endif /* USB_DEBUG */
 struct ehci_pipe {
 	struct usbd_pipe pipe;
 	int nexttoggle;
 	ehci_soft_qh_t *sqh;
 	union {
 		ehci_soft_qtd_t *qtd;
 		/* ehci_soft_itd_t *itd; */
 		/* ehci_soft_sitd_t *sitd; */
 	} tail;
 	union {
 		/* Control pipe */
 		struct {
 			usb_dma_t reqdma;
 		} ctl;
 		/* Interrupt pipe */
 		struct {
 			u_int length;
 		} intr;
 		/* Bulk pipe */
 		struct {
 			u_int length;
 		} bulk;
 		/* Iso pipe */
 		struct {
 			u_int next_frame;
 			u_int cur_xfers;
 		} isoc;
 	} u;
 };
 Static usbd_status	ehci_open(usbd_pipe_handle);
 Static void		ehci_poll(struct usbd_bus *);
 Static void		ehci_softintr(void *);
 Static int		ehci_intr1(ehci_softc_t *);
 Static void		ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
 Static void		ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
 Static void		ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *);
 Static void		ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *);
 Static void		ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *);
 Static void		ehci_idone(struct ehci_xfer *);
 Static void		ehci_timeout(void *);
 Static void		ehci_timeout_task(void *);
 Static void		ehci_intrlist_timeout(void *);
 Static void		ehci_doorbell(void *);
 Static void		ehci_pcd(void *);
 Static usbd_xfer_handle	ehci_allocx(struct usbd_bus *);
 Static void		ehci_freex(struct usbd_bus *, usbd_xfer_handle);
 Static void		ehci_get_lock(struct usbd_bus *, kmutex_t **);
 Static int		ehci_roothub_ctrl(struct usbd_bus *,
     usb_device_request_t *, void *, int);
 Static usbd_status	ehci_root_intr_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_root_intr_start(usbd_xfer_handle);
 Static void		ehci_root_intr_abort(usbd_xfer_handle);
 Static void		ehci_root_intr_close(usbd_pipe_handle);
 Static void		ehci_root_intr_done(usbd_xfer_handle);
 Static usbd_status	ehci_device_ctrl_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_device_ctrl_start(usbd_xfer_handle);
 Static void		ehci_device_ctrl_abort(usbd_xfer_handle);
 Static void		ehci_device_ctrl_close(usbd_pipe_handle);
 Static void		ehci_device_ctrl_done(usbd_xfer_handle);
 Static usbd_status	ehci_device_bulk_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_device_bulk_start(usbd_xfer_handle);
 Static void		ehci_device_bulk_abort(usbd_xfer_handle);
 Static void		ehci_device_bulk_close(usbd_pipe_handle);
 Static void		ehci_device_bulk_done(usbd_xfer_handle);
 Static usbd_status	ehci_device_intr_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_device_intr_start(usbd_xfer_handle);
 Static void		ehci_device_intr_abort(usbd_xfer_handle);
 Static void		ehci_device_intr_close(usbd_pipe_handle);
 Static void		ehci_device_intr_done(usbd_xfer_handle);
 Static usbd_status	ehci_device_isoc_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_device_isoc_start(usbd_xfer_handle);
 Static void		ehci_device_isoc_abort(usbd_xfer_handle);
 Static void		ehci_device_isoc_close(usbd_pipe_handle);
 Static void		ehci_device_isoc_done(usbd_xfer_handle);
 Static usbd_status	ehci_device_fs_isoc_transfer(usbd_xfer_handle);
 Static usbd_status	ehci_device_fs_isoc_start(usbd_xfer_handle);
 Static void		ehci_device_fs_isoc_abort(usbd_xfer_handle);
 Static void		ehci_device_fs_isoc_close(usbd_pipe_handle);
 Static void		ehci_device_fs_isoc_done(usbd_xfer_handle);
 Static void		ehci_device_clear_toggle(usbd_pipe_handle);
 Static void		ehci_noop(usbd_pipe_handle);
 Static void		ehci_disown(ehci_softc_t *, int, int);
 Static ehci_soft_qh_t  *ehci_alloc_sqh(ehci_softc_t *);
 Static void		ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
 Static ehci_soft_qtd_t  *ehci_alloc_sqtd(ehci_softc_t *);
 Static void		ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
 Static usbd_status	ehci_alloc_sqtd_chain(struct ehci_pipe *,
 			    ehci_softc_t *, int, int, usbd_xfer_handle,
 			    ehci_soft_qtd_t **, ehci_soft_qtd_t **);
 Static void		ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
 					    ehci_soft_qtd_t *);
 Static ehci_soft_itd_t	*ehci_alloc_itd(ehci_softc_t *);
 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *);
 Static void		ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *);
 Static void		ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *);
 Static void 		ehci_rem_free_itd_chain(ehci_softc_t *,
 						struct ehci_xfer *);
 Static void		ehci_rem_free_sitd_chain(ehci_softc_t *,
 						 struct ehci_xfer *);
 Static void 		ehci_abort_isoc_xfer(usbd_xfer_handle,
 						usbd_status);
 Static usbd_status	ehci_device_request(usbd_xfer_handle);
 Static usbd_status	ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
 			    int);
 Static void		ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *,
 				    ehci_soft_qh_t *);
 Static void		ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
 				    ehci_soft_qh_t *);
 Static void		ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
 Static void		ehci_sync_hc(ehci_softc_t *);
 Static void		ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
 Static void		ehci_abort_xfer(usbd_xfer_handle, usbd_status);
 #ifdef EHCI_DEBUG
 Static ehci_softc_t 	*theehci;
 void			ehci_dump(void);
 #endif
 #ifdef EHCI_DEBUG
 Static void		ehci_dump_regs(ehci_softc_t *);
 Static void		ehci_dump_sqtds(ehci_soft_qtd_t *);
 Static void		ehci_dump_sqtd(ehci_soft_qtd_t *);
 Static void		ehci_dump_qtd(ehci_qtd_t *);
 Static void		ehci_dump_sqh(ehci_soft_qh_t *);
 Static void		ehci_dump_sitd(struct ehci_soft_itd *);
 Static void		ehci_dump_itd(struct ehci_soft_itd *);
 Static void		ehci_dump_exfer(struct ehci_xfer *);
 #endif
 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
 #define ehci_add_intr_list(sc, ex) \
 	TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next);
 #define ehci_del_intr_list(sc, ex) \
 	do { \
 		TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \
 		(ex)->ex_next.tqe_prev = NULL; \
 	} while (0)
 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL)
 Static const struct usbd_bus_methods ehci_bus_methods = {
 	.ubm_open =	ehci_open,
 	.ubm_softint =	ehci_softintr,
 	.ubm_dopoll =	ehci_poll,
 	.ubm_allocx =	ehci_allocx,
 	.ubm_freex =	ehci_freex,
 	.ubm_getlock =	ehci_get_lock,
 	.ubm_rhctrl =	ehci_roothub_ctrl,
 };
 Static const struct usbd_pipe_methods ehci_root_intr_methods = {
 	.upm_transfer =	ehci_root_intr_transfer,
 	.upm_start =	ehci_root_intr_start,
 	.upm_abort =	ehci_root_intr_abort,
 	.upm_close =	ehci_root_intr_close,
 	.upm_cleartoggle =	ehci_noop,
 	.upm_done =	ehci_root_intr_done,
 };
 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
 	.upm_transfer =	ehci_device_ctrl_transfer,
 	.upm_start =	ehci_device_ctrl_start,
 	.upm_abort =	ehci_device_ctrl_abort,
 	.upm_close =	ehci_device_ctrl_close,
 	.upm_cleartoggle =	ehci_noop,
 	.upm_done =	ehci_device_ctrl_done,
 };
 Static const struct usbd_pipe_methods ehci_device_intr_methods = {
 	.upm_transfer =	ehci_device_intr_transfer,
 	.upm_start =	ehci_device_intr_start,
 	.upm_abort =	ehci_device_intr_abort,
 	.upm_close =	ehci_device_intr_close,
 	.upm_cleartoggle =	ehci_device_clear_toggle,
 	.upm_done =	ehci_device_intr_done,
 };
 Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
 	.upm_transfer =	ehci_device_bulk_transfer,
 	.upm_start =	ehci_device_bulk_start,
 	.upm_abort =	ehci_device_bulk_abort,
 	.upm_close =	ehci_device_bulk_close,
 	.upm_cleartoggle =	ehci_device_clear_toggle,
 	.upm_done =	ehci_device_bulk_done,
 };
 Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
 	.upm_transfer =	ehci_device_isoc_transfer,
 	.upm_start =	ehci_device_isoc_start,
 	.upm_abort =	ehci_device_isoc_abort,
 	.upm_close =	ehci_device_isoc_close,
 	.upm_cleartoggle =	ehci_noop,
 	.upm_done =	ehci_device_isoc_done,
 };
 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = {
 	.upm_transfer =	ehci_device_fs_isoc_transfer,
 	.upm_start =	ehci_device_fs_isoc_start,
 	.upm_abort =	ehci_device_fs_isoc_abort,
 	.upm_close =	ehci_device_fs_isoc_close,
 	.upm_cleartoggle = ehci_noop,
 	.upm_done =	ehci_device_fs_isoc_done,
 };
 static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
 x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
 x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
 x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
 x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
 x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
 x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
 x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
 x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
 };
 int
 ehci_init(ehci_softc_t *sc)
+{
 	uint32_t vers, sparams, cparams, hcr;
 	u_int i;
 	usbd_status err;
 	ehci_soft_qh_t *sqh;
 	u_int ncomp;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 #ifdef EHCI_DEBUG
 	theehci = sc;
 #endif
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
 	cv_init(&sc->sc_softwake_cv, "ehciab");
 	cv_init(&sc->sc_doorbell, "ehcidi");
 	sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0,
 	    "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL);
 	sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
 	    ehci_doorbell, sc);
 	KASSERT(sc->sc_doorbell_si != NULL);
 	sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
 	    ehci_pcd, sc);
 	KASSERT(sc->sc_pcd_si != NULL);
 	sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
 	vers = EREAD2(sc, EHCI_HCIVERSION);
 	aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
 	       vers >> 8, vers & 0xff);
 	sparams = EREAD4(sc, EHCI_HCSPARAMS);
 	USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0);
 	sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
 	ncomp = EHCI_HCS_N_CC(sparams);
 	if (ncomp != sc->sc_ncomp) {
 		aprint_verbose("%s: wrong number of companions (%d != %d)\n",
 			       device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
 #if NOHCI == 0 || NUHCI == 0
 		aprint_error("%s: ohci or uhci probably not configured\n",
 			     device_xname(sc->sc_dev));
 #endif
 		if (ncomp < sc->sc_ncomp)
 			sc->sc_ncomp = ncomp;
+	}
 	if (sc->sc_ncomp > 0) {
 		KASSERT(!(sc->sc_flags & EHCIF_ETTF));
 		aprint_normal("%s: companion controller%s, %d port%s each:",
 		    device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "",
 		    EHCI_HCS_N_PCC(sparams),
 		    EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
 		for (i = 0; i < sc->sc_ncomp; i++)
 			aprint_normal(" %s", device_xname(sc->sc_comps[i]));
 		aprint_normal("\n");
+	}
 	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
 	cparams = EREAD4(sc, EHCI_HCCPARAMS);
 	USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0);
 	sc->sc_hasppc = EHCI_HCS_PPC(sparams);
 	if (EHCI_HCC_64BIT(cparams)) {
 		/* MUST clear segment register if 64 bit capable. */
 		EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
+	}
 	sc->sc_bus.ub_revision = USBREV_2_0;
 	sc->sc_bus.ub_usedma = true;
 	sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG;
 	/* Reset the controller */
 	USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0);
 	EOWRITE4(sc, EHCI_USBCMD, 0);	/* Halt controller */
 	usb_delay_ms(&sc->sc_bus, 1);
 	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
 	for (i = 0; i < 100; i++) {
 		usb_delay_ms(&sc->sc_bus, 1);
 		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
 		if (!hcr)
 			break;
+	}
 	if (hcr) {
 		aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
 		return EIO;
+	}
 	if (sc->sc_vendor_init)
 		sc->sc_vendor_init(sc);
 	/*
 	 * If we are doing embedded transaction translation function, force
 	 * the controller to host mode.
 	 */
 	if (sc->sc_flags & EHCIF_ETTF) {
 		uint32_t usbmode = EREAD4(sc, EHCI_USBMODE);
 		usbmode &= ~EHCI_USBMODE_CM;
 		usbmode |= EHCI_USBMODE_CM_HOST;
 		EWRITE4(sc, EHCI_USBMODE, usbmode);
+	}
 	/* XXX need proper intr scheduling */
 	sc->sc_rand = 96;
 	/* frame list size at default, read back what we got and use that */
 	switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
 	case 0: sc->sc_flsize = 1024; break;
 	case 1: sc->sc_flsize = 512; break;
 	case 2: sc->sc_flsize = 256; break;
 	case 3: return EIO;
+	}
 	err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
 	    EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
 	if (err)
 		return err;
 	USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0);
 	sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
 	for (i = 0; i < sc->sc_flsize; i++) {
 		sc->sc_flist[i] = EHCI_NULL;
+	}
 	EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
 	sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
 				     KM_SLEEP);
 	if (sc->sc_softitds == NULL)
 		return ENOMEM;
 	LIST_INIT(&sc->sc_freeitds);
 	LIST_INIT(&sc->sc_freesitds);
 	TAILQ_INIT(&sc->sc_intrhead);
 	/* Set up the bus struct. */
 	sc->sc_bus.ub_methods = &ehci_bus_methods;
 	sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe);
 	sc->sc_eintrs = EHCI_NORMAL_INTRS;
 	/*
 	 * Allocate the interrupt dummy QHs. These are arranged to give poll
 	 * intervals that are powers of 2 times 1ms.
 	 */
 	for (i = 0; i < EHCI_INTRQHS; i++) {
 		sqh = ehci_alloc_sqh(sc);
 		if (sqh == NULL) {
 			err = ENOMEM;
 			goto bad1;
+		}
 		sc->sc_islots[i].sqh = sqh;
+	}
 	for (i = 0; i < EHCI_INTRQHS; i++) {
 		sqh = sc->sc_islots[i].sqh;
 		if (i == 0) {
 			/* The last (1ms) QH terminates. */
 			sqh->qh.qh_link = EHCI_NULL;
 			sqh->next = NULL;
 		} else {
 			/* Otherwise the next QH has half the poll interval */
 			sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
 			sqh->qh.qh_link = htole32(sqh->next->physaddr |
 			    EHCI_LINK_QH);
+		}
 		sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
 		sqh->qh.qh_curqtd = EHCI_NULL;
 		sqh->next = NULL;
 		sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
 		sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
 		sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
 		sqh->sqtd = NULL;
 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
+	}
 	/* Point the frame list at the last level (128ms). */
 	for (i = 0; i < sc->sc_flsize; i++) {
 		int j;
 		j = (i & ~(EHCI_MAX_POLLRATE-1)) |
 		    revbits[i & (EHCI_MAX_POLLRATE-1)];
 		sc->sc_flist[j] = htole32(EHCI_LINK_QH |
 		    sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
 		    i)].sqh->physaddr);
+	}
 	usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
 	    BUS_DMASYNC_PREWRITE);
 	/* Allocate dummy QH that starts the async list. */
 	sqh = ehci_alloc_sqh(sc);
 	if (sqh == NULL) {
 		err = ENOMEM;
 		goto bad1;
+	}
 	/* Fill the QH */
 	sqh->qh.qh_endp =
 	    htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
 	sqh->qh.qh_link =
 	    htole32(sqh->physaddr | EHCI_LINK_QH);
 	sqh->qh.qh_curqtd = EHCI_NULL;
 	sqh->next = NULL;
 	/* Fill the overlay qTD */
 	sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
 	sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
 	sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
 	sqh->sqtd = NULL;
 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
 #endif
 	/* Point to async list */
 	sc->sc_async_head = sqh;
 	EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
 	callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE);
 	/* Turn on controller */
 	EOWRITE4(sc, EHCI_USBCMD,
 		 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
 		 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
 		 EHCI_CMD_ASE |
 		 EHCI_CMD_PSE |
 		 EHCI_CMD_RS);
 	/* Take over port ownership */
 	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
 	for (i = 0; i < 100; i++) {
 		usb_delay_ms(&sc->sc_bus, 1);
 		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
 		if (!hcr)
 			break;
+	}
 	if (hcr) {
 		aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
 		return EIO;
+	}
 	/* Enable interrupts */
 	USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0);
 	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
 	return 0;
 #if 0
  bad2:
 	ehci_free_sqh(sc, sc->sc_async_head);
 #endif
  bad1:
 	usb_freemem(&sc->sc_bus, &sc->sc_fldma);
 	return err;
+}
 int
 ehci_intr(void *v)
+{
 	ehci_softc_t *sc = v;
 	int ret = 0;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	if (sc == NULL)
 		return 0;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
 		goto done;
 	/* If we get an interrupt while polling, then just ignore it. */
 	if (sc->sc_bus.ub_usepolling) {
 		uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
 		if (intrs)
 			EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
 		USBHIST_LOGN(ehcidebug, 16,
 		    "ignored interrupt while polling", 0, 0, 0, 0);
 		goto done;
+	}
 	ret = ehci_intr1(sc);
 done:
 	mutex_spin_exit(&sc->sc_intr_lock);
 	return ret;
+}
 Static int
 ehci_intr1(ehci_softc_t *sc)
+{
 	uint32_t intrs, eintrs;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	/* In case the interrupt occurs before initialization has completed. */
 	if (sc == NULL) {
 #ifdef DIAGNOSTIC
 		printf("ehci_intr1: sc == NULL\n");
 #endif
 		return 0;
+	}
 	KASSERT(mutex_owned(&sc->sc_intr_lock));
 	intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
 	if (!intrs)
 		return 0;
 	eintrs = intrs & sc->sc_eintrs;
 	USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x",
 	    sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs);
 	if (!eintrs)
 		return 0;
 	EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
 	if (eintrs & EHCI_STS_IAA) {
 		USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0);
 		kpreempt_disable();
 		KASSERT(sc->sc_doorbell_si != NULL);
 		softint_schedule(sc->sc_doorbell_si);
 		kpreempt_enable();
 		eintrs &= ~EHCI_STS_IAA;
+	}
 	if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
 		USBHIST_LOG(ehcidebug, "INT=%d  ERRINT=%d",
 		    eintrs & EHCI_STS_INT ? 1 : 0,
 		    eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0);
 		usb_schedsoftintr(&sc->sc_bus);
 		eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
+	}
 	if (eintrs & EHCI_STS_HSE) {
 		printf("%s: unrecoverable error, controller halted\n",
 		       device_xname(sc->sc_dev));
 		/* XXX what else */
+	}
 	if (eintrs & EHCI_STS_PCD) {
 		kpreempt_disable();
 		KASSERT(sc->sc_pcd_si != NULL);
 		softint_schedule(sc->sc_pcd_si);
 		kpreempt_enable();
 		eintrs &= ~EHCI_STS_PCD;
+	}
 	if (eintrs != 0) {
 		/* Block unprocessed interrupts. */
 		sc->sc_eintrs &= ~eintrs;
 		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
 		printf("%s: blocking intrs 0x%x\n",
 		       device_xname(sc->sc_dev), eintrs);
+	}
 	return 1;
+}
 Static void
 ehci_doorbell(void *addr)
+{
 	ehci_softc_t *sc = addr;
 	mutex_enter(&sc->sc_lock);
 	cv_broadcast(&sc->sc_doorbell);
 	mutex_exit(&sc->sc_lock);
+}
 Static void
 ehci_pcd(void *addr)
+{
 	ehci_softc_t *sc = addr;
 	usbd_xfer_handle xfer;
 	u_char *p;
 	int i, m;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	mutex_enter(&sc->sc_lock);
 	xfer = sc->sc_intrxfer;
 	if (xfer == NULL) {
 		/* Just ignore the change. */
 		goto done;
+	}
 	p = xfer->ux_buf;
 	m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
 	memset(p, 0, xfer->ux_length);
 	for (i = 1; i <= m; i++) {
 		/* Pick out CHANGE bits from the status reg. */
 		if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
 			p[i/8] |= 1 << (i%8);
 		if (i % 8 == 7)
 			USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8,
 			    p[i/8], 0, 0);
+	}
 	xfer->ux_actlen = xfer->ux_length;
 	xfer->ux_status = USBD_NORMAL_COMPLETION;
 	usb_transfer_complete(xfer);
 done:
 	mutex_exit(&sc->sc_lock);
+}
 Static void
 ehci_softintr(void *v)
+{
 	struct usbd_bus *bus = v;
 	ehci_softc_t *sc = bus->ub_hcpriv;
 	struct ehci_xfer *ex, *nextex;
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	/*
 	 * The only explanation I can think of for why EHCI is as brain dead
 	 * as UHCI interrupt-wise is that Intel was involved in both.
 	 * An interrupt just tells us that something is done, we have no
 	 * clue what, so we need to scan through all active transfers. :-(
 	 */
 	for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
 		nextex = TAILQ_NEXT(ex, ex_next);
 		ehci_check_intr(sc, ex);
+	}
 	/* Schedule a callout to catch any dropped transactions. */
 	if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
 	    !TAILQ_EMPTY(&sc->sc_intrhead))
 		callout_reset(&sc->sc_tmo_intrlist,
 		    hz, ehci_intrlist_timeout, sc);
 	if (sc->sc_softwake) {
 		sc->sc_softwake = 0;
 		cv_broadcast(&sc->sc_softwake_cv);
+	}
+}
 /* Check for an interrupt. */
 Static void
 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
+{
 	usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev;
 	int attr;
 	USBHIST_FUNC();	USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes;
 	if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) {
 		if (dev->ud_speed == USB_SPEED_HIGH)
 			ehci_check_itd_intr(sc, ex);
 		else
 			ehci_check_sitd_intr(sc, ex);
 	} else
 		ehci_check_qh_intr(sc, ex);
 	return;
+}
 Static void
 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
+{
 	ehci_soft_qtd_t *sqtd, *lsqtd;
 	uint32_t status;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	if (ex->ex_sqtdstart == NULL) {
 		printf("ehci_check_qh_intr: not valid sqtd\n");
 		return;
+	}
 	lsqtd = ex->ex_sqtdend;
 #ifdef DIAGNOSTIC
 	if (lsqtd == NULL) {
 		printf("ehci_check_qh_intr: lsqtd==0\n");
 		return;
+	}
 #endif
 	/*
 	 * If the last TD is still active we need to check whether there
 	 * is an error somewhere in the middle, or whether there was a
 	 * short packet (SPD and not ACTIVE).
 	 */
 	usb_syncmem(&lsqtd->dma,
 	    lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 	    sizeof(lsqtd->qtd.qtd_status),
 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 	status = le32toh(lsqtd->qtd.qtd_status);
 	usb_syncmem(&lsqtd->dma,
 	    lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 	    sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
 	if (status & EHCI_QTD_ACTIVE) {
 		USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0);
 		for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd;
 		     sqtd = sqtd->nextqtd) {
 			usb_syncmem(&sqtd->dma,
 			    sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 			    sizeof(sqtd->qtd.qtd_status),
 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 			status = le32toh(sqtd->qtd.qtd_status);
 			usb_syncmem(&sqtd->dma,
 			    sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 			    sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
 			/* If there's an active QTD the xfer isn't done. */
 			if (status & EHCI_QTD_ACTIVE)
 				break;
 			/* Any kind of error makes the xfer done. */
 			if (status & EHCI_QTD_HALTED)
 				goto done;
 			/* Handle short packets */
 			if (EHCI_QTD_GET_BYTES(status) != 0) {
 				usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe;
 				usb_endpoint_descriptor_t *ed =
 				    pipe->up_endpoint->ue_edesc;
 				uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes);
 				/*
 				 * If we get here for a control transfer then
 				 * we need to let the hardware complete the
 				 * status phase.  That is, we're not done
 				 * quite yet.
+				 *
 				 * Otherwise, we're done.
 				 */
 				if (xt == UE_CONTROL) {
 					break;
+				}
 				goto done;
+			}
+		}
 		USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active",
 		    ex, ex->ex_sqtdstart, 0, 0);
 #ifdef EHCI_DEBUG
 		USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0);
 		ehci_dump_sqtds(ex->ex_sqtdstart);
 		USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0);
 #endif
 		return;
+	}
  done:
 	USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0);
 	callout_stop(&ex->ex_xfer.ux_callout);
 	ehci_idone(ex);
+}
 Static void
 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
+{
 	ehci_soft_itd_t *itd;
 	int i;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
 		return;
 	if (ex->ex_itdstart == NULL) {
 		printf("ehci_check_itd_intr: not valid itd\n");
 		return;
+	}
 	itd = ex->ex_itdend;
 #ifdef DIAGNOSTIC
 	if (itd == NULL) {
 		printf("ehci_check_itd_intr: itdend == 0\n");
 		return;
+	}
 #endif
 	/*
 	 * check no active transfers in last itd, meaning we're finished
 	 */
 	usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
 		    sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
 		    BUS_DMASYNC_POSTREAD);
 	for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
 		if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
 			break;
+	}
 	if (i == EHCI_ITD_NUFRAMES) {
 		goto done; /* All 8 descriptors inactive, it's done */
+	}
 	USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex,
 	    ex->ex_itdstart, 0, 0);
 	return;
 done:
 	USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0);
 	callout_stop(&ex->ex_xfer.ux_callout);
 	ehci_idone(ex);
+}
 void
 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
+{
 	ehci_soft_sitd_t *sitd;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
 		return;
 	if (ex->ex_sitdstart == NULL) {
 		printf("ehci_check_sitd_intr: not valid sitd\n");
 		return;
+	}
 	sitd = ex->ex_sitdend;
 #ifdef DIAGNOSTIC
 	if (sitd == NULL) {
 		printf("ehci_check_sitd_intr: sitdend == 0\n");
 		return;
+	}
 #endif
 	/*
 	 * check no active transfers in last sitd, meaning we're finished
 	 */
 	usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
 		    sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE |
 		    BUS_DMASYNC_POSTREAD);
 	if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE)
 		return;
 	USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0);
 	callout_stop(&(ex->ex_xfer.ux_callout));
 	ehci_idone(ex);
+}
 Static void
 ehci_idone(struct ehci_xfer *ex)
+{
 	usbd_xfer_handle xfer = &ex->ex_xfer;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	ehci_soft_qtd_t *sqtd, *lsqtd;
 	uint32_t status = 0, nstatus = 0;
 	int actlen;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0);
 #ifdef DIAGNOSTIC
 #ifdef EHCI_DEBUG
 	if (ex->ex_isdone) {
 		USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
 		ehci_dump_exfer(ex);
 		USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
+	}
 #endif
 	KASSERT(!ex->ex_isdone);
 	ex->ex_isdone = true;
 #endif
 	if (xfer->ux_status == USBD_CANCELLED ||
 	    xfer->ux_status == USBD_TIMEOUT) {
 		USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0);
 		return;
+	}
 	USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
 	ehci_dump_sqtds(ex->ex_sqtdstart);
 	USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
 #endif
 	/* The transfer is done, compute actual length and status. */
 	u_int xfertype, speed;
 	xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes);
 	speed = xfer->ux_pipe->up_dev->ud_speed;
 	if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) {
 		/* HS isoc transfer */
 		struct ehci_soft_itd *itd;
 		int i, nframes, len, uframes;
 @@ -2539,2003 +2539,2003 @@ ehci_roothub_ctrl(struct usbd_bus *bus,
 			break;
 		default:
 			return -1;
+		}
 		break;
 	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
 	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
 	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
 	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
 		break;
 	default:
 		/* default from usbroothub */
 		USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)",
 		    buflen, 0, 0, 0);
 		return buflen;
+	}
 	USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0);
 	return totlen;
+}
 Static void
 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
+{
 	int port;
 	uint32_t v;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0);
 #ifdef DIAGNOSTIC
 	if (sc->sc_npcomp != 0) {
 		int i = (index-1) / sc->sc_npcomp;
 		if (i >= sc->sc_ncomp)
 			printf("%s: strange port\n",
 			       device_xname(sc->sc_dev));
 		else
 			printf("%s: handing over %s speed device on "
 			       "port %d to %s\n",
 			       device_xname(sc->sc_dev),
 			       lowspeed ? "low" : "full",
 			       index, device_xname(sc->sc_comps[i]));
 	} else {
 		printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
+	}
 #endif
 	port = EHCI_PORTSC(index);
 	v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
 	EOWRITE4(sc, port, v | EHCI_PS_PO);
+}
 Static usbd_status
 ehci_root_intr_transfer(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	/* Insert last in queue. */
 	mutex_enter(&sc->sc_lock);
 	err = usb_insert_transfer(xfer);
 	mutex_exit(&sc->sc_lock);
 	if (err)
 		return err;
 	/* Pipe isn't running, start first */
 	return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
+}
 Static usbd_status
 ehci_root_intr_start(usbd_xfer_handle xfer)
+{
 	usbd_pipe_handle pipe = xfer->ux_pipe;
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	mutex_enter(&sc->sc_lock);
 	sc->sc_intrxfer = xfer;
 	mutex_exit(&sc->sc_lock);
 	return USBD_IN_PROGRESS;
+}
 /* Abort a root interrupt request. */
 Static void
 ehci_root_intr_abort(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
 	sc->sc_intrxfer = NULL;
 	xfer->ux_status = USBD_CANCELLED;
 	usb_transfer_complete(xfer);
+}
 /* Close the root pipe. */
 Static void
 ehci_root_intr_close(usbd_pipe_handle pipe)
+{
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	sc->sc_intrxfer = NULL;
+}
 Static void
 ehci_root_intr_done(usbd_xfer_handle xfer)
+{
 	xfer->ux_hcpriv = NULL;
+}
 /************************/
 Static ehci_soft_qh_t *
 ehci_alloc_sqh(ehci_softc_t *sc)
+{
 	ehci_soft_qh_t *sqh;
 	usbd_status err;
 	int i, offs;
 	usb_dma_t dma;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	if (sc->sc_freeqhs == NULL) {
 		USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0);
 		err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
 			  EHCI_PAGE_SIZE, &dma);
 #ifdef EHCI_DEBUG
 		if (err)
 			printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
 #endif
 		if (err)
 			return NULL;
 		for (i = 0; i < EHCI_SQH_CHUNK; i++) {
 			offs = i * EHCI_SQH_SIZE;
 			sqh = KERNADDR(&dma, offs);
 			sqh->physaddr = DMAADDR(&dma, offs);
 			sqh->dma = dma;
 			sqh->offs = offs;
 			sqh->next = sc->sc_freeqhs;
 			sc->sc_freeqhs = sqh;
+		}
+	}
 	sqh = sc->sc_freeqhs;
 	sc->sc_freeqhs = sqh->next;
 	memset(&sqh->qh, 0, sizeof(ehci_qh_t));
 	sqh->next = NULL;
 	return sqh;
+}
 Static void
 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
+{
 	sqh->next = sc->sc_freeqhs;
 	sc->sc_freeqhs = sqh;
+}
 Static ehci_soft_qtd_t *
 ehci_alloc_sqtd(ehci_softc_t *sc)
+{
 	ehci_soft_qtd_t *sqtd = NULL;
 	usbd_status err;
 	int i, offs;
 	usb_dma_t dma;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	if (sc->sc_freeqtds == NULL) {
 		USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0);
 		err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
 			  EHCI_PAGE_SIZE, &dma);
 #ifdef EHCI_DEBUG
 		if (err)
 			printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
 #endif
 		if (err)
 			goto done;
 		for (i = 0; i < EHCI_SQTD_CHUNK; i++) {
 			offs = i * EHCI_SQTD_SIZE;
 			sqtd = KERNADDR(&dma, offs);
 			sqtd->physaddr = DMAADDR(&dma, offs);
 			sqtd->dma = dma;
 			sqtd->offs = offs;
 			sqtd->nextqtd = sc->sc_freeqtds;
 			sc->sc_freeqtds = sqtd;
+		}
+	}
 	sqtd = sc->sc_freeqtds;
 	sc->sc_freeqtds = sqtd->nextqtd;
 	memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
 	sqtd->nextqtd = NULL;
 	sqtd->xfer = NULL;
 done:
 	return sqtd;
+}
 Static void
 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
+{
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	sqtd->nextqtd = sc->sc_freeqtds;
 	sc->sc_freeqtds = sqtd;
+}
 Static usbd_status
 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
 		     int alen, int rd, usbd_xfer_handle xfer,
 		     ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
+{
 	ehci_soft_qtd_t *next, *cur;
 	ehci_physaddr_t nextphys;
 	uint32_t qtdstatus;
 	int len, curlen, mps;
 	int i, tog;
 	int pages, pageoffs;
 	size_t curoffs;
 	vaddr_t va, va_offs;
 	usb_dma_t *dma = &xfer->ux_dmabuf;
 	uint16_t flags = xfer->ux_flags;
 	paddr_t a;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0);
 	len = alen;
 	qtdstatus = EHCI_QTD_ACTIVE |
 	    EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
 	    EHCI_QTD_SET_CERR(3)
 	    /* IOC set below */
 	    /* BYTES set below */
+	    ;
 	mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
 	tog = epipe->nexttoggle;
 	qtdstatus |= EHCI_QTD_SET_TOGGLE(tog);
 	cur = ehci_alloc_sqtd(sc);
 	*sp = cur;
 	if (cur == NULL)
 		goto nomem;
 	usb_syncmem(dma, 0, alen,
 	    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
 	curoffs = 0;
 	for (;;) {
 		/* The EHCI hardware can handle at most 5 pages. */
 		va_offs = (vaddr_t)KERNADDR(dma, curoffs);
 		va_offs = EHCI_PAGE_OFFSET(va_offs);
 		if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) {
 			/* we can handle it in this QTD */
 			curlen = len - curoffs;
 		} else {
 			/* must use multiple TDs, fill as much as possible. */
 			curlen = EHCI_QTD_MAXTRANSFER - va_offs;
 			/* the length must be a multiple of the max size */
 			curlen -= curlen % mps;
 			USBHIST_LOG(ehcidebug, "multiple QTDs, "
 				    "curlen=%d", curlen, 0, 0, 0);
 			KASSERT(curlen != 0);
+		}
 		USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu",
 			len, curlen, curoffs, 0);
 		/*
 		 * Allocate another transfer if there's more data left,
 		 * or if force last short transfer flag is set and we're
 		 * allocating a multiple of the max packet size.
 		 */
 		if (curoffs + curlen != len ||
 		    ((curlen % mps) == 0 && !rd && curlen != 0 &&
 		     (flags & USBD_FORCE_SHORT_XFER))) {
 			next = ehci_alloc_sqtd(sc);
 			if (next == NULL)
 				goto nomem;
 			nextphys = htole32(next->physaddr);
 		} else {
 			next = NULL;
 			nextphys = EHCI_NULL;
+		}
 		/* Find number of pages we'll be using, insert dma addresses */
 		pages = EHCI_NPAGES(curlen);
 		KASSERT(pages <= EHCI_QTD_NBUFFERS);
 		pageoffs = EHCI_PAGE(curoffs);
 		for (i = 0; i < pages; i++) {
 			a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE);
 			cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a));
 			/* Cast up to avoid compiler warnings */
 			cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32);
+		}
 		/* First buffer pointer requires a page offset to start at */
 		va = (vaddr_t)KERNADDR(dma, curoffs);
 		cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va));
 		cur->nextqtd = next;
 		cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
 		cur->qtd.qtd_status =
 		    htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
 		cur->xfer = xfer;
 		cur->len = curlen;
 		USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx",
 		    curoffs, curoffs + curlen, 0, 0);
 		/*
 		 * adjust the toggle based on the number of packets in this
 		 * qtd
 		 */
 		if (((curlen + mps - 1) / mps) & 1) {
 			tog ^= 1;
 			qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
+		}
 		if (next == NULL)
 			break;
 		usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0);
 		if (len)
 			curoffs += curlen;
 		cur = next;
+	}
 	cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
 	usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	*ep = cur;
 	epipe->nexttoggle = tog;
 	USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p",
 	    *sp, *ep, 0, 0);
 	return USBD_NORMAL_COMPLETION;
  nomem:
 	/* XXX free chain */
 	USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0);
 	return USBD_NOMEM;
+}
 Static void
 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
 		    ehci_soft_qtd_t *sqtdend)
+{
 	ehci_soft_qtd_t *p;
 	int i;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p",
 	    sqtd, sqtdend, 0, 0);
 	for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
 		p = sqtd->nextqtd;
 		ehci_free_sqtd(sc, sqtd);
+	}
+}
 Static ehci_soft_itd_t *
 ehci_alloc_itd(ehci_softc_t *sc)
+{
 	struct ehci_soft_itd *itd, *freeitd;
 	usbd_status err;
 	int i, offs, frindex, previndex;
 	usb_dma_t dma;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	mutex_enter(&sc->sc_lock);
 	/*
 	 * Find an itd that wasn't freed this frame or last frame. This can
 	 * discard itds that were freed before frindex wrapped around
 	 * XXX - can this lead to thrashing? Could fix by enabling wrap-around
 	 *       interrupt and fiddling with list when that happens
 	 */
 	frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3;
 	previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize;
 	freeitd = NULL;
 	LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) {
 		if (itd == NULL)
 			break;
 		if (itd->slot != frindex && itd->slot != previndex) {
 			freeitd = itd;
 			break;
+		}
+	}
 	if (freeitd == NULL) {
 		USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0);
 		err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
 				EHCI_PAGE_SIZE, &dma);
 		if (err) {
 			USBHIST_LOG(ehcidebug,
 			    "alloc returned %d", err, 0, 0, 0);
 			mutex_exit(&sc->sc_lock);
 			return NULL;
+		}
 		for (i = 0; i < EHCI_ITD_CHUNK; i++) {
 			offs = i * EHCI_ITD_SIZE;
 			itd = KERNADDR(&dma, offs);
 			itd->physaddr = DMAADDR(&dma, offs);
 	 		itd->dma = dma;
 			itd->offs = offs;
 			LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
+		}
 		freeitd = LIST_FIRST(&sc->sc_freeitds);
+	}
 	itd = freeitd;
 	LIST_REMOVE(itd, u.free_list);
 	memset(&itd->itd, 0, sizeof(ehci_itd_t));
 	usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next),
 	    sizeof(itd->itd.itd_next),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	itd->u.frame_list.next = NULL;
 	itd->u.frame_list.prev = NULL;
 	itd->xfer_next = NULL;
 	itd->slot = 0;
 	mutex_exit(&sc->sc_lock);
 	return itd;
+}
 Static ehci_soft_sitd_t *
 ehci_alloc_sitd(ehci_softc_t *sc)
+{
 	struct ehci_soft_sitd *sitd, *freesitd;
 	usbd_status err;
 	int i, offs, frindex, previndex;
 	usb_dma_t dma;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	mutex_enter(&sc->sc_lock);
 	/*
 	 * Find an sitd that wasn't freed this frame or last frame. This can
 	 * discard sitds that were freed before frindex wrapped around
 	 * XXX - can this lead to thrashing? Could fix by enabling wrap-around
 	 *       interrupt and fiddling with list when that happens
 	 */
 	frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3;
 	previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize;
 	freesitd = NULL;
 	LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) {
 		if (sitd == NULL)
 			break;
 		if (sitd->slot != frindex && sitd->slot != previndex) {
 			freesitd = sitd;
 			break;
+		}
+	}
 	if (freesitd == NULL) {
 		USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0);
 		err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK,
 				EHCI_PAGE_SIZE, &dma);
 		if (err) {
 			USBHIST_LOG(ehcidebug,
 			    "alloc returned %d", err, 0, 0, 0);
 			mutex_exit(&sc->sc_lock);
 			return NULL;
+		}
 		for (i = 0; i < EHCI_SITD_CHUNK; i++) {
 			offs = i * EHCI_SITD_SIZE;
 			sitd = KERNADDR(&dma, offs);
 			sitd->physaddr = DMAADDR(&dma, offs);
 	 		sitd->dma = dma;
 			sitd->offs = offs;
 			LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list);
+		}
 		freesitd = LIST_FIRST(&sc->sc_freesitds);
+	}
 	sitd = freesitd;
 	LIST_REMOVE(sitd, u.free_list);
 	memset(&sitd->sitd, 0, sizeof(ehci_sitd_t));
 	usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next),
 		    sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE |
 		    BUS_DMASYNC_PREREAD);
 	sitd->u.frame_list.next = NULL;
 	sitd->u.frame_list.prev = NULL;
 	sitd->xfer_next = NULL;
 	sitd->slot = 0;
 	mutex_exit(&sc->sc_lock);
 	return sitd;
+}
 Static void
 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd)
+{
 	KASSERT(mutex_owned(&sc->sc_lock));
 	LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
+}
 Static void
 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd)
+{
 	KASSERT(mutex_owned(&sc->sc_lock));
 	LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list);
+}
 /****************/
 /*
  * Close a reqular pipe.
  * Assumes that there are no pending transactions.
  */
 Static void
 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
+{
 	struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	ehci_soft_qh_t *sqh = epipe->sqh;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	ehci_rem_qh(sc, sqh, head);
 	ehci_free_sqh(sc, epipe->sqh);
+}
 /*
  * Abort a device request.
  * If this routine is called at splusb() it guarantees that the request
  * will be removed from the hardware scheduling and that the callback
  * for it will be called with USBD_CANCELLED status.
  * It's impossible to guarantee that the requested transfer will not
  * have happened since the hardware runs concurrently.
  * If the transaction has already happened we rely on the ordinary
  * interrupt processing to process it.
  * XXX This is most probably wrong.
  * XXXMRG this doesn't make sense anymore.
  */
 Static void
 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
+{
 #define exfer EXFER(xfer)
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv;
 	ehci_soft_qh_t *sqh = epipe->sqh;
 	ehci_soft_qtd_t *sqtd;
 	ehci_physaddr_t cur;
 	uint32_t qhstatus;
 	int hit;
 	int wake;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	ASSERT_SLEEPABLE();
 	if (sc->sc_dying) {
 		/* If we're dying, just do the software part. */
 		xfer->ux_status = status;	/* make software ignore it */
 		callout_stop(&xfer->ux_callout);
 		usb_transfer_complete(xfer);
 		return;
+	}
 	/*
 	 * If an abort is already in progress then just wait for it to
 	 * complete and return.
 	 */
 	if (xfer->ux_hcflags & UXFER_ABORTING) {
 		USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0);
 #ifdef DIAGNOSTIC
 		if (status == USBD_TIMEOUT)
 			printf("ehci_abort_xfer: TIMEOUT while aborting\n");
 #endif
 		/* Override the status which might be USBD_TIMEOUT. */
 		xfer->ux_status = status;
 		USBHIST_LOG(ehcidebug, "waiting for abort to finish",
 , 0, 0, 0);
 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
 		while (xfer->ux_hcflags & UXFER_ABORTING)
 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
 		return;
+	}
 	xfer->ux_hcflags |= UXFER_ABORTING;
 	/*
 	 * Step 1: Make interrupt routine and hardware ignore xfer.
 	 */
 	xfer->ux_status = status;	/* make software ignore it */
 	callout_stop(&xfer->ux_callout);
 	usb_syncmem(&sqh->dma,
 	    sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
 	    sizeof(sqh->qh.qh_qtd.qtd_status),
 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 	qhstatus = sqh->qh.qh_qtd.qtd_status;
 	sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
 	usb_syncmem(&sqh->dma,
 	    sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
 	    sizeof(sqh->qh.qh_qtd.qtd_status),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) {
 		usb_syncmem(&sqtd->dma,
 		    sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 		    sizeof(sqtd->qtd.qtd_status),
 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 		sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
 		usb_syncmem(&sqtd->dma,
 		    sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
 		    sizeof(sqtd->qtd.qtd_status),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		if (sqtd == exfer->ex_sqtdend)
 			break;
+	}
 	/*
 	 * Step 2: Wait until we know hardware has finished any possible
 	 * use of the xfer.  Also make sure the soft interrupt routine
 	 * has run.
 	 */
 	ehci_sync_hc(sc);
 	sc->sc_softwake = 1;
 	usb_schedsoftintr(&sc->sc_bus);
 	cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
 	/*
 	 * Step 3: Remove any vestiges of the xfer from the hardware.
 	 * The complication here is that the hardware may have executed
 	 * beyond the xfer we're trying to abort.  So as we're scanning
 	 * the TDs of this xfer we check if the hardware points to
 	 * any of them.
 	 */
 	usb_syncmem(&sqh->dma,
 	    sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
 	    sizeof(sqh->qh.qh_curqtd),
 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 	cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
 	hit = 0;
 	for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) {
 		hit |= cur == sqtd->physaddr;
 		if (sqtd == exfer->ex_sqtdend)
 			break;
+	}
 	sqtd = sqtd->nextqtd;
 	/* Zap curqtd register if hardware pointed inside the xfer. */
 	if (hit && sqtd != NULL) {
 		USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0);
 		sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
 		usb_syncmem(&sqh->dma,
 		    sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
 		    sizeof(sqh->qh.qh_curqtd),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		sqh->qh.qh_qtd.qtd_status = qhstatus;
 		usb_syncmem(&sqh->dma,
 		    sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
 		    sizeof(sqh->qh.qh_qtd.qtd_status),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	} else {
 		USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0);
+	}
 	/*
 	 * Step 4: Execute callback.
 	 */
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = true;
 #endif
 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
 	usb_transfer_complete(xfer);
 	if (wake) {
 		cv_broadcast(&xfer->ux_hccv);
+	}
 	KASSERT(mutex_owned(&sc->sc_lock));
 #undef exfer
+}
 Static void
 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status)
+{
 	ehci_isoc_trans_t trans_status;
 	struct ehci_pipe *epipe;
 	struct ehci_xfer *exfer;
 	ehci_softc_t *sc;
 	struct ehci_soft_itd *itd;
 	struct ehci_soft_sitd *sitd;
 	int i, wake;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	epipe = (struct ehci_pipe *) xfer->ux_pipe;
 	exfer = EXFER(xfer);
 	sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv;
 	USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	if (sc->sc_dying) {
 		xfer->ux_status = status;
 		callout_stop(&xfer->ux_callout);
 		usb_transfer_complete(xfer);
 		return;
+	}
 	if (xfer->ux_hcflags & UXFER_ABORTING) {
 		USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0);
 #ifdef DIAGNOSTIC
 		if (status == USBD_TIMEOUT)
 			printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n");
 #endif
 		xfer->ux_status = status;
 		USBHIST_LOG(ehcidebug,
 		    "waiting for abort to finish", 0, 0, 0, 0);
 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
 		while (xfer->ux_hcflags & UXFER_ABORTING)
 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
 		goto done;
+	}
 	xfer->ux_hcflags |= UXFER_ABORTING;
 	xfer->ux_status = status;
 	callout_stop(&xfer->ux_callout);
 	if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) {
 		for (itd = exfer->ex_itdstart; itd != NULL;
 		     itd = itd->xfer_next) {
 			usb_syncmem(&itd->dma,
 			    itd->offs + offsetof(ehci_itd_t, itd_ctl),
 			    sizeof(itd->itd.itd_ctl),
 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 			for (i = 0; i < 8; i++) {
 				trans_status = le32toh(itd->itd.itd_ctl[i]);
 				trans_status &= ~EHCI_ITD_ACTIVE;
 				itd->itd.itd_ctl[i] = htole32(trans_status);
+			}
 			usb_syncmem(&itd->dma,
 			    itd->offs + offsetof(ehci_itd_t, itd_ctl),
 			    sizeof(itd->itd.itd_ctl),
 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
+		}
 	} else {
 		for (sitd = exfer->ex_sitdstart; sitd != NULL;
 		     sitd = sitd->xfer_next) {
 			usb_syncmem(&sitd->dma,
 			    sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
 			    sizeof(sitd->sitd.sitd_buffer),
 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 			trans_status = le32toh(sitd->sitd.sitd_trans);
 			trans_status &= ~EHCI_SITD_ACTIVE;
 			sitd->sitd.sitd_trans = htole32(trans_status);
 			usb_syncmem(&sitd->dma,
 			    sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
 			    sizeof(sitd->sitd.sitd_buffer),
 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
+		}
+	}
 	sc->sc_softwake = 1;
 	usb_schedsoftintr(&sc->sc_bus);
 	cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = true;
 #endif
 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
 	usb_transfer_complete(xfer);
 	if (wake) {
 		cv_broadcast(&xfer->ux_hccv);
+	}
 done:
 	KASSERT(mutex_owned(&sc->sc_lock));
 	return;
+}
 Static void
 ehci_timeout(void *addr)
+{
 	struct ehci_xfer *exfer = addr;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe;
 	ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0);
 #ifdef EHCI_DEBUG
 	if (ehcidebug > 1)
 		usbd_dump_pipe(exfer->ex_xfer.ux_pipe);
 #endif
 	if (sc->sc_dying) {
 		mutex_enter(&sc->sc_lock);
 		ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT);
 		mutex_exit(&sc->sc_lock);
 		return;
+	}
 	/* Execute the abort in a process context. */
 	usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr,
 	    USB_TASKQ_MPSAFE);
 	usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask,
 	    USB_TASKQ_HC);
+}
 Static void
 ehci_timeout_task(void *addr)
+{
 	usbd_xfer_handle xfer = addr;
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0);
 	mutex_enter(&sc->sc_lock);
 	ehci_abort_xfer(xfer, USBD_TIMEOUT);
 	mutex_exit(&sc->sc_lock);
+}
 /************************/
 Static usbd_status
 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	/* Insert last in queue. */
 	mutex_enter(&sc->sc_lock);
 	err = usb_insert_transfer(xfer);
 	mutex_exit(&sc->sc_lock);
 	if (err)
 		return err;
 	/* Pipe isn't running, start first */
 	return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
+}
 Static usbd_status
 ehci_device_ctrl_start(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
 	err = ehci_device_request(xfer);
 	if (err) {
 		return err;
+	}
 	if (sc->sc_bus.ub_usepolling)
 		ehci_waitintr(sc, xfer);
 	return USBD_IN_PROGRESS;
+}
 Static void
 ehci_device_ctrl_done(usbd_xfer_handle xfer)
+{
 	struct ehci_xfer *ex = EXFER(xfer);
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	usb_device_request_t *req = &xfer->ux_request;
 	int len = UGETW(req->wLength);
 	int rd = req->bmRequestType & UT_READ;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
 	if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) {
 		ehci_del_intr_list(sc, ex);	/* remove from active list */
 		ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL);
 		usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req),
 		    BUS_DMASYNC_POSTWRITE);
 		if (len)
 			usb_syncmem(&xfer->ux_dmabuf, 0, len,
 			    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+	}
 	USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0);
+}
 /* Abort a device control request. */
 Static void
 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
+{
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0);
 	ehci_abort_xfer(xfer, USBD_CANCELLED);
+}
 /* Close a device control pipe. */
 Static void
 ehci_device_ctrl_close(usbd_pipe_handle pipe)
+{
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	/*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0);
 	ehci_close_pipe(pipe, sc->sc_async_head);
+}
 Static usbd_status
 ehci_device_request(usbd_xfer_handle xfer)
+{
 #define exfer EXFER(xfer)
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	usb_device_request_t *req = &xfer->ux_request;
 	usbd_device_handle dev = epipe->pipe.up_dev;
 	ehci_softc_t *sc = dev->ud_bus->ub_hcpriv;
 	ehci_soft_qtd_t *setup, *stat, *next;
 	ehci_soft_qh_t *sqh;
 	int isread;
 	int len;
 	usbd_status err;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	isread = req->bmRequestType & UT_READ;
 	len = UGETW(req->wLength);
 	USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, "
 	    "wValue=0x%04x, wIndex=0x%04x",
 	    req->bmRequestType, req->bRequest, UGETW(req->wValue),
 	    UGETW(req->wIndex));
 	USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d",
 	    len, dev->ud_addr,
 	    epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0);
 	setup = ehci_alloc_sqtd(sc);
 	if (setup == NULL) {
 		err = USBD_NOMEM;
 		goto bad1;
+	}
 	stat = ehci_alloc_sqtd(sc);
 	if (stat == NULL) {
 		err = USBD_NOMEM;
 		goto bad2;
+	}
 	mutex_enter(&sc->sc_lock);
 	sqh = epipe->sqh;
 	KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr,
-	    "address QH %d pipe %d\n",
+	    "address QH %" __PRIuBIT " pipe %d\n",
 	    EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr);
 	KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) ==
 	    UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
-	    "MPS QH %d pipe %d\n",
+	    "MPS QH %" __PRIuBIT " pipe %d\n",
 	    EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)),
 	    UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
 	/* Set up data transaction */
 	if (len != 0) {
 		ehci_soft_qtd_t *end;
 		/* Start toggle at 1. */
 		epipe->nexttoggle = 1;
 		err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
 			  &next, &end);
 		if (err)
 			goto bad3;
 		end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
 		end->nextqtd = stat;
 		end->qtd.qtd_next = end->qtd.qtd_altnext =
 		    htole32(stat->physaddr);
 		usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
 		   BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	} else {
 		next = stat;
+	}
 	memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req));
 	usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
 	/* Clear toggle */
 	setup->qtd.qtd_status = htole32(
 	    EHCI_QTD_ACTIVE |
 	    EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
 	    EHCI_QTD_SET_CERR(3) |
 	    EHCI_QTD_SET_TOGGLE(0) |
 	    EHCI_QTD_SET_BYTES(sizeof(*req))
 	    );
 	setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
 	setup->qtd.qtd_buffer_hi[0] = 0;
 	setup->nextqtd = next;
 	setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
 	setup->xfer = xfer;
 	setup->len = sizeof(*req);
 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	stat->qtd.qtd_status = htole32(
 	    EHCI_QTD_ACTIVE |
 	    EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
 	    EHCI_QTD_SET_CERR(3) |
 	    EHCI_QTD_SET_TOGGLE(1) |
 	    EHCI_QTD_IOC
 	    );
 	stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
 	stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
 	stat->nextqtd = NULL;
 	stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
 	stat->xfer = xfer;
 	stat->len = 0;
 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(setup);
 #endif
 	exfer->ex_sqtdstart = setup;
 	exfer->ex_sqtdend = stat;
 	KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = false;
 #endif
 	/* Insert qTD in QH list. */
 	ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */
 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
 		    ehci_timeout, xfer);
+	}
 	ehci_add_intr_list(sc, exfer);
 	xfer->ux_status = USBD_IN_PROGRESS;
 	mutex_exit(&sc->sc_lock);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:",
 	    EOREAD4(sc, EHCI_USBSTS), 0, 0, 0);
 //	delay(10000);
 	ehci_dump_regs(sc);
 	ehci_dump_sqh(sc->sc_async_head);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(setup);
 #endif
 	return USBD_NORMAL_COMPLETION;
  bad3:
 	mutex_exit(&sc->sc_lock);
 	ehci_free_sqtd(sc, stat);
  bad2:
 	ehci_free_sqtd(sc, setup);
  bad1:
 	USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0);
 	mutex_enter(&sc->sc_lock);
 	xfer->ux_status = err;
 	usb_transfer_complete(xfer);
 	mutex_exit(&sc->sc_lock);
 	return err;
 #undef exfer
+}
 /*
  * Some EHCI chips from VIA seem to trigger interrupts before writing back the
  * qTD status, or miss signalling occasionally under heavy load.  If the host
  * machine is too fast, we we can miss transaction completion - when we scan
  * the active list the transaction still seems to be active.  This generally
  * exhibits itself as a umass stall that never recovers.
+ *
  * We work around this behaviour by setting up this callback after any softintr
  * that completes with transactions still pending, giving us another chance to
  * check for completion after the writeback has taken place.
  */
 Static void
 ehci_intrlist_timeout(void *arg)
+{
 	ehci_softc_t *sc = arg;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	usb_schedsoftintr(&sc->sc_bus);
+}
 /************************/
 Static usbd_status
 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	/* Insert last in queue. */
 	mutex_enter(&sc->sc_lock);
 	err = usb_insert_transfer(xfer);
 	mutex_exit(&sc->sc_lock);
 	if (err)
 		return err;
 	/* Pipe isn't running, start first */
 	return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
+}
 Static usbd_status
 ehci_device_bulk_start(usbd_xfer_handle xfer)
+{
 #define exfer EXFER(xfer)
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	usbd_device_handle dev = epipe->pipe.up_dev;
 	ehci_softc_t *sc = dev->ud_bus->ub_hcpriv;
 	ehci_soft_qtd_t *data, *dataend;
 	ehci_soft_qh_t *sqh;
 	usbd_status err;
 	int len, isread, endpt;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d",
 	    xfer, xfer->ux_length, xfer->ux_flags, 0);
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
 	mutex_enter(&sc->sc_lock);
 	len = xfer->ux_length;
 	endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
 	sqh = epipe->sqh;
 	epipe->u.bulk.length = len;
 	err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
 				   &dataend);
 	if (err) {
 		USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0);
 		xfer->ux_status = err;
 		usb_transfer_complete(xfer);
 		mutex_exit(&sc->sc_lock);
 		return err;
+	}
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(data);
 	USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
 #endif
 	/* Set up interrupt info. */
 	exfer->ex_sqtdstart = data;
 	exfer->ex_sqtdend = dataend;
 	KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = false;
 #endif
 	ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
 		    ehci_timeout, xfer);
+	}
 	ehci_add_intr_list(sc, exfer);
 	xfer->ux_status = USBD_IN_PROGRESS;
 	mutex_exit(&sc->sc_lock);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0);
 //	delay(10000);
 	USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0);
 	ehci_dump_regs(sc);
 #if 0
 	printf("async_head:\n");
 	ehci_dump_sqh(sc->sc_async_head);
 #endif
 	USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(data);
 #endif
 	if (sc->sc_bus.ub_usepolling)
 		ehci_waitintr(sc, xfer);
 	return USBD_IN_PROGRESS;
 #undef exfer
+}
 Static void
 ehci_device_bulk_abort(usbd_xfer_handle xfer)
+{
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0);
 	ehci_abort_xfer(xfer, USBD_CANCELLED);
+}
 /*
  * Close a device bulk pipe.
  */
 Static void
 ehci_device_bulk_close(usbd_pipe_handle pipe)
+{
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0);
 	pipe->up_endpoint->ue_toggle = epipe->nexttoggle;
 	ehci_close_pipe(pipe, sc->sc_async_head);
+}
 Static void
 ehci_device_bulk_done(usbd_xfer_handle xfer)
+{
 	struct ehci_xfer *ex = EXFER(xfer);
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d",
 	    xfer, xfer->ux_actlen, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) {
 		ehci_del_intr_list(sc, ex);	/* remove from active list */
 		ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL);
 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+	}
 	USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0);
+}
 /************************/
 Static usbd_status
 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
+{
 	struct ehci_soft_islot *isp;
 	int islot, lev;
 	/* Find a poll rate that is large enough. */
 	for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
 		if (EHCI_ILEV_IVAL(lev) <= ival)
 			break;
 	/* Pick an interrupt slot at the right level. */
 	/* XXX could do better than picking at random */
 	sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
 	islot = EHCI_IQHIDX(lev, sc->sc_rand);
 	sqh->islot = islot;
 	isp = &sc->sc_islots[islot];
 	mutex_enter(&sc->sc_lock);
 	ehci_add_qh(sc, sqh, isp->sqh);
 	mutex_exit(&sc->sc_lock);
 	return USBD_NORMAL_COMPLETION;
+}
 Static usbd_status
 ehci_device_intr_transfer(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	/* Insert last in queue. */
 	mutex_enter(&sc->sc_lock);
 	err = usb_insert_transfer(xfer);
 	mutex_exit(&sc->sc_lock);
 	if (err)
 		return err;
 	/*
 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
 	 * so start it first.
 	 */
 	return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
+}
 Static usbd_status
 ehci_device_intr_start(usbd_xfer_handle xfer)
+{
 #define exfer EXFER(xfer)
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	usbd_device_handle dev = xfer->ux_pipe->up_dev;
 	ehci_softc_t *sc = dev->ud_bus->ub_hcpriv;
 	ehci_soft_qtd_t *data, *dataend;
 	ehci_soft_qh_t *sqh;
 	usbd_status err;
 	int len, isread, endpt;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d",
 	    xfer, xfer->ux_length, xfer->ux_flags, 0);
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
 	mutex_enter(&sc->sc_lock);
 	len = xfer->ux_length;
 	endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
 	sqh = epipe->sqh;
 	epipe->u.intr.length = len;
 	err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
 	    &dataend);
 	if (err) {
 		USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0);
 		xfer->ux_status = err;
 		usb_transfer_complete(xfer);
 		mutex_exit(&sc->sc_lock);
 		return err;
+	}
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(data);
 	USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
 #endif
 	/* Set up interrupt info. */
 	exfer->ex_sqtdstart = data;
 	exfer->ex_sqtdend = dataend;
 	KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = false;
 #endif
 	ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
 		    ehci_timeout, xfer);
+	}
 	ehci_add_intr_list(sc, exfer);
 	xfer->ux_status = USBD_IN_PROGRESS;
 	mutex_exit(&sc->sc_lock);
 #ifdef EHCI_DEBUG
 	USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0);
 //	delay(10000);
 	USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0);
 	ehci_dump_regs(sc);
 	USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0);
 	ehci_dump_sqh(sqh);
 	ehci_dump_sqtds(data);
 #endif
 	if (sc->sc_bus.ub_usepolling)
 		ehci_waitintr(sc, xfer);
 	return USBD_IN_PROGRESS;
 #undef exfer
+}
 Static void
 ehci_device_intr_abort(usbd_xfer_handle xfer)
+{
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0);
 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
 	/*
 	 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
 	 *       async doorbell. That's dependent on the async list, wheras
 	 *       intr xfers are periodic, should not use this?
 	 */
 	ehci_abort_xfer(xfer, USBD_CANCELLED);
+}
 Static void
 ehci_device_intr_close(usbd_pipe_handle pipe)
+{
 	ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
 	struct ehci_soft_islot *isp;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	isp = &sc->sc_islots[epipe->sqh->islot];
 	ehci_close_pipe(pipe, isp->sqh);
+}
 Static void
 ehci_device_intr_done(usbd_xfer_handle xfer)
+{
 #define exfer EXFER(xfer)
 	struct ehci_xfer *ex = EXFER(xfer);
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	ehci_soft_qtd_t *data, *dataend;
 	ehci_soft_qh_t *sqh;
 	usbd_status err;
 	int len, isread, endpt;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d",
 	    xfer, xfer->ux_actlen, 0, 0);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	if (xfer->ux_pipe->up_repeat) {
 		ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL);
 		len = epipe->u.intr.length;
 		xfer->ux_length = len;
 		endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 		isread = UE_GET_DIR(endpt) == UE_DIR_IN;
 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
 		sqh = epipe->sqh;
 		err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
 		    &data, &dataend);
 		if (err) {
 			USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0);
 			xfer->ux_status = err;
 			return;
+		}
 		/* Set up interrupt info. */
 		exfer->ex_sqtdstart = data;
 		exfer->ex_sqtdend = dataend;
 		KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 		exfer->ex_isdone = false;
 #endif
 		ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
 		if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
 			callout_reset(&xfer->ux_callout,
 			    mstohz(xfer->ux_timeout), ehci_timeout, xfer);
+		}
 		xfer->ux_status = USBD_IN_PROGRESS;
 	} else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) {
 		ehci_del_intr_list(sc, ex); /* remove from active list */
 		ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL);
 		endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 		isread = UE_GET_DIR(endpt) == UE_DIR_IN;
 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+	}
 #undef exfer
+}
 /************************/
 Static usbd_status
 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer)
+{
 	usbd_status err;
 	err = usb_insert_transfer(xfer);
 	if (err && err != USBD_IN_PROGRESS)
 		return err;
 	return ehci_device_fs_isoc_start(xfer);
+}
 Static usbd_status
 ehci_device_fs_isoc_start(usbd_xfer_handle xfer)
+{
 	struct ehci_pipe *epipe;
 	usbd_device_handle dev;
 	ehci_softc_t *sc;
 	struct ehci_xfer *exfer;
 	ehci_soft_sitd_t *sitd, *prev, *start, *stop;
 	usb_dma_t *dma_buf;
 	int i, j, k, frames;
 	int offs, total_length;
 	int frindex;
 	u_int huba, dir;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	start = NULL;
 	prev = NULL;
 	sitd = NULL;
 	total_length = 0;
 	exfer = (struct ehci_xfer *) xfer;
 	sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	dev = xfer->ux_pipe->up_dev;
 	epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	/*
 	 * To allow continuous transfers, above we start all transfers
 	 * immediately. However, we're still going to get usbd_start_next call
 	 * this when another xfer completes. So, check if this is already
 	 * in progress or not
 	 */
 	if (exfer->ex_sitdstart != NULL)
 		return USBD_IN_PROGRESS;
 	USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d",
 	    xfer, xfer->ux_length, xfer->ux_flags, 0);
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	/*
 	 * To avoid complication, don't allow a request right now that'll span
 	 * the entire frame table. To within 4 frames, to allow some leeway
 	 * on either side of where the hc currently is.
 	 */
 	if (epipe->pipe.up_endpoint->ue_edesc->bInterval *
 			xfer->ux_nframes >= sc->sc_flsize - 4) {
 		printf("ehci: isoc descriptor requested that spans the entire"
 		    "frametable, too many frames\n");
 		return USBD_INVAL;
+	}
 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
 	KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = false;
 #endif
 	/*
 	 * Step 1: Allocate and initialize sitds.
 	 */
 	i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
 	if (i > 16 || i == 0) {
 		/* Spec page 271 says intervals > 16 are invalid */
 		USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0);
 		return USBD_INVAL;
+	}
 	frames = xfer->ux_nframes;
 	if (frames == 0) {
 		USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0);
 		return USBD_INVAL;
+	}
 	dma_buf = &xfer->ux_dmabuf;
 	offs = 0;
 	for (i = 0; i < frames; i++) {
 		sitd = ehci_alloc_sitd(sc);
 		if (prev)
 			prev->xfer_next = sitd;
 		else
 			start = sitd;
 #ifdef DIAGNOSTIC
 		if (xfer->ux_frlengths[i] > 0x3ff) {
 			printf("ehci: invalid frame length\n");
 			xfer->ux_frlengths[i] = 0x3ff;
+		}
 #endif
 		sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE |
 		    EHCI_SITD_SET_LEN(xfer->ux_frlengths[i]));
 		/* Set page0 index and offset. */
 		sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs));
 		total_length += xfer->ux_frlengths[i];
 		offs += xfer->ux_frlengths[i];
 		sitd->sitd.sitd_buffer[1] =
 		    htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1)));
 		huba = dev->ud_myhsport->up_parent->ud_addr;
 /*		if (sc->sc_flags & EHCIF_FREESCALE) {
 			// Set hub address to 0 if embedded TT is used.
 			if (huba == sc->sc_addr)
 				huba = 0;
+		}
 */
 		k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
 		dir = UE_GET_DIR(k) ? 1 : 0;
 		sitd->sitd.sitd_endp =
 		    htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) |
 		    EHCI_SITD_SET_DADDR(dev->ud_addr) |
 		    EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) |
 		    EHCI_SITD_SET_HUBA(huba) |
 		    EHCI_SITD_SET_DIR(dir));
 		sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE);
 		/* XXX */
 		u_char sa, sb;
 		u_int temp, tlen;
 		sa = 0;
 		if (dir == 0) {	/* OUT */
 			temp = 0;
 			tlen = xfer->ux_frlengths[i];
 			if (tlen <= 188) {
 				temp |= 1;	/* T-count = 1, TP = ALL */
 				tlen = 1;
 			} else {
 				tlen += 187;
 				tlen /= 188;
 				temp |= tlen;	/* T-count = [1..6] */
 				temp |= 8;	/* TP = Begin */
+			}
 			sitd->sitd.sitd_buffer[1] |= htole32(temp);
 			tlen += sa;
 			if (tlen >= 8) {
 				sb = 0;
 			} else {
 				sb = (1 << tlen);
+			}
 			sa = (1 << sa);
 			sa = (sb - sa) & 0x3F;
 			sb = 0;
 		} else {
 			sb = (-(4 << sa)) & 0xFE;
 			sa = (1 << sa) & 0x3F;
 			sa = 0x01;
 			sb = 0xfc;
+		}
 		sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) |
 		    EHCI_SITD_SET_CMASK(sb));
 		prev = sitd;
 	} /* End of frame */
 	sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC);
 	stop = sitd;
 	stop->xfer_next = NULL;
 	usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length,
 		BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	/*
 	 * Part 2: Transfer descriptors have now been set up, now they must
 	 * be scheduled into the periodic frame list. Erk. Not wanting to
 	 * complicate matters, transfer is denied if the transfer spans
 	 * more than the period frame list.
 	 */
 	mutex_enter(&sc->sc_lock);
 	/* Start inserting frames */
 	if (epipe->u.isoc.cur_xfers > 0) {
 		frindex = epipe->u.isoc.next_frame;
 	} else {
 		frindex = EOREAD4(sc, EHCI_FRINDEX);
 		frindex = frindex >> 3; /* Erase microframe index */
 		frindex += 2;
+	}
 	if (frindex >= sc->sc_flsize)
 		frindex &= (sc->sc_flsize - 1);
 	/* Whats the frame interval? */
 	i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
 	sitd = start;
 	for (j = 0; j < frames; j++) {
 		if (sitd == NULL)
 			panic("ehci: unexpectedly ran out of isoc sitds\n");
 		sitd->sitd.sitd_next = sc->sc_flist[frindex];
 		if (sitd->sitd.sitd_next == 0)
 			/* FIXME: frindex table gets initialized to NULL
 			 * or EHCI_NULL? */
 			sitd->sitd.sitd_next = EHCI_NULL;
 		usb_syncmem(&sitd->dma,
 		    sitd->offs + offsetof(ehci_sitd_t, sitd_next),
 		    sizeof(ehci_sitd_t),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		sc->sc_flist[frindex] =
 		    htole32(EHCI_LINK_SITD | sitd->physaddr);
 		usb_syncmem(&sc->sc_fldma,
 		    sizeof(ehci_link_t) * frindex,
 		    sizeof(ehci_link_t),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		sitd->u.frame_list.next = sc->sc_softsitds[frindex];
 		sc->sc_softsitds[frindex] = sitd;
 		if (sitd->u.frame_list.next != NULL)
 			sitd->u.frame_list.next->u.frame_list.prev = sitd;
 		sitd->slot = frindex;
 		sitd->u.frame_list.prev = NULL;
 		frindex += i;
 		if (frindex >= sc->sc_flsize)
 			frindex -= sc->sc_flsize;
 		sitd = sitd->xfer_next;
+	}
 	epipe->u.isoc.cur_xfers++;
 	epipe->u.isoc.next_frame = frindex;
 	exfer->ex_sitdstart = start;
 	exfer->ex_sitdend = stop;
 	ehci_add_intr_list(sc, exfer);
 	xfer->ux_status = USBD_IN_PROGRESS;
 	xfer->ux_done = 0;
 	mutex_exit(&sc->sc_lock);
 	if (sc->sc_bus.ub_usepolling) {
 		printf("Starting ehci isoc xfer with polling. Bad idea?\n");
 		ehci_waitintr(sc, xfer);
+	}
 	return USBD_IN_PROGRESS;
+}
 Static void
 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer)
+{
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0);
 	ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
+}
 Static void
 ehci_device_fs_isoc_close(usbd_pipe_handle pipe)
+{
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0);
+}
 Static void
 ehci_device_fs_isoc_done(usbd_xfer_handle xfer)
+{
 	struct ehci_xfer *exfer;
 	ehci_softc_t *sc;
 	struct ehci_pipe *epipe;
 	exfer = EXFER(xfer);
 	sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	epipe = (struct ehci_pipe *) xfer->ux_pipe;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	epipe->u.isoc.cur_xfers--;
 	if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) {
 		ehci_del_intr_list(sc, exfer);
 		ehci_rem_free_sitd_chain(sc, exfer);
+	}
 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE |
 		    BUS_DMASYNC_POSTREAD);
+}
 Static usbd_status
 ehci_device_isoc_transfer(usbd_xfer_handle xfer)
+{
 	ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	usbd_status err;
 	mutex_enter(&sc->sc_lock);
 	err = usb_insert_transfer(xfer);
 	mutex_exit(&sc->sc_lock);
 	if (err && err != USBD_IN_PROGRESS)
 		return err;
 	return ehci_device_isoc_start(xfer);
+}
 Static usbd_status
 ehci_device_isoc_start(usbd_xfer_handle xfer)
+{
 	struct ehci_pipe *epipe;
 	ehci_softc_t *sc;
 	struct ehci_xfer *exfer;
 	ehci_soft_itd_t *itd, *prev, *start, *stop;
 	usb_dma_t *dma_buf;
 	int i, j, k, frames, uframes, ufrperframe;
 	int trans_count, offs, total_length;
 	int frindex;
 	USBHIST_FUNC(); USBHIST_CALLED(ehcidebug);
 	start = NULL;
 	prev = NULL;
 	itd = NULL;
 	trans_count = 0;
 	total_length = 0;
 	exfer = (struct ehci_xfer *) xfer;
 	sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
 	epipe = (struct ehci_pipe *)xfer->ux_pipe;
 	/*
 	 * To allow continuous transfers, above we start all transfers
 	 * immediately. However, we're still going to get usbd_start_next call
 	 * this when another xfer completes. So, check if this is already
 	 * in progress or not
 	 */
 	if (exfer->ex_itdstart != NULL)
 		return USBD_IN_PROGRESS;
 	USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d",
 	    xfer, xfer->ux_length, xfer->ux_flags, 0);
 	if (sc->sc_dying)
 		return USBD_IOERROR;
 	/*
 	 * To avoid complication, don't allow a request right now that'll span
 	 * the entire frame table. To within 4 frames, to allow some leeway
 	 * on either side of where the hc currently is.
 	 */
 	if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) *
 			xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) {
 		USBHIST_LOG(ehcidebug,
 		    "isoc descriptor spans entire frametable", 0, 0, 0, 0);
 		printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
 		return USBD_INVAL;
+	}
 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
 	KASSERT(exfer->ex_isdone);
 #ifdef DIAGNOSTIC
 	exfer->ex_isdone = false;
 #endif
 	/*
 	 * Step 1: Allocate and initialize itds, how many do we need?
 	 * One per transfer if interval >= 8 microframes, fewer if we use
 	 * multiple microframes per frame.
 	 */
 	i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
 	if (i > 16 || i == 0) {
 		/* Spec page 271 says intervals > 16 are invalid */
 		USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0);
 		return USBD_INVAL;
+	}
 	ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
 	frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe;
 	uframes = USB_UFRAMES_PER_FRAME / ufrperframe;
 	if (frames == 0) {
 		USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0);
 		return USBD_INVAL;
+	}
 	dma_buf = &xfer->ux_dmabuf;
 	offs = 0;
 	for (i = 0; i < frames; i++) {
 		int froffs = offs;
 		itd = ehci_alloc_itd(sc);
 		if (prev != NULL) {
 			prev->itd.itd_next =
 			    htole32(itd->physaddr | EHCI_LINK_ITD);
 			usb_syncmem(&itd->dma,
 			    itd->offs + offsetof(ehci_itd_t, itd_next),
 			    sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE);
 			prev->xfer_next = itd;
 	    	} else {
 			start = itd;
+		}
 		/*
 		 * Step 1.5, initialize uframes
 		 */
 		for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) {
 			/* Calculate which page in the list this starts in */
 			int addr = DMAADDR(dma_buf, froffs);
 			addr = EHCI_PAGE_OFFSET(addr);
 			addr += (offs - froffs);
 			addr = EHCI_PAGE(addr);
 			addr /= EHCI_PAGE_SIZE;
 			/*
 			 * This gets the initial offset into the first page,
 			 * looks how far further along the current uframe
 			 * offset is. Works out how many pages that is.
 			 */
 			itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
 			    EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) |
 			    EHCI_ITD_SET_PG(addr) |
 			    EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
 			total_length += xfer->ux_frlengths[trans_count];
 			offs += xfer->ux_frlengths[trans_count];
 			trans_count++;
 			if (trans_count >= xfer->ux_nframes) { /*Set IOC*/
 				itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
 				break;
+			}
+		}
 		/*
 		 * Step 1.75, set buffer pointers. To simplify matters, all
 		 * pointers are filled out for the next 7 hardware pages in
 		 * the dma block, so no need to worry what pages to cover
 		 * and what to not.
 		 */
 		for (j = 0; j < EHCI_ITD_NBUFFERS; j++) {
 			/*
 			 * Don't try to lookup a page that's past the end
 			 * of buffer
 			 */
 			int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
 			if (page_offs >= dma_buf->udma_block->size)
 				break;
 			unsigned long long page = DMAADDR(dma_buf, page_offs);
 			page = EHCI_PAGE(page);
 			itd->itd.itd_bufr[j] =
 			    htole32(EHCI_ITD_SET_BPTR(page));
 			itd->itd.itd_bufr_hi[j] =
 			    htole32(page >> 32);
+		}
 		/*
 		 * Other special values
 		 */

 @@ -1,405 +1,433 @@
-/*	$NetBSD: ehcireg.h,v 1.34.14.5 2015/03/03 06:36:53 skrll Exp $	*/
+/*	$NetBSD: ehcireg.h,v 1.34.14.6 2015/03/03 10:06:01 skrll Exp $	*/
 /*
  * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net).
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * The EHCI 0.96 spec can be found at
  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
  * and the USB 2.0 spec at
  * http://www.usb.org/developers/data/usb_20.zip
  */
 #ifndef _DEV_PCI_EHCIREG_H_
 #define _DEV_PCI_EHCIREG_H_
 /*** PCI config registers ***/
 #define PCI_CBMEM		0x10	/* configuration base MEM */
 #define PCI_INTERFACE_EHCI	0x20
 #define PCI_USBREV		0x60	/* RO USB protocol revision */
 #define  PCI_USBREV_MASK	0xff
 #define  PCI_USBREV_PRE_1_0	0x00
 #define  PCI_USBREV_1_0		0x10
 #define  PCI_USBREV_1_1		0x11
 #define  PCI_USBREV_2_0		0x20
 #define PCI_EHCI_FLADJ		0x61	/*RW Frame len adj, SOF=59488+6*fladj */
 #define PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
 /* Regs at EECP + offset */
 #define PCI_EHCI_USBLEGSUP	0x00
 #define  EHCI_LEG_HC_OS_OWNED		0x01000000
 #define  EHCI_LEG_HC_BIOS_OWNED		0x00010000
 #define PCI_EHCI_USBLEGCTLSTS	0x04
 #define  EHCI_LEG_EXT_SMI_BAR		0x80000000
 #define  EHCI_LEG_EXT_SMI_PCICMD	0x40000000
 #define  EHCI_LEG_EXT_SMI_OS_CHANGE	0x20000000
 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff)
 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff)
 #define EHCI_CAP_ID_LEGACY 1
 /*** EHCI capability registers ***/
 #define EHCI_CAPLENGTH		0x00	/*RO Capability register length field */
 /* reserved			0x01 */
 #define EHCI_HCIVERSION		0x02	/* RO Interface version number */
 #define EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
 #define  EHCI_HCS_N_TT(x)	(((x) >> 20) & 0xf) /* # of xacts xlater ETTF */
 #define  EHCI_HCS_N_PTT(x)	(((x) >> 20) & 0xf) /* ports per xlater ETTF */
 #define  EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
 #define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf) /* # of companion ctlrs */
 #define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf) /* # of ports per comp. */
 #define  EHCI_HCS_PPC(x)	((x) & 0x10) /* port power control */
 #define  EHCI_HCS_N_PORTS(x)	((x) & 0xf) /* # of ports */
 #define EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
 #define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff) /* extended ports caps */
 #define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf) /* isoc sched threshold */
 #define  EHCI_HCC_ASPC(x)	((x) & 0x4) /* async sched park cap */
 #define  EHCI_HCC_PFLF(x)	((x) & 0x2) /* prog frame list flag */
 #define  EHCI_HCC_64BIT(x)	((x) & 0x1) /* 64 bit address cap */
 #define EHCI_HCSP_PORTROUTE	0x0c	/*RO Companion port route description */
 /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
 #define EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
 #define  EHCI_CMD_ITC_M		0x00ff0000 /* RW interrupt threshold ctrl */
 #define   EHCI_CMD_ITC_1	0x00010000
 #define   EHCI_CMD_ITC_2	0x00020000
 #define   EHCI_CMD_ITC_4	0x00040000
 #define   EHCI_CMD_ITC_8	0x00080000
 #define   EHCI_CMD_ITC_16	0x00100000
 #define   EHCI_CMD_ITC_32	0x00200000
 #define   EHCI_CMD_ITC_64	0x00400000
 #define  EHCI_CMD_ASPME		0x00000800 /* RW/RO async park enable */
 #define  EHCI_CMD_ASPMC		0x00000300 /* RW/RO async park count */
 #define  EHCI_CMD_LHCR		0x00000080 /* RW light host ctrl reset */
 #define  EHCI_CMD_IAAD		0x00000040 /* RW intr on async adv door bell */
 #define  EHCI_CMD_ASE		0x00000020 /* RW async sched enable */
 #define  EHCI_CMD_PSE		0x00000010 /* RW periodic sched enable */
 #define  EHCI_CMD_FLS_M		0x0000000c /* RW/RO frame list size */
 #define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3) /* RW/RO frame list size */
 #define  EHCI_CMD_HCRESET	0x00000002 /* RW reset */
 #define  EHCI_CMD_RS		0x00000001 /* RW run/stop */
 #define EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
 #define  EHCI_STS_ASS		0x00008000 /* RO async sched status */
 #define  EHCI_STS_PSS		0x00004000 /* RO periodic sched status */
 #define  EHCI_STS_REC		0x00002000 /* RO reclamation */
 #define  EHCI_STS_HCH		0x00001000 /* RO host controller halted */
 #define  EHCI_STS_IAA		0x00000020 /* RWC interrupt on async adv */
 #define  EHCI_STS_HSE		0x00000010 /* RWC host system error */
 #define  EHCI_STS_FLR		0x00000008 /* RWC frame list rollover */
 #define  EHCI_STS_PCD		0x00000004 /* RWC port change detect */
 #define  EHCI_STS_ERRINT	0x00000002 /* RWC error interrupt */
 #define  EHCI_STS_INT		0x00000001 /* RWC interrupt */
 #define  EHCI_STS_INTRS(x)	((x) & 0x3f)
 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
 #define EHCI_USBINTR		0x08	/* RW Interrupt register */
 #define EHCI_INTR_IAAE		0x00000020 /* interrupt on async advance ena */
 #define EHCI_INTR_HSEE		0x00000010 /* host system error ena */
 #define EHCI_INTR_FLRE		0x00000008 /* frame list rollover ena */
 #define EHCI_INTR_PCIE		0x00000004 /* port change ena */
 #define EHCI_INTR_UEIE		0x00000002 /* USB error intr ena */
 #define EHCI_INTR_UIE		0x00000001 /* USB intr ena */
 #define EHCI_FRINDEX		0x0c	/* RW Frame Index register */
 #define EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
 #define EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
 #define EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
 #define EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
 #define  EHCI_CONF_CF		0x00000001 /* RW configure flag */
 #define EHCI_PORTSC(n)		(0x40+4*(n)) /* RO, RW, RWC Port Status reg */
 #define  EHCI_PS_PSPD		0x0C000000 /* RO port speed (ETTF) */
 #define  EHCI_PS_PSPD_FS	0x00000000 /* Full speed (ETTF) */
 #define  EHCI_PS_PSPD_LS	0x04000000 /* Low speed (ETTF) */
 #define  EHCI_PS_PSPD_HS	0x08000000 /* High speed (ETTF) */
 #define  EHCI_PS_WKOC_E		0x00400000 /* RW wake on over current ena */
 #define  EHCI_PS_WKDSCNNT_E	0x00200000 /* RW wake on disconnect ena */
 #define  EHCI_PS_WKCNNT_E	0x00100000 /* RW wake on connect ena */
 #define  EHCI_PS_PTC		0x000f0000 /* RW port test control */
 #define  EHCI_PS_PIC		0x0000c000 /* RW port indicator control */
 #define  EHCI_PS_PO		0x00002000 /* RW port owner */
 #define  EHCI_PS_PP		0x00001000 /* RW,RO port power */
 #define  EHCI_PS_LS		0x00000c00 /* RO line status */
 #define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
 #define  EHCI_PS_PR		0x00000100 /* RW port reset */
 #define  EHCI_PS_SUSP		0x00000080 /* RW suspend */
 #define  EHCI_PS_FPR		0x00000040 /* RW force port resume */
 #define  EHCI_PS_OCC		0x00000020 /* RWC over current change */
 #define  EHCI_PS_OCA		0x00000010 /* RO over current active */
 #define  EHCI_PS_PEC		0x00000008 /* RWC port enable change */
 #define  EHCI_PS_PE		0x00000004 /* RW port enable */
 #define  EHCI_PS_CSC		0x00000002 /* RWC connect status change */
 #define  EHCI_PS_CS		0x00000001 /* RO connect status */
 #define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
 #define	EHCI_USBMODE		0xa8		/* USB Device mode */
 #define	  EHCI_USBMODE_SDIS	__BIT(4)	/* Stream disable mode 1=act */
 #define	  EHCI_USBMODE_SLOM	__BIT(3)	/* setup lockouts on */
 #define	  EHCI_USBMODE_ES	__BIT(2)	/* Endian Select ES=1 */
 #define	  EHCI_USBMODE_CM	__BITS(0,1)	/* Controller Mode */
 #define	  EHCI_USBMODE_CM_IDLE	0x00		/* Idle (combo host/device) */
 #define	  EHCI_USBMODE_CM_DEV	0x02		/* Device Controller */
 #define	  EHCI_USBMODE_CM_HOST	0x03		/* Host Controller */
 #define EHCI_FLALIGN_ALIGN	0x1000
 #define EHCI_MAX_PORTS		16 /* only 4 bits available in EHCI_HCS_N_PORTS */
 /* No data structure may cross a page boundary. */
 #define EHCI_PAGE_SHIFT		12
 #define EHCI_PAGE_SIZE		(1 << EHCI_PAGE_SHIFT)
 #define EHCI_PAGE_MASK		(EHCI_PAGE_SIZE - 1)
 #define EHCI_PAGE(x)		((x) & ~EHCI_PAGE_MASK)
 #define EHCI_PAGE_OFFSET(x)	((x) & EHCI_PAGE_MASK)
 #define EHCI_NPAGES(x)		(((x) + EHCI_PAGE_MASK) >> EHCI_PAGE_SHIFT)
 typedef uint32_t ehci_link_t;
-#define EHCI_LINK_TERMINATE	0x00000001
+#define EHCI_LINK_TERMINATE	__BIT(0)
 #define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
 #define  EHCI_LINK_ITD		0x0
 #define  EHCI_LINK_QH		0x2
 #define  EHCI_LINK_SITD		0x4
 #define  EHCI_LINK_FSTN		0x6
 #define EHCI_LINK_ADDR(x)	((x) &~ 0x1f)
 typedef uint32_t ehci_physaddr_t;
 typedef uint32_t ehci_isoc_trans_t;
 typedef uint32_t ehci_isoc_bufr_ptr_t;
 /* Isochronous Transfer Descriptor */
 #define EHCI_ITD_NUFRAMES USB_UFRAMES_PER_FRAME
 #define EHCI_ITD_NBUFFERS 7
 typedef struct {
 	volatile ehci_link_t		itd_next;
 	volatile ehci_isoc_trans_t	itd_ctl[EHCI_ITD_NUFRAMES];
-#define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf)
+#define EHCI_ITD_STATUS_MASK	__BITS(31,28)
-#define EHCI_ITD_SET_STATUS(x) (((x) & 0xf) << 28)
+#define EHCI_ITD_GET_STATUS(x)	__SHIFTOUT((x), EHCI_ITD_STATUS_MASK)
-#define EHCI_ITD_ACTIVE		0x80000000
+#define EHCI_ITD_SET_STATUS(x)	__SHIFTIN((x), EHCI_ITD_STATUS_MASK)
-#define EHCI_ITD_BUF_ERR	0x40000000
+#define EHCI_ITD_ACTIVE		__BIT(31)
-#define EHCI_ITD_BABBLE		0x20000000
+#define EHCI_ITD_BUF_ERR	__BIT(30)
-#define EHCI_ITD_ERROR		0x10000000
+#define EHCI_ITD_BABBLE		__BIT(29)
-#define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xfff)
+#define EHCI_ITD_ERROR		__BIT(28)
-#define EHCI_ITD_SET_LEN(x) (((x) & 0xfff) << 16)
+#define EHCI_ITD_LEN_MASK	__BITS(27,16)
-#define EHCI_ITD_IOC		0x8000
+#define EHCI_ITD_GET_LEN(x)	__SHIFTOUT((x), EHCI_ITD_LEN_MASK)
-#define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 1)
+#define EHCI_ITD_SET_LEN(x)	__SHIFTIN((x), EHCI_ITD_LEN_MASK)
-#define EHCI_ITD_SET_IOC(x) (((x) << 15) & EHCI_ITD_IOC)
+#define EHCI_ITD_IOC		__BIT(15)
-#define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7)
+#define EHCI_ITD_GET_IOC(x)	__SHIFTOUT((x), EHCI_ITD_IOC)
-#define EHCI_ITD_SET_PG(x) (((x) & 0x7) << 12)
+#define EHCI_ITD_SET_IOC(x)	__SHIFTIN((x), EHCI_ITD_IOC)
-#define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xfff)
+#define EHCI_ITD_PG_MASK	__BITS(14,12)
-#define EHCI_ITD_SET_OFFS(x) (((x) & 0xfff) << 0)
+#define EHCI_ITD_GET_PG(x)	__SHIFTOUT((x), EHCI_ITD_PG_MASK)
 #define EHCI_ITD_SET_PG(x)	__SHIFTIN((x), EHCI_ITD_PG_MASK)
 #define EHCI_ITD_OFFSET_MASK	__BITS(11,0)
 #define EHCI_ITD_GET_OFFS(x)	__SHIFTOUT((x), EHCI_ITD_OFFSET_MASK)
 #define EHCI_ITD_SET_OFFS(x)	__SHIFTIN((x), EHCI_ITD_OFFSET_MASK)
 	volatile ehci_isoc_bufr_ptr_t	itd_bufr[EHCI_ITD_NBUFFERS];
-#define EHCI_ITD_GET_BPTR(x) ((x) & 0xfffff000)
+#define EHCI_ITD_BPTR_MASK	__BITS(31,12)
-#define EHCI_ITD_SET_BPTR(x) ((x) & 0xfffff000)
+#define EHCI_ITD_GET_BPTR(x)	__SHIFTOUT((x), EHCI_ITD_BPTR_MASK)
-#define EHCI_ITD_GET_EP(x) (((x) >> 8) & 0xf)
+#define EHCI_ITD_SET_BPTR(x)	__SHIFTIN((x), EHCI_ITD_BPTR_MASK)
-#define EHCI_ITD_SET_EP(x) (((x) & 0xf) << 8)
+#define EHCI_ITD_EP_MASK	__BITS(11,8)
-#define EHCI_ITD_GET_DADDR(x) ((x) & 0x7f)
+#define EHCI_ITD_GET_EP(x)	__SHIFTOUT((x), EHCI_ITD_EP_MASK)
-#define EHCI_ITD_SET_DADDR(x) ((x) & 0x7f)
+#define EHCI_ITD_SET_EP(x)	__SHIFTIN((x), EHCI_ITD_EP_MASK)
-#define EHCI_ITD_GET_DIR(x) (((x) >> 11) & 1)
+#define EHCI_ITD_DADDR_MASK	__BITS(6,0)
-#define EHCI_ITD_SET_DIR(x) (((x) & 1) << 11)
+#define EHCI_ITD_GET_DADDR(x)	__SHIFTOUT((x), EHCI_ITD_DADDR_MASK)
-#define EHCI_ITD_GET_MAXPKT(x) ((x) & 0x7ff)
+#define EHCI_ITD_SET_DADDR(x)	__SHIFTIN((x), EHCI_ITD_DADDR_MASK)
-#define EHCI_ITD_SET_MAXPKT(x) ((x) & 0x7ff)
+#define EHCI_ITD_DIR_MASK	__BIT(11)
-#define EHCI_ITD_GET_MULTI(x) ((x) & 0x3)
+#define EHCI_ITD_GET_DIR(x)	__SHIFTOUT((x), EHCI_ITD_DIR_MASK)
-#define EHCI_ITD_SET_MULTI(x) ((x) & 0x3)
+#define EHCI_ITD_SET_DIR(x)	__SHIFTIN((x), EHCI_ITD_DIR_MASK)
 #define EHCI_ITD_MAXPKT_MASK	__BITS(10,0)
 #define EHCI_ITD_GET_MAXPKT(x)	__SHIFTOUT((x), EHCI_ITD_MAXPKT_MASK)
 #define EHCI_ITD_SET_MAXPKT(x)	__SHIFTIN((x), EHCI_ITD_MAXPKT_MASK)
 #define EHCI_ITD_MULTI_MASK	__BITS(1,0)
 #define EHCI_ITD_GET_MULTI(x)	__SHIFTOUT((x), EHCI_ITD_MULTI_MASK)
 #define EHCI_ITD_SET_MULTI(x)	__SHIFTIN((x), EHCI_ITD_MULTI_MASK)
 	volatile ehci_isoc_bufr_ptr_t	itd_bufr_hi[EHCI_ITD_NBUFFERS];
 } ehci_itd_t;
 #define EHCI_ITD_ALIGN 32
 /* Split Transaction Isochronous Transfer Descriptor */
 typedef struct {
 	volatile ehci_link_t	sitd_next;
 	volatile uint32_t	sitd_endp;
-#define EHCI_SITD_SET_DIR(x)	(((x) & 0x01) << 31)
+#define EHCI_SITD_DIR_MASK	__BIT(31)
-#define EHCI_SITD_SET_PORT(x)	(((x) & 0x7f) << 24)
+#define EHCI_SITD_PORT_MASK	__BITS(30,24)
-#define EHCI_SITD_SET_HUBA(x)	(((x) & 0x7f) << 16)
+#define EHCI_SITD_HUBA_MASK	__BITS(22,16)
-#define EHCI_SITD_SET_ENDPT(x)	(((x) & 0x0f) << 8)
+#define EHCI_SITD_ENDPT_MASK	__BITS(11,8)
-#define EHCI_SITD_SET_DADDR(x)	((x) & 0x7f)
+#define EHCI_SITD_DADDR_MASK	__BITS(6,0)
 #define EHCI_SITD_SET_DIR(x)	__SHIFTIN((x), EHCI_SITD_DIR_MASK)
 #define EHCI_SITD_SET_PORT(x)	__SHIFTIN((x), EHCI_SITD_PORT_MASK)
 #define EHCI_SITD_SET_HUBA(x)	__SHIFTIN((x), EHCI_SITD_HUBA_MASK)
 #define EHCI_SITD_SET_ENDPT(x)	__SHIFTIN((x), EHCI_SITD_ENDPT_MASK)
 #define EHCI_SITD_SET_DADDR(x)	__SHIFTIN((x), EHCI_SITD_DADDR_MASK)
 	volatile uint32_t	sitd_sched;
-#define EHCI_SITD_SET_SMASK(x)	((x) & 0xff)
+#define EHCI_SITD_SMASK_MASK	__BITS(7,0)
-#define EHCI_SITD_SET_CMASK(x)	(((x) & 0xff) << 8)
+#define EHCI_SITD_CMASK_MASK	__BITS(15,8)
 #define EHCI_SITD_SET_SMASK(x)	__SHIFTIN((x), EHCI_SITD_SMASK_MASK)
 #define EHCI_SITD_SET_CMASK(x)	__SHIFTIN((x), EHCI_SITD_CMASK_MASK)
 	volatile uint32_t	sitd_trans;
-#define EHCI_SITD_IOC		0x80000000
+#define EHCI_SITD_IOC		__BIT(31)
-#define EHCI_SITD_P		0x40000000
+#define EHCI_SITD_P		__BIT(30)
-#define EHCI_SITD_GET_LEN(x)	(((x) & 0x03ff0000) >> 16)
+#define EHCI_SITD_LENGTH_MASK	__BITS(25,16)
-#define EHCI_SITD_SET_LEN(x)	(((x) & 0x3ff) << 16)
+#define EHCI_SITD_GET_LEN(x)	__SHIFTOUT((x), EHCI_SITD_LENGTH_MASK)
 #define EHCI_SITD_SET_LEN(x)	__SHIFTIN((x), EHCI_SITD_LENGTH_MASK)
 #define EHCI_SITD_ACTIVE	0x00000080
 #define EHCI_SITD_ERR		0x00000040
 #define EHCI_SITD_BUFERR	0x00000020
 #define EHCI_SITD_BABBLE	0x00000010
 #define EHCI_SITD_XACTERR	0x00000008
 #define EHCI_SITD_MISS		0x00000004
 #define EHCI_SITD_SPLITXSTATE	0x00000002
 	volatile uint32_t	sitd_buffer[2];
 #define EHCI_SITD_SET_BPTR(x)	((x) & 0xfffff000)
 #define EHCI_SITD_SET_OFFS(x)	((x) & 0xfff)
 	volatile uint32_t	sitd_back;
 } ehci_sitd_t;
 #define EHCI_SITD_ALIGN 32
 /* Queue Element Transfer Descriptor */
 #define EHCI_QTD_NBUFFERS	5
 #define EHCI_QTD_MAXTRANSFER	(EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE)
 typedef struct {
 	volatile ehci_link_t	qtd_next;
 	volatile ehci_link_t	qtd_altnext;
 	volatile uint32_t	qtd_status;
-#define EHCI_QTD_GET_STATUS(x)	(((x) >>  0) & 0xff)
+#define EHCI_QTD_STATUS_MASK	__BITS(7,0)
-#define EHCI_QTD_SET_STATUS(x)	((x) <<  0)
+#define EHCI_QTD_GET_STATUS(x)	__SHIFTOUT((x), EHCI_QTD_STATUS_MASK)
 #define EHCI_QTD_SET_STATUS(x)	__SHIFTIN((x), EHCI_QTD_STATUS_MASK)
 #define  EHCI_QTD_ACTIVE	0x80
 #define  EHCI_QTD_HALTED	0x40
 #define  EHCI_QTD_BUFERR	0x20
 #define  EHCI_QTD_BABBLE	0x10
 #define  EHCI_QTD_XACTERR	0x08
 #define  EHCI_QTD_MISSEDMICRO	0x04
 #define  EHCI_QTD_SPLITXSTATE	0x02
 #define  EHCI_QTD_PINGSTATE	0x01
 #define  EHCI_QTD_STATERRS	0x3c
-#define EHCI_QTD_GET_PID(x)	(((x) >>  8) & 0x3)
+#define EHCI_QTD_PID_MASK	__BITS(9,8)
-#define EHCI_QTD_SET_PID(x)	((x) <<  8)
+#define EHCI_QTD_GET_PID(x)	__SHIFTOUT((x), EHCI_QTD_PID_MASK)
 #define EHCI_QTD_SET_PID(x)	__SHIFTIN((x), EHCI_QTD_PID_MASK)
 #define  EHCI_QTD_PID_OUT	0x0
 #define  EHCI_QTD_PID_IN	0x1
 #define  EHCI_QTD_PID_SETUP	0x2
-#define EHCI_QTD_GET_CERR(x)	(((x) >> 10) &  0x3)
+#define EHCI_QTD_CERR_MASK	__BITS(11,10)
-#define EHCI_QTD_SET_CERR(x)	((x) << 10)
+#define EHCI_QTD_GET_CERR(x)	__SHIFTOUT((x), EHCI_QTD_CERR_MASK)
-#define EHCI_QTD_GET_C_PAGE(x)	(((x) >> 12) &  0x7)
+#define EHCI_QTD_SET_CERR(x)	__SHIFTIN((x), EHCI_QTD_CERR_MASK)
-#define EHCI_QTD_SET_C_PAGE(x)	((x) << 12)
+#define EHCI_QTD_C_PAGE_MASK	__BITS(14,12)
-#define EHCI_QTD_GET_IOC(x)	(((x) >> 15) &  0x1)
+#define EHCI_QTD_GET_C_PAGE(x)	__SHIFTOUT((x), EHCI_QTD_C_PAGE_MASK)
-#define EHCI_QTD_IOC		0x00008000
+#define EHCI_QTD_SET_C_PAGE(x)	__SHIFTIN((x), EHCI_QTD_C_PAGE_MASK)
-#define EHCI_QTD_GET_BYTES(x)	(((x) >> 16) &  0x7fff)
+#define EHCI_QTD_IOC		__BIT(15)
-#define EHCI_QTD_SET_BYTES(x)	((x) << 16)
+#define EHCI_QTD_GET_IOC(x)	__SHIFTOUT((x), EHCI_QTD_IOC)
-#define EHCI_QTD_GET_TOGGLE(x)	(((x) >> 31) &  0x1)
+#define EHCI_QTD_BYTES_MASK	__BITS(30,16)
-#define	EHCI_QTD_SET_TOGGLE(x)	((x) << 31)
+#define EHCI_QTD_GET_BYTES(x)	__SHIFTOUT((x), EHCI_QTD_BYTES_MASK)
-#define EHCI_QTD_TOGGLE_MASK	0x80000000
+#define EHCI_QTD_SET_BYTES(x)	__SHIFTIN((x), EHCI_QTD_BYTES_MASK)
 #define EHCI_QTD_TOGGLE_MASK	__BIT(31)
 #define EHCI_QTD_GET_TOGGLE(x)	__SHIFTOUT((x), EHCI_QTD_TOGGLE_MASK)
 #define	EHCI_QTD_SET_TOGGLE(x)	__SHIFTIN((x), EHCI_QTD_TOGGLE_MASK)
 	volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
 	volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
 } ehci_qtd_t;
 #define EHCI_QTD_ALIGN 32
 /* Queue Head */
 typedef struct {
 	volatile ehci_link_t	qh_link;
 	volatile uint32_t	qh_endp;
-#define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f) /* endpoint addr */
+#define EHCI_QH_ADDR_MASK	__BITS(6,0)	/* endpoint addr */
-#define EHCI_QH_SET_ADDR(x)	(x)
+#define EHCI_QH_GET_ADDR(x)	__SHIFTOUT((x), EHCI_QH_ADDR_MASK)
-#define EHCI_QH_ADDRMASK	0x0000007f
+#define EHCI_QH_SET_ADDR(x)	__SHIFTIN((x), EHCI_QH_ADDR_MASK)
-#define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01) /* inactivate on next */
+#define EHCI_QH_INACT		__BIT(7)	/* inactivate on next */
-#define EHCI_QH_INACT		0x00000080
+#define EHCI_QH_GET_INACT(x)	__SHIFTOUT((x), EHCI_QH_INACT)
-#define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f) /* endpoint no */
+#define EHCI_QH_ENDPT_MASK	__BITS(11,8)	 /* endpoint no */
-#define EHCI_QH_SET_ENDPT(x)	((x) <<  8)
+#define EHCI_QH_GET_ENDPT(x)	__SHIFTOUT((x), EHCI_QH_ENDPT_MASK)
-#define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03) /* endpoint speed */
+#define EHCI_QH_SET_ENDPT(x)	__SHIFTIN((x), EHCI_QH_ENDPT_MASK)
-#define EHCI_QH_SET_EPS(x)	((x) << 12)
+#define EHCI_QH_EPS_MASK	__BITS(13,12)	/* endpoint speed */
 #define EHCI_QH_GET_EPS(x)	__SHIFTOUT((x), EHCI_QH_EPS_MASK)
 #define EHCI_QH_SET_EPS(x)	__SHIFTIN((x), EHCI_QH_EPS_MASK)
 #define  EHCI_QH_SPEED_FULL	0x0
 #define  EHCI_QH_SPEED_LOW	0x1
 #define  EHCI_QH_SPEED_HIGH	0x2
-#define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01) /* data toggle control */
+#define EHCI_QH_DTC		__BIT(14)	 /* data toggle control */
-#define EHCI_QH_DTC		0x00004000
+#define EHCI_QH_GET_DTC(x)	__SHIFTOUT((x), EHCI_QH_DTC)
-#define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01) /* head of reclamation */
+#define EHCI_QH_HRECL		__BIT(15)	/* head of reclamation */
-#define EHCI_QH_HRECL		0x00008000
+#define EHCI_QH_GET_HRECL(x)	__SHIFTOUT((x), EHCI_QH_HRECL)
-#define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff) /* max packet len */
+#define EHCI_QH_MPL_MASK	__BITS(26,16)	/* max packet len */
-#define EHCI_QH_SET_MPL(x)	((x) << 16)
+#define EHCI_QH_GET_MPL(x)	__SHIFTOUT((x), EHCI_QH_MPL_MASK)
-#define EHCI_QH_MPLMASK		0x07ff0000
+#define EHCI_QH_SET_MPL(x)	__SHIFTIN((x), EHCI_QH_MPL_MASK)
-#define EHCI_QH_GET_CTL(x)	(((x) >> 27) & 0x01) /* control endpoint */
+#define EHCI_QH_CTL		__BIT(27)	/* control endpoint */
-#define EHCI_QH_CTL		0x08000000
+#define EHCI_QH_GET_CTL(x)	__SHIFTOUT((x), EHCI_QH_CTL)
-#define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f) /* NAK reload */
+#define EHCI_QH_NRL_MASK	__BITS(31,28)	/* NAK reload */
-#define EHCI_QH_SET_NRL(x)	((x) << 28)
+#define EHCI_QH_GET_NRL(x)	__SHIFTOUT((x), EHCI_QH_NRL_MASK)
 #define EHCI_QH_SET_NRL(x)	__SHIFTIN((x), EHCI_QH_NRL_MASK)
 	volatile uint32_t	qh_endphub;
-#define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff) /* intr sched mask */
+#define EHCI_QH_SMASK_MASK	__BITS(7,0)	 /* intr sched mask */
-#define EHCI_QH_SET_SMASK(x)	((x) <<  0)
+#define EHCI_QH_GET_SMASK(x)	__SHIFTOUT((x), EHCI_QH_SMASK_MASK)
-#define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff) /* split completion mask */
+#define EHCI_QH_SET_SMASK(x)	__SHIFTIN((x), EHCI_QH_SMASK_MASK)
-#define EHCI_QH_SET_CMASK(x)	((x) <<  8)
+#define EHCI_QH_CMASK_MASK	__BITS(15,8)	 /* split completion mask */
-#define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f) /* hub address */
+#define EHCI_QH_GET_CMASK(x)	__SHIFTOUT((x), EHCI_QH_CMASK_MASK)
-#define EHCI_QH_SET_HUBA(x)	((x) << 16)
+#define EHCI_QH_SET_CMASK(x)	__SHIFTIN((x), EHCI_QH_CMASK_MASK)
-#define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f) /* hub port */
+#define EHCI_QH_HUBA_MASK	__BITS(22,16)	/* hub address */
-#define EHCI_QH_SET_PORT(x)	((x) << 23)
+#define EHCI_QH_GET_HUBA(x)	__SHIFTOUT((x), EHCI_QH_HUBA_MASK)
-#define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03) /* pipe multiplier */
+#define EHCI_QH_SET_HUBA(x)	__SHIFTIN((x), EHCI_QH_HUBA_MASK)
-#define EHCI_QH_SET_MULT(x)	((x) << 30)
+#define EHCI_QH_PORT_MASK	__BITS(29,23)	 /* hub port */
 #define EHCI_QH_GET_PORT(x)	__SHIFTOUT((x), EHCI_QH_PORT_MASK)
 #define EHCI_QH_SET_PORT(x)	__SHIFTIN((x), EHCI_QH_PORT_MASK)
 #define EHCI_QH_MULTI_MASK	__BITS(31,30)	/* pipe multiplier */
 #define EHCI_QH_GET_MULT(x)	__SHIFTOUT((x), EHCI_QH_MULTI_MASK)
 #define EHCI_QH_SET_MULT(x)	__SHIFTIN((x), EHCI_QH_MULTI_MASK)
 	volatile ehci_link_t	qh_curqtd;
 	ehci_qtd_t		qh_qtd;
 } ehci_qh_t;
 #define EHCI_QH_ALIGN 32
 /* Periodic Frame Span Traversal Node */
 typedef struct {
 	volatile ehci_link_t	fstn_link;
 	volatile ehci_link_t	fstn_back;
 } ehci_fstn_t;
 #define EHCI_FSTN_ALIGN 32
 /* Debug Port */
 #define PCI_CAP_DEBUGPORT_OFFSET __BITS(28,16)
 #define PCI_CAP_DEBUGPORT_BAR	__BITS(31,29)
 /* Debug Port Registers, offset into DEBUGPORT_BAR at DEBUGPORT_OFFSET */
 #define EHCI_DEBUG_SC		0x00
 /* Status/Control Register */
 #define  EHCI_DSC_DATA_LENGTH	__BITS(3,0)
 #define  EHCI_DSC_WRITE		__BIT(4)
 #define  EHCI_DSC_GO		__BIT(5)
 #define  EHCI_DSC_ERROR		__BIT(6)
 #define  EHCI_DSC_EXCEPTION	__BITS(9,7)
 #define   EHCI_DSC_EXCEPTION_NONE	0
 #define   EHCI_DSC_EXCEPTION_XACT	1
 #define   EHCI_DSC_EXCEPTION_HW		2
 #define  EHCI_DSC_IN_USE	__BIT(10)
 #define  EHCI_DSC_DONE		__BIT(16)
 #define  EHCI_DSC_ENABLED	__BIT(28)
 #define  EHCI_DSC_OWNER		__BIT(30)
 #define EHCI_DEBUG_UPR		0x04
 /* USB PIDs Register */
 #define  EHCI_DPR_TOKEN		__BITS(7,0)
 #define  EHCI_DPR_SEND		__BITS(15,8)
 #define  EHCI_DPR_RECEIVED	__BITS(23,16)
 /* Data Registers */
 #define EHCI_DEBUG_DATA0123	0x08
 #define EHCI_DEBUG_DATA4567	0x0c
 #define EHCI_DEBUG_DAR		0x10
 /* Device Address Register */
 #define  EHCI_DAR_ENDPOINT	__BITS(3,0)
 #define  EHCI_DAR_ADDRESS	__BITS(14,8)
 #endif /* _DEV_PCI_EHCIREG_H_ */