Tue Mar 3 21:53:12 2015 UTC ()
in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)


(jmcneill)
diff -r1.13 -r1.14 src/sys/arch/arm/cortex/gic.c
cvs diff -r1.13 -r1.14 src/sys/arch/arm/cortex/gic.c (expand / switch to unified diff)

--- src/sys/arch/arm/cortex/gic.c 2015/03/02 11:37:25 1.13
+++ src/sys/arch/arm/cortex/gic.c 2015/03/03 21:53:12 1.14
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: gic.c,v 1.13 2015/03/02 11:37:25 jmcneill Exp $ */ 1/* $NetBSD: gic.c,v 1.14 2015/03/03 21:53:12 jmcneill Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -24,27 +24,27 @@ @@ -24,27 +24,27 @@
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#include "opt_ddb.h" 31#include "opt_ddb.h"
32#include "opt_multiprocessor.h" 32#include "opt_multiprocessor.h"
33 33
34#define _INTR_PRIVATE 34#define _INTR_PRIVATE
35 35
36#include <sys/cdefs.h> 36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.13 2015/03/02 11:37:25 jmcneill Exp $"); 37__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.14 2015/03/03 21:53:12 jmcneill Exp $");
38 38
39#include <sys/param.h> 39#include <sys/param.h>
40#include <sys/bus.h> 40#include <sys/bus.h>
41#include <sys/device.h> 41#include <sys/device.h>
42#include <sys/evcnt.h> 42#include <sys/evcnt.h>
43#include <sys/intr.h> 43#include <sys/intr.h>
44#include <sys/cpu.h> 44#include <sys/cpu.h>
45#include <sys/proc.h> 45#include <sys/proc.h>
46 46
47#include <arm/armreg.h> 47#include <arm/armreg.h>
48#include <arm/cpufunc.h> 48#include <arm/cpufunc.h>
49#include <arm/atomic.h> 49#include <arm/atomic.h>
50 50
@@ -361,27 +361,27 @@ armgic_establish_irq(struct pic_softc *p @@ -361,27 +361,27 @@ armgic_establish_irq(struct pic_softc *p
361 gicd_write(sc, targets_reg, targets); 361 gicd_write(sc, targets_reg, targets);
362 362
363 /*  363 /*
364 * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL 364 * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL
365 */ 365 */
366 uint32_t new_cfg = cfg; 366 uint32_t new_cfg = cfg;
367 uint32_t old_cfg = (cfg >> twopair_shift) & 3; 367 uint32_t old_cfg = (cfg >> twopair_shift) & 3;
368 if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { 368 if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) {
369 new_cfg &= ~(3 << twopair_shift); 369 new_cfg &= ~(3 << twopair_shift);
370 } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { 370 } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) {
371 new_cfg |= 2 << twopair_shift; 371 new_cfg |= 2 << twopair_shift;
372 } 372 }
373 if (new_cfg != cfg) { 373 if (new_cfg != cfg) {
374 gicd_write(sc, cfg_reg, cfg); 374 gicd_write(sc, cfg_reg, new_cfg);
375#if 0 375#if 0
376 printf("%s: irq %u: cfg changed from %#x to %#x\n", 376 printf("%s: irq %u: cfg changed from %#x to %#x\n",
377 pic->pic_name, is->is_irq, cfg, new_cfg); 377 pic->pic_name, is->is_irq, cfg, new_cfg);
378#endif 378#endif
379 } 379 }
380#ifdef MULTIPROCESSOR 380#ifdef MULTIPROCESSOR
381 } else { 381 } else {
382 /* 382 /*
383 * All group 0 interrupts are per processor and MPSAFE by 383 * All group 0 interrupts are per processor and MPSAFE by
384 * default. 384 * default.
385 */ 385 */
386 is->is_mpsafe = true; 386 is->is_mpsafe = true;
387#endif 387#endif