Thu Mar 5 21:13:48 2015 UTC ()

Write the loops the same way, leaving i containing the number of tries
left. Also break early in the hot case.


(christos)

diff -r1.12 -r1.13 src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c

--- src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_i2c.c 2015/03/02 23:05:03	1.12
+++ src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_i2c.c 2015/03/05 21:13:48	1.13

 @@ -277,46 +277,49 @@ gmbus_wait_hw_status(struct drm_i915_pri
 #else
 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
 		gmbus4_irq_en = 0;
 #endif
 	/* Important: The hw handles only the first bit, so set only one! Since
 	 * we also need to check for NAKs besides the hw ready/idle signal, we
 	 * need to wake up periodically and check that ourselves. */
 	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 #ifdef __NetBSD__
 	if (cold) {
 		i = 50;
-		while (gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset),
+		do {
-		    !ISSET(gmbus2, (GMBUS_SATOER | gmbus2_status))) {
+			gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
-			if (i-- == 0)
+			if (ISSET(gmbus2, (GMBUS_SATOER | gmbus2_status)))
 				break;
 			DELAY(1000);
 		} while (i-- > 0);
 	} else {
-		for (i = 0; i < mstohz(50); i++) {
+		i = mstohz(50);
 		do {
 			int ret;
 			spin_lock(&dev_priv->gmbus_wait_lock);
 			DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
 			    &dev_priv->gmbus_wait_queue,
 			    &dev_priv->gmbus_wait_lock,
 ,
 			    (gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset),
 				ISSET(gmbus2,
 				    (GMBUS_SATOER | gmbus2_status))));
 			spin_unlock(&dev_priv->gmbus_wait_lock);
 			if (ret)
 				break;
 		} while (i-- > 0);
+	}
 #else
 	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 				TASK_UNINTERRUPTIBLE);
 		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
 		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 			break;
 		schedule_timeout(1);
+	}
 	finish_wait(&dev_priv->gmbus_wait_queue, &wait);