 @@ -1,14 +1,14 @@
-/*	$NetBSD: tifb.c,v 1.4 2015/04/11 13:44:14 bouyer Exp $	*/
+/*	$NetBSD: tifb.c,v 1.5 2015/04/12 20:00:42 bouyer Exp $	*/
 /*
  * Copyright (c) 2010 Michael Lorenz
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -47,37 +47,38 @@
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * A framebuffer driver for TI 35xx built-in video controller
  * tested on beaglebone
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tifb.c,v 1.4 2015/04/11 13:44:14 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tifb.c,v 1.5 2015/04/12 20:00:42 bouyer Exp $");
 #include "opt_omap.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/lwp.h>
 #include <sys/kauth.h>
 #include <sys/kmem.h>
 #include <uvm/uvm_extern.h>
 #include <dev/videomode/videomode.h>
 #include <sys/bus.h>
 #include <arm/omap/tifbreg.h>
 #include <arm/omap/omap_var.h>
 #include <arm/omap/omap2_obiovar.h>
 #include <arm/omap/omap2_obioreg.h>
 #ifdef TI_AM335X
 #  include <arm/omap/am335x_prcm.h>
 #  include <arm/omap/omap2_prcm.h>
 @@ -145,26 +146,27 @@ struct tifb_softc {
 	void *sc_ih;
 	bus_space_tag_t sc_iot;
 	bus_dma_tag_t sc_dmat;
 	bus_space_handle_t sc_regh;
 	bus_dmamap_t sc_dmamap;
 	bus_dma_segment_t sc_dmamem[1];
 	size_t sc_vramsize;
 	size_t sc_palettesize;
 	int sc_stride;
 	int sc_locked;
 	void *sc_fbaddr, *sc_vramaddr;
 	void *sc_shadowfb;
 	bus_addr_t sc_fbhwaddr;
 	uint16_t *sc_palette;
 	uint32_t sc_dispc_config;
 	struct vcons_screen sc_console_screen;
 	struct wsscreen_descr sc_defaultscreen_descr;
 	const struct wsscreen_descr *sc_screens[1];
 	struct wsscreen_list sc_screenlist;
 	struct vcons_data vd;
 	int sc_mode;
 	uint8_t sc_cmap_red[256], sc_cmap_green[256], sc_cmap_blue[256];
 	void (*sc_putchar)(void *, int, int, u_int, long);
 @@ -385,35 +387,41 @@ tifb_attach(device_t parent, device_t se
 	/* setup video DMA */
 	switch(sc->sc_panel->bpp) {
 	case 8:
 		sc->sc_palettesize = 512;
 		break;
 	default:
 		sc->sc_palettesize = 32;
 		break;
+	}
 	sc->sc_vramsize = sc->sc_palettesize +
 	    sc->sc_stride * sc->sc_panel->panel_height;
 	sc->sc_shadowfb = kmem_alloc(sc->sc_vramsize - sc->sc_palettesize,
 	    KM_NOSLEEP);
 	if (sc->sc_shadowfb == NULL) {
 		aprint_error_dev(sc->sc_dev,
 		    "warning: failed to allocate shadow framebuffer\n");
+	}
 	if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_vramsize, 0, 0,
 	    sc->sc_dmamem, 1, &segs, BUS_DMA_NOWAIT) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "failed to allocate video memory\n");
 		return;
+	}
 	if (bus_dmamem_map(sc->sc_dmat, sc->sc_dmamem, 1, sc->sc_vramsize,
-	    &sc->sc_vramaddr, BUS_DMA_NOWAIT) != 0) {
+	    &sc->sc_vramaddr, BUS_DMA_NOWAIT | BUS_DMA_PREFETCHABLE) != 0) {
 		aprint_error_dev(sc->sc_dev, "failed to map video RAM\n");
 		return;
+	}
 	sc->sc_fbaddr = (uint8_t *)sc->sc_vramaddr + sc->sc_palettesize;
 	sc->sc_palette = sc->sc_vramaddr;
 	if (bus_dmamap_create(sc->sc_dmat, sc->sc_vramsize, 1, sc->sc_vramsize,
 , BUS_DMA_NOWAIT, &sc->sc_dmamap) != 0) {
 		aprint_error_dev(sc->sc_dev, "failed to create DMA map\n");
 		return;
+	}
 	if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_vramaddr,
 @@ -533,27 +541,27 @@ tifb_attach(device_t parent, device_t se
 		timing2 |= RASTER_TIMING_2_IPC;
 	/* AC bias */
 	timing2 |= (sc->sc_panel->ac_bias << RASTER_TIMING_2_ACB_SHIFT);
 	timing2 |= (sc->sc_panel->ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT);
 	TIFB_WRITE(sc, LCD_RASTER_TIMING_0, timing0);
 	TIFB_WRITE(sc, LCD_RASTER_TIMING_1, timing1);
 	TIFB_WRITE(sc, LCD_RASTER_TIMING_2, timing2);
 	aprint_debug_dev(self, ": timings 0x%x 0x%x 0x%x\n",
 	    timing0, timing1, timing2);
 	/* DMA settings */
-	reg = LCDDMA_CTRL_FB0_FB1;
+	reg = 0;
 	/* Find power of 2 for current burst size */
 	switch (sc->sc_panel->dma_burst_sz) {
 	case 1:
 		burst_log = 0;
 		break;
 	case 2:
 		burst_log = 1;
 		break;
 	case 4:
 		burst_log = 2;
 		break;
 	case 8:
 		burst_log = 3;
 @@ -587,29 +595,27 @@ tifb_attach(device_t parent, device_t se
 	if (sc->sc_panel->bpp == 32)
 		reg |= RASTER_CTRL_TFT24_UNPACKED;
 	TIFB_WRITE(sc, LCD_RASTER_CTRL, reg);
 	aprint_debug_dev(self, ": LCD_RASTER_CTRL 0x%x\n", reg);
 	TIFB_WRITE(sc, LCD_CLKC_ENABLE,
 	    CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE);
 	TIFB_WRITE(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN);
 	DELAY(100);
 	TIFB_WRITE(sc, LCD_CLKC_RESET, 0);
 	aprint_debug_dev(self, ": LCD_CLKC_ENABLE 0x%x\n", TIFB_READ(sc, LCD_CLKC_ENABLE));
-	reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL |
+	reg = IRQ_FUF | IRQ_PL | IRQ_ACB | IRQ_SYNC_LOST;
 	    IRQ_ACB | IRQ_SYNC_LOST |  IRQ_RASTER_DONE |
 	    IRQ_FRAME_DONE;
 	TIFB_WRITE(sc, LCD_IRQENABLE_SET, reg);
 	reg = TIFB_READ(sc, LCD_RASTER_CTRL);
 	reg |= RASTER_CTRL_LCDEN;
 	TIFB_WRITE(sc, LCD_RASTER_CTRL, reg);
 	aprint_debug_dev(self, ": LCD_RASTER_CTRL 0x%x\n", TIFB_READ(sc, LCD_RASTER_CTRL));
 	TIFB_WRITE(sc, LCD_SYSCONFIG,
 	    SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART);
 	aprint_debug_dev(self, ": LCD_SYSCONFIG 0x%x\n", TIFB_READ(sc, LCD_SYSCONFIG));
 	/* attach wscons */
 	sc->sc_defaultscreen_descr = (struct wsscreen_descr){
 @@ -643,26 +649,28 @@ tifb_attach(device_t parent, device_t se
 		wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0,
 		    defattr);
 		vcons_replay_msgbuf(&sc->sc_console_screen);
+	}
 	aa.console = is_console;
 	aa.scrdata = &sc->sc_screenlist;
 	aa.accessops = &tifb_accessops;
 	aa.accesscookie = &sc->vd;
 	config_found(sc->sc_dev, &aa, wsemuldisplaydevprint);
+}
 uint32_t tifb_intr_unh = 0;
 static int
 tifb_intr(void *v)
+{
 	struct tifb_softc *sc = v;
 	uint32_t reg;
 	reg = TIFB_READ(sc, LCD_IRQSTATUS);
 	TIFB_WRITE(sc, LCD_IRQSTATUS, reg);
 	if (reg & IRQ_SYNC_LOST) {
 		ev_sync_lost.ev_count ++;
 		reg = TIFB_READ(sc, LCD_RASTER_CTRL);
 		reg &= ~RASTER_CTRL_LCDEN;
 @@ -676,32 +684,26 @@ tifb_intr(void *v)
 	if (reg & IRQ_PL) {
 		ev_palette.ev_count ++;
 		reg = TIFB_READ(sc, LCD_RASTER_CTRL);
 		reg &= ~RASTER_CTRL_LCDEN;
 		TIFB_WRITE(sc, LCD_RASTER_CTRL, reg);
 		reg = TIFB_READ(sc, LCD_RASTER_CTRL);
 		reg |= RASTER_CTRL_LCDEN;
 		TIFB_WRITE(sc, LCD_RASTER_CTRL, reg);
 		return 0;
+	}
 	if (reg & (IRQ_FRAME_DONE|IRQ_EOF0|IRQ_EOF1)) {
 		/* flush the write-back cache */
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 , sc->sc_vramsize, BUS_DMASYNC_PREWRITE);
 	if (reg & IRQ_FRAME_DONE) {
 		ev_frame_done.ev_count ++;
 		reg &= ~IRQ_FRAME_DONE;
+	}
 	if (reg & IRQ_EOF0) {
 		ev_eof0.ev_count ++;
 		TIFB_WRITE(sc, LCD_LCDDMA_FB0_BASE, sc->sc_dmamem->ds_addr);
 		TIFB_WRITE(sc, LCD_LCDDMA_FB0_CEILING,
 		    sc->sc_dmamem->ds_addr + sc->sc_vramsize - 1);
 		reg &= ~IRQ_EOF0;
+	}
 @@ -714,28 +716,30 @@ tifb_intr(void *v)
+	}
 	if (reg & IRQ_FUF) {
 		ev_fifo_underflow.ev_count ++;
 		/* TODO: Handle FUF */
 		reg =~ IRQ_FUF;
+	}
 	if (reg & IRQ_ACB) {
 		ev_ac_bias.ev_count ++;
 		/* TODO: Handle ACB */
 		reg =~ IRQ_ACB;
+	}
-	if (reg)
+	if (reg) {
 		ev_others.ev_count ++;
 		tifb_intr_unh = reg;
+	}
 	return 0;
+}
 static int
 tifb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
 	struct lwp *l)
+{
 	struct vcons_data *vd = v;
 	struct tifb_softc *sc = vd->cookie;
 	struct wsdisplay_fbinfo *wdf;
 	struct vcons_screen *ms = vd->active;
 	switch (cmd) {
 @@ -840,28 +844,34 @@ tifb_mmap(void *v, void *vs, off_t offse
 static void
 tifb_init_screen(void *cookie, struct vcons_screen *scr,
     int existing, long *defattr)
+{
 	struct tifb_softc *sc = cookie;
 	struct rasops_info *ri = &scr->scr_ri;
 	ri->ri_depth = sc->sc_panel->bpp;
 	ri->ri_width = sc->sc_panel->panel_width;
 	ri->ri_height = sc->sc_panel->panel_height;
 	ri->ri_stride = sc->sc_stride;
 	ri->ri_flg = RI_CENTER | RI_FULLCLEAR;
-	ri->ri_bits = (char *)sc->sc_fbaddr;
+	if (sc->sc_shadowfb != NULL) {
 		ri->ri_bits = (char *)sc->sc_shadowfb;
 		ri->ri_hwbits = (char *)sc->sc_fbaddr;
 	} else {
 		ri->ri_bits = (char *)sc->sc_fbaddr;
 		ri->ri_hwbits = NULL;
+	}
 	if (existing) {
 		ri->ri_flg |= RI_CLEAR;
+	}
 	rasops_init(ri, sc->sc_panel->panel_height / 8, sc->sc_panel->panel_width / 8);
 	ri->ri_caps = WSSCREEN_WSCOLORS;
 	rasops_reconfig(ri, sc->sc_panel->panel_height / ri->ri_font->fontheight,
 		    sc->sc_panel->panel_width / ri->ri_font->fontwidth);
 	ri->ri_hw = scr;
+}