Tue Apr 14 18:34:29 2015 UTC ()
Add a new SDHC_FLAG, SDHC_FLAG_EXTDMA_DMAEN, which request that the
SDHC_DMA_ENABLE bit be set in the command, even if we're using an
external DMA engine. Needed by the upcoming DMA support for AM335x
(beaglebone).


(bouyer)
diff -r1.54 -r1.55 src/sys/dev/sdmmc/sdhc.c
diff -r1.15 -r1.16 src/sys/dev/sdmmc/sdhcvar.h
cvs diff -r1.54 -r1.55 src/sys/dev/sdmmc/sdhc.c (switch to unified diff)

--- src/sys/dev/sdmmc/sdhc.c 2015/02/27 15:53:09 1.54
+++ src/sys/dev/sdmmc/sdhc.c 2015/04/14 18:34:29 1.55
@@ -1,1810 +1,1820 @@ @@ -1,1810 +1,1820 @@
1/* $NetBSD: sdhc.c,v 1.54 2015/02/27 15:53:09 nonaka Exp $ */ 1/* $NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $ */
2/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 2/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
3 3
4/* 4/*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 * 6 *
7 * Permission to use, copy, modify, and distribute this software for any 7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above 8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies. 9 * copyright notice and this permission notice appear in all copies.
10 * 10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */ 18 */
19 19
20/* 20/*
21 * SD Host Controller driver based on the SD Host Controller Standard 21 * SD Host Controller driver based on the SD Host Controller Standard
22 * Simplified Specification Version 1.00 (www.sdcard.com). 22 * Simplified Specification Version 1.00 (www.sdcard.com).
23 */ 23 */
24 24
25#include <sys/cdefs.h> 25#include <sys/cdefs.h>
26__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.54 2015/02/27 15:53:09 nonaka Exp $"); 26__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $");
27 27
28#ifdef _KERNEL_OPT 28#ifdef _KERNEL_OPT
29#include "opt_sdmmc.h" 29#include "opt_sdmmc.h"
30#endif 30#endif
31 31
32#include <sys/param.h> 32#include <sys/param.h>
33#include <sys/device.h> 33#include <sys/device.h>
34#include <sys/kernel.h> 34#include <sys/kernel.h>
35#include <sys/kthread.h> 35#include <sys/kthread.h>
36#include <sys/malloc.h> 36#include <sys/malloc.h>
37#include <sys/systm.h> 37#include <sys/systm.h>
38#include <sys/mutex.h> 38#include <sys/mutex.h>
39#include <sys/condvar.h> 39#include <sys/condvar.h>
40 40
41#include <dev/sdmmc/sdhcreg.h> 41#include <dev/sdmmc/sdhcreg.h>
42#include <dev/sdmmc/sdhcvar.h> 42#include <dev/sdmmc/sdhcvar.h>
43#include <dev/sdmmc/sdmmcchip.h> 43#include <dev/sdmmc/sdmmcchip.h>
44#include <dev/sdmmc/sdmmcreg.h> 44#include <dev/sdmmc/sdmmcreg.h>
45#include <dev/sdmmc/sdmmcvar.h> 45#include <dev/sdmmc/sdmmcvar.h>
46 46
47#ifdef SDHC_DEBUG 47#ifdef SDHC_DEBUG
48int sdhcdebug = 1; 48int sdhcdebug = 1;
49#define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49#define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0)
50void sdhc_dump_regs(struct sdhc_host *); 50void sdhc_dump_regs(struct sdhc_host *);
51#else 51#else
52#define DPRINTF(n,s) do {} while (0) 52#define DPRINTF(n,s) do {} while (0)
53#endif 53#endif
54 54
55#define SDHC_COMMAND_TIMEOUT hz 55#define SDHC_COMMAND_TIMEOUT hz
56#define SDHC_BUFFER_TIMEOUT hz 56#define SDHC_BUFFER_TIMEOUT hz
57#define SDHC_TRANSFER_TIMEOUT hz 57#define SDHC_TRANSFER_TIMEOUT hz
58#define SDHC_DMA_TIMEOUT hz 58#define SDHC_DMA_TIMEOUT hz
59 59
60struct sdhc_host { 60struct sdhc_host {
61 struct sdhc_softc *sc; /* host controller device */ 61 struct sdhc_softc *sc; /* host controller device */
62 62
63 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_tag_t iot; /* host register set tag */
64 bus_space_handle_t ioh; /* host register set handle */ 64 bus_space_handle_t ioh; /* host register set handle */
65 bus_size_t ios; /* host register space size */ 65 bus_size_t ios; /* host register space size */
66 bus_dma_tag_t dmat; /* host DMA tag */ 66 bus_dma_tag_t dmat; /* host DMA tag */
67 67
68 device_t sdmmc; /* generic SD/MMC device */ 68 device_t sdmmc; /* generic SD/MMC device */
69 69
70 struct kmutex host_mtx; 70 struct kmutex host_mtx;
71 71
72 u_int clkbase; /* base clock frequency in KHz */ 72 u_int clkbase; /* base clock frequency in KHz */
73 int maxblklen; /* maximum block length */ 73 int maxblklen; /* maximum block length */
74 uint32_t ocr; /* OCR value from capabilities */ 74 uint32_t ocr; /* OCR value from capabilities */
75 75
76 uint8_t regs[14]; /* host controller state */ 76 uint8_t regs[14]; /* host controller state */
77 77
78 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_status; /* soft interrupt status */
79 uint16_t intr_error_status; /* soft error status */ 79 uint16_t intr_error_status; /* soft error status */
80 struct kmutex intr_mtx; 80 struct kmutex intr_mtx;
81 struct kcondvar intr_cv; 81 struct kcondvar intr_cv;
82 82
83 int specver; /* spec. version */ 83 int specver; /* spec. version */
84 84
85 uint32_t flags; /* flags for this host */ 85 uint32_t flags; /* flags for this host */
86#define SHF_USE_DMA 0x0001 86#define SHF_USE_DMA 0x0001
87#define SHF_USE_4BIT_MODE 0x0002 87#define SHF_USE_4BIT_MODE 0x0002
88#define SHF_USE_8BIT_MODE 0x0004 88#define SHF_USE_8BIT_MODE 0x0004
 89#define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */
89}; 90};
90 91
91#define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 92#define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev))
92 93
93static uint8_t 94static uint8_t
94hread1(struct sdhc_host *hp, bus_size_t reg) 95hread1(struct sdhc_host *hp, bus_size_t reg)
95{ 96{
96 97
97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_1(hp->iot, hp->ioh, reg);
99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));
100} 101}
101 102
102static uint16_t 103static uint16_t
103hread2(struct sdhc_host *hp, bus_size_t reg) 104hread2(struct sdhc_host *hp, bus_size_t reg)
104{ 105{
105 106
106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_2(hp->iot, hp->ioh, reg);
108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2));
109} 110}
110 111
111#define HREAD1(hp, reg) hread1(hp, reg) 112#define HREAD1(hp, reg) hread1(hp, reg)
112#define HREAD2(hp, reg) hread2(hp, reg) 113#define HREAD2(hp, reg) hread2(hp, reg)
113#define HREAD4(hp, reg) \ 114#define HREAD4(hp, reg) \
114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
115 116
116 117
117static void 118static void
118hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val)
119{ 120{
120 121
121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 bus_space_write_1(hp->iot, hp->ioh, o, val);
123 } else { 124 } else {
124 const size_t shift = 8 * (o & 3); 125 const size_t shift = 8 * (o & 3);
125 o &= -4; 126 o &= -4;
126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 tmp = (val << shift) | (tmp & ~(0xff << shift));
128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 bus_space_write_4(hp->iot, hp->ioh, o, tmp);
129 } 130 }
130} 131}
131 132
132static void 133static void
133hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val)
134{ 135{
135 136
136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 bus_space_write_2(hp->iot, hp->ioh, o, val);
138 } else { 139 } else {
139 const size_t shift = 8 * (o & 2); 140 const size_t shift = 8 * (o & 2);
140 o &= -4; 141 o &= -4;
141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 tmp = (val << shift) | (tmp & ~(0xffff << shift));
143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 bus_space_write_4(hp->iot, hp->ioh, o, tmp);
144 } 145 }
145} 146}
146 147
147#define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148#define HWRITE1(hp, reg, val) hwrite1(hp, reg, val)
148#define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149#define HWRITE2(hp, reg, val) hwrite2(hp, reg, val)
149#define HWRITE4(hp, reg, val) \ 150#define HWRITE4(hp, reg, val) \
150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
151 152
152#define HCLR1(hp, reg, bits) \ 153#define HCLR1(hp, reg, bits) \
153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0)
154#define HCLR2(hp, reg, bits) \ 155#define HCLR2(hp, reg, bits) \
155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0)
156#define HCLR4(hp, reg, bits) \ 157#define HCLR4(hp, reg, bits) \
157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
158#define HSET1(hp, reg, bits) \ 159#define HSET1(hp, reg, bits) \
159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0)
160#define HSET2(hp, reg, bits) \ 161#define HSET2(hp, reg, bits) \
161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0)
162#define HSET4(hp, reg, bits) \ 163#define HSET4(hp, reg, bits) \
163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
164 165
165static int sdhc_host_reset(sdmmc_chipset_handle_t); 166static int sdhc_host_reset(sdmmc_chipset_handle_t);
166static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167static int sdhc_host_reset1(sdmmc_chipset_handle_t);
167static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t);
168static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169static int sdhc_host_maxblklen(sdmmc_chipset_handle_t);
169static int sdhc_card_detect(sdmmc_chipset_handle_t); 170static int sdhc_card_detect(sdmmc_chipset_handle_t);
170static int sdhc_write_protect(sdmmc_chipset_handle_t); 171static int sdhc_write_protect(sdmmc_chipset_handle_t);
171static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t);
172static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173static int sdhc_bus_clock(sdmmc_chipset_handle_t, int);
173static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174static int sdhc_bus_width(sdmmc_chipset_handle_t, int);
174static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175static int sdhc_bus_rod(sdmmc_chipset_handle_t, int);
175static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int);
176static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177static void sdhc_card_intr_ack(sdmmc_chipset_handle_t);
177static void sdhc_exec_command(sdmmc_chipset_handle_t, 178static void sdhc_exec_command(sdmmc_chipset_handle_t,
178 struct sdmmc_command *); 179 struct sdmmc_command *);
179static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
180static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t);
181static int sdhc_soft_reset(struct sdhc_host *, int); 182static int sdhc_soft_reset(struct sdhc_host *, int);
182static int sdhc_wait_intr(struct sdhc_host *, int, int); 183static int sdhc_wait_intr(struct sdhc_host *, int, int);
183static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
184static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *);
185static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *);
186static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int);
187static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int);
188static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int);
189static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int);
190 191
191 192
192static struct sdmmc_chip_functions sdhc_functions = { 193static struct sdmmc_chip_functions sdhc_functions = {
193 /* host controller reset */ 194 /* host controller reset */
194 sdhc_host_reset, 195 sdhc_host_reset,
195 196
196 /* host controller capabilities */ 197 /* host controller capabilities */
197 sdhc_host_ocr, 198 sdhc_host_ocr,
198 sdhc_host_maxblklen, 199 sdhc_host_maxblklen,
199 200
200 /* card detection */ 201 /* card detection */
201 sdhc_card_detect, 202 sdhc_card_detect,
202 203
203 /* write protect */ 204 /* write protect */
204 sdhc_write_protect, 205 sdhc_write_protect,
205 206
206 /* bus power, clock frequency and width */ 207 /* bus power, clock frequency and width */
207 sdhc_bus_power, 208 sdhc_bus_power,
208 sdhc_bus_clock, 209 sdhc_bus_clock,
209 sdhc_bus_width, 210 sdhc_bus_width,
210 sdhc_bus_rod, 211 sdhc_bus_rod,
211 212
212 /* command execution */ 213 /* command execution */
213 sdhc_exec_command, 214 sdhc_exec_command,
214 215
215 /* card interrupt */ 216 /* card interrupt */
216 sdhc_card_enable_intr, 217 sdhc_card_enable_intr,
217 sdhc_card_intr_ack 218 sdhc_card_intr_ack
218}; 219};
219 220
220static int 221static int
221sdhc_cfprint(void *aux, const char *pnp) 222sdhc_cfprint(void *aux, const char *pnp)
222{ 223{
223 const struct sdmmcbus_attach_args * const saa = aux; 224 const struct sdmmcbus_attach_args * const saa = aux;
224 const struct sdhc_host * const hp = saa->saa_sch; 225 const struct sdhc_host * const hp = saa->saa_sch;
225 226
226 if (pnp) { 227 if (pnp) {
227 aprint_normal("sdmmc at %s", pnp); 228 aprint_normal("sdmmc at %s", pnp);
228 } 229 }
229 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 230 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) {
230 if (hp->sc->sc_host[host] == hp) { 231 if (hp->sc->sc_host[host] == hp) {
231 aprint_normal(" slot %zu", host); 232 aprint_normal(" slot %zu", host);
232 } 233 }
233 } 234 }
234 235
235 return UNCONF; 236 return UNCONF;
236} 237}
237 238
238/* 239/*
239 * Called by attachment driver. For each SD card slot there is one SD 240 * Called by attachment driver. For each SD card slot there is one SD
240 * host controller standard register set. (1.3) 241 * host controller standard register set. (1.3)
241 */ 242 */
242int 243int
243sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 244sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
244 bus_space_handle_t ioh, bus_size_t iosize) 245 bus_space_handle_t ioh, bus_size_t iosize)
245{ 246{
246 struct sdmmcbus_attach_args saa; 247 struct sdmmcbus_attach_args saa;
247 struct sdhc_host *hp; 248 struct sdhc_host *hp;
248 uint32_t caps; 249 uint32_t caps;
249 uint16_t sdhcver; 250 uint16_t sdhcver;
250 251
251 /* Allocate one more host structure. */ 252 /* Allocate one more host structure. */
252 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 253 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO);
253 if (hp == NULL) { 254 if (hp == NULL) {
254 aprint_error_dev(sc->sc_dev, 255 aprint_error_dev(sc->sc_dev,
255 "couldn't alloc memory (sdhc host)\n"); 256 "couldn't alloc memory (sdhc host)\n");
256 goto err1; 257 goto err1;
257 } 258 }
258 sc->sc_host[sc->sc_nhosts++] = hp; 259 sc->sc_host[sc->sc_nhosts++] = hp;
259 260
260 /* Fill in the new host structure. */ 261 /* Fill in the new host structure. */
261 hp->sc = sc; 262 hp->sc = sc;
262 hp->iot = iot; 263 hp->iot = iot;
263 hp->ioh = ioh; 264 hp->ioh = ioh;
264 hp->ios = iosize; 265 hp->ios = iosize;
265 hp->dmat = sc->sc_dmat; 266 hp->dmat = sc->sc_dmat;
266 267
267 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 268 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC);
268 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 269 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC);
269 cv_init(&hp->intr_cv, "sdhcintr"); 270 cv_init(&hp->intr_cv, "sdhcintr");
270 271
271 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 272 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
272 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 273 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION);
273 } else { 274 } else {
274 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 275 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION);
275 } 276 }
276 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 277 aprint_normal_dev(sc->sc_dev, "SD Host Specification ");
277 hp->specver = SDHC_SPEC_VERSION(sdhcver); 278 hp->specver = SDHC_SPEC_VERSION(sdhcver);
278 switch (SDHC_SPEC_VERSION(sdhcver)) { 279 switch (SDHC_SPEC_VERSION(sdhcver)) {
279 case SDHC_SPEC_VERS_100: 280 case SDHC_SPEC_VERS_100:
280 aprint_normal("1.0"); 281 aprint_normal("1.0");
281 break; 282 break;
282 283
283 case SDHC_SPEC_VERS_200: 284 case SDHC_SPEC_VERS_200:
284 aprint_normal("2.0"); 285 aprint_normal("2.0");
285 break; 286 break;
286 287
287 case SDHC_SPEC_VERS_300: 288 case SDHC_SPEC_VERS_300:
288 aprint_normal("3.0"); 289 aprint_normal("3.0");
289 break; 290 break;
290 291
291 default: 292 default:
292 aprint_normal("unknown version(0x%x)", 293 aprint_normal("unknown version(0x%x)",
293 SDHC_SPEC_VERSION(sdhcver)); 294 SDHC_SPEC_VERSION(sdhcver));
294 break; 295 break;
295 } 296 }
296 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 297 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver));
297 298
298 /* 299 /*
299 * Reset the host controller and enable interrupts. 300 * Reset the host controller and enable interrupts.
300 */ 301 */
301 (void)sdhc_host_reset(hp); 302 (void)sdhc_host_reset(hp);
302 303
303 /* Determine host capabilities. */ 304 /* Determine host capabilities. */
304 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 305 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) {
305 caps = sc->sc_caps; 306 caps = sc->sc_caps;
306 } else { 307 } else {
307 mutex_enter(&hp->host_mtx); 308 mutex_enter(&hp->host_mtx);
308 caps = HREAD4(hp, SDHC_CAPABILITIES); 309 caps = HREAD4(hp, SDHC_CAPABILITIES);
309 mutex_exit(&hp->host_mtx); 310 mutex_exit(&hp->host_mtx);
310 } 311 }
311 312
312 /* Use DMA if the host system and the controller support it. */ 313 /*
 314 * Use DMA if the host system and the controller support it.
 315 * Suports integrated or external DMA egine, with or without
 316 * SDHC_DMA_ENABLE in the command.
 317 */
313 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 318 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) ||
314 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 319 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA &&
315 ISSET(caps, SDHC_DMA_SUPPORT)))) { 320 ISSET(caps, SDHC_DMA_SUPPORT)))) {
316 SET(hp->flags, SHF_USE_DMA); 321 SET(hp->flags, SHF_USE_DMA);
 322 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) ||
 323 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN))
 324 SET(hp->flags, SHF_MODE_DMAEN);
 325
317 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 326 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n");
318 } 327 }
319 328
320 /* 329 /*
321 * Determine the base clock frequency. (2.2.24) 330 * Determine the base clock frequency. (2.2.24)
322 */ 331 */
323 if (hp->specver == SDHC_SPEC_VERS_300) { 332 if (hp->specver == SDHC_SPEC_VERS_300) {
324 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 333 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps);
325 } else { 334 } else {
326 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 335 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
327 } 336 }
328 if (hp->clkbase == 0) { 337 if (hp->clkbase == 0) {
329 if (sc->sc_clkbase == 0) { 338 if (sc->sc_clkbase == 0) {
330 /* The attachment driver must tell us. */ 339 /* The attachment driver must tell us. */
331 aprint_error_dev(sc->sc_dev, 340 aprint_error_dev(sc->sc_dev,
332 "unknown base clock frequency\n"); 341 "unknown base clock frequency\n");
333 goto err; 342 goto err;
334 } 343 }
335 hp->clkbase = sc->sc_clkbase; 344 hp->clkbase = sc->sc_clkbase;
336 } 345 }
337 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 346 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) {
338 /* SDHC 1.0 supports only 10-63 MHz. */ 347 /* SDHC 1.0 supports only 10-63 MHz. */
339 aprint_error_dev(sc->sc_dev, 348 aprint_error_dev(sc->sc_dev,
340 "base clock frequency out of range: %u MHz\n", 349 "base clock frequency out of range: %u MHz\n",
341 hp->clkbase / 1000); 350 hp->clkbase / 1000);
342 goto err; 351 goto err;
343 } 352 }
344 DPRINTF(1,("%s: base clock frequency %u MHz\n", 353 DPRINTF(1,("%s: base clock frequency %u MHz\n",
345 device_xname(sc->sc_dev), hp->clkbase / 1000)); 354 device_xname(sc->sc_dev), hp->clkbase / 1000));
346 355
347 /* 356 /*
348 * XXX Set the data timeout counter value according to 357 * XXX Set the data timeout counter value according to
349 * capabilities. (2.2.15) 358 * capabilities. (2.2.15)
350 */ 359 */
351 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 360 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
352#if 1 361#if 1
353 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 362 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
354 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 363 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
355#endif 364#endif
356 365
357 /* 366 /*
358 * Determine SD bus voltage levels supported by the controller. 367 * Determine SD bus voltage levels supported by the controller.
359 */ 368 */
360 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) && 369 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) &&
361 (hp->specver < SDHC_SPEC_VERS_300 || 370 (hp->specver < SDHC_SPEC_VERS_300 ||
362 ISSET(caps, SDHC_EMBEDDED_SLOT))) { 371 ISSET(caps, SDHC_EMBEDDED_SLOT))) {
363 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 372 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
364 } 373 }
365 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 374 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) {
366 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 375 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
367 } 376 }
368 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 377 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) {
369 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 378 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
370 } 379 }
371 380
372 /* 381 /*
373 * Determine the maximum block length supported by the host 382 * Determine the maximum block length supported by the host
374 * controller. (2.2.24) 383 * controller. (2.2.24)
375 */ 384 */
376 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 385 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) {
377 case SDHC_MAX_BLK_LEN_512: 386 case SDHC_MAX_BLK_LEN_512:
378 hp->maxblklen = 512; 387 hp->maxblklen = 512;
379 break; 388 break;
380 389
381 case SDHC_MAX_BLK_LEN_1024: 390 case SDHC_MAX_BLK_LEN_1024:
382 hp->maxblklen = 1024; 391 hp->maxblklen = 1024;
383 break; 392 break;
384 393
385 case SDHC_MAX_BLK_LEN_2048: 394 case SDHC_MAX_BLK_LEN_2048:
386 hp->maxblklen = 2048; 395 hp->maxblklen = 2048;
387 break; 396 break;
388 397
389 case SDHC_MAX_BLK_LEN_4096: 398 case SDHC_MAX_BLK_LEN_4096:
390 hp->maxblklen = 4096; 399 hp->maxblklen = 4096;
391 break; 400 break;
392 401
393 default: 402 default:
394 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 403 aprint_error_dev(sc->sc_dev, "max block length unknown\n");
395 goto err; 404 goto err;
396 } 405 }
397 DPRINTF(1, ("%s: max block length %u byte%s\n", 406 DPRINTF(1, ("%s: max block length %u byte%s\n",
398 device_xname(sc->sc_dev), hp->maxblklen, 407 device_xname(sc->sc_dev), hp->maxblklen,
399 hp->maxblklen > 1 ? "s" : "")); 408 hp->maxblklen > 1 ? "s" : ""));
400 409
401 /* 410 /*
402 * Attach the generic SD/MMC bus driver. (The bus driver must 411 * Attach the generic SD/MMC bus driver. (The bus driver must
403 * not invoke any chipset functions before it is attached.) 412 * not invoke any chipset functions before it is attached.)
404 */ 413 */
405 memset(&saa, 0, sizeof(saa)); 414 memset(&saa, 0, sizeof(saa));
406 saa.saa_busname = "sdmmc"; 415 saa.saa_busname = "sdmmc";
407 saa.saa_sct = &sdhc_functions; 416 saa.saa_sct = &sdhc_functions;
408 saa.saa_sch = hp; 417 saa.saa_sch = hp;
409 saa.saa_dmat = hp->dmat; 418 saa.saa_dmat = hp->dmat;
410 saa.saa_clkmax = hp->clkbase; 419 saa.saa_clkmax = hp->clkbase;
411 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 420 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM))
412 saa.saa_clkmin = hp->clkbase / 256 / 2046; 421 saa.saa_clkmin = hp->clkbase / 256 / 2046;
413 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 422 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS))
414 saa.saa_clkmin = hp->clkbase / 256 / 16; 423 saa.saa_clkmin = hp->clkbase / 256 / 16;
415 else if (hp->sc->sc_clkmsk != 0) 424 else if (hp->sc->sc_clkmsk != 0)
416 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 425 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >>
417 (ffs(hp->sc->sc_clkmsk) - 1)); 426 (ffs(hp->sc->sc_clkmsk) - 1));
418 else if (hp->specver == SDHC_SPEC_VERS_300) 427 else if (hp->specver == SDHC_SPEC_VERS_300)
419 saa.saa_clkmin = hp->clkbase / 0x3ff; 428 saa.saa_clkmin = hp->clkbase / 0x3ff;
420 else 429 else
421 saa.saa_clkmin = hp->clkbase / 256; 430 saa.saa_clkmin = hp->clkbase / 256;
422 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 431 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP;
423 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 432 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE))
424 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 433 saa.saa_caps |= SMC_CAPS_8BIT_MODE;
425 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 434 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP))
426 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 435 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED;
427 if (ISSET(hp->flags, SHF_USE_DMA)) { 436 if (ISSET(hp->flags, SHF_USE_DMA)) {
428 saa.saa_caps |= SMC_CAPS_DMA; 437 saa.saa_caps |= SMC_CAPS_DMA;
429 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 438 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
430 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 439 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA;
431 } 440 }
432 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 441 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY))
433 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 442 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY;
434 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 443 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint);
435 444
436 return 0; 445 return 0;
437 446
438err: 447err:
439 cv_destroy(&hp->intr_cv); 448 cv_destroy(&hp->intr_cv);
440 mutex_destroy(&hp->intr_mtx); 449 mutex_destroy(&hp->intr_mtx);
441 mutex_destroy(&hp->host_mtx); 450 mutex_destroy(&hp->host_mtx);
442 free(hp, M_DEVBUF); 451 free(hp, M_DEVBUF);
443 sc->sc_host[--sc->sc_nhosts] = NULL; 452 sc->sc_host[--sc->sc_nhosts] = NULL;
444err1: 453err1:
445 return 1; 454 return 1;
446} 455}
447 456
448int 457int
449sdhc_detach(struct sdhc_softc *sc, int flags) 458sdhc_detach(struct sdhc_softc *sc, int flags)
450{ 459{
451 struct sdhc_host *hp; 460 struct sdhc_host *hp;
452 int rv = 0; 461 int rv = 0;
453 462
454 for (size_t n = 0; n < sc->sc_nhosts; n++) { 463 for (size_t n = 0; n < sc->sc_nhosts; n++) {
455 hp = sc->sc_host[n]; 464 hp = sc->sc_host[n];
456 if (hp == NULL) 465 if (hp == NULL)
457 continue; 466 continue;
458 if (hp->sdmmc != NULL) { 467 if (hp->sdmmc != NULL) {
459 rv = config_detach(hp->sdmmc, flags); 468 rv = config_detach(hp->sdmmc, flags);
460 if (rv) 469 if (rv)
461 break; 470 break;
462 hp->sdmmc = NULL; 471 hp->sdmmc = NULL;
463 } 472 }
464 /* disable interrupts */ 473 /* disable interrupts */
465 if ((flags & DETACH_FORCE) == 0) { 474 if ((flags & DETACH_FORCE) == 0) {
466 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 475 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
467 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 476 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
468 } else { 477 } else {
469 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 478 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
470 } 479 }
471 sdhc_soft_reset(hp, SDHC_RESET_ALL); 480 sdhc_soft_reset(hp, SDHC_RESET_ALL);
472 } 481 }
473 cv_destroy(&hp->intr_cv); 482 cv_destroy(&hp->intr_cv);
474 mutex_destroy(&hp->intr_mtx); 483 mutex_destroy(&hp->intr_mtx);
475 mutex_destroy(&hp->host_mtx); 484 mutex_destroy(&hp->host_mtx);
476 if (hp->ios > 0) { 485 if (hp->ios > 0) {
477 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 486 bus_space_unmap(hp->iot, hp->ioh, hp->ios);
478 hp->ios = 0; 487 hp->ios = 0;
479 } 488 }
480 free(hp, M_DEVBUF); 489 free(hp, M_DEVBUF);
481 sc->sc_host[n] = NULL; 490 sc->sc_host[n] = NULL;
482 } 491 }
483 492
484 return rv; 493 return rv;
485} 494}
486 495
487bool 496bool
488sdhc_suspend(device_t dev, const pmf_qual_t *qual) 497sdhc_suspend(device_t dev, const pmf_qual_t *qual)
489{ 498{
490 struct sdhc_softc *sc = device_private(dev); 499 struct sdhc_softc *sc = device_private(dev);
491 struct sdhc_host *hp; 500 struct sdhc_host *hp;
492 size_t i; 501 size_t i;
493 502
494 /* XXX poll for command completion or suspend command 503 /* XXX poll for command completion or suspend command
495 * in progress */ 504 * in progress */
496 505
497 /* Save the host controller state. */ 506 /* Save the host controller state. */
498 for (size_t n = 0; n < sc->sc_nhosts; n++) { 507 for (size_t n = 0; n < sc->sc_nhosts; n++) {
499 hp = sc->sc_host[n]; 508 hp = sc->sc_host[n];
500 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 509 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
501 for (i = 0; i < sizeof hp->regs; i += 4) { 510 for (i = 0; i < sizeof hp->regs; i += 4) {
502 uint32_t v = HREAD4(hp, i); 511 uint32_t v = HREAD4(hp, i);
503 hp->regs[i + 0] = (v >> 0); 512 hp->regs[i + 0] = (v >> 0);
504 hp->regs[i + 1] = (v >> 8); 513 hp->regs[i + 1] = (v >> 8);
505 if (i + 3 < sizeof hp->regs) { 514 if (i + 3 < sizeof hp->regs) {
506 hp->regs[i + 2] = (v >> 16); 515 hp->regs[i + 2] = (v >> 16);
507 hp->regs[i + 3] = (v >> 24); 516 hp->regs[i + 3] = (v >> 24);
508 } 517 }
509 } 518 }
510 } else { 519 } else {
511 for (i = 0; i < sizeof hp->regs; i++) { 520 for (i = 0; i < sizeof hp->regs; i++) {
512 hp->regs[i] = HREAD1(hp, i); 521 hp->regs[i] = HREAD1(hp, i);
513 } 522 }
514 } 523 }
515 } 524 }
516 return true; 525 return true;
517} 526}
518 527
519bool 528bool
520sdhc_resume(device_t dev, const pmf_qual_t *qual) 529sdhc_resume(device_t dev, const pmf_qual_t *qual)
521{ 530{
522 struct sdhc_softc *sc = device_private(dev); 531 struct sdhc_softc *sc = device_private(dev);
523 struct sdhc_host *hp; 532 struct sdhc_host *hp;
524 size_t i; 533 size_t i;
525 534
526 /* Restore the host controller state. */ 535 /* Restore the host controller state. */
527 for (size_t n = 0; n < sc->sc_nhosts; n++) { 536 for (size_t n = 0; n < sc->sc_nhosts; n++) {
528 hp = sc->sc_host[n]; 537 hp = sc->sc_host[n];
529 (void)sdhc_host_reset(hp); 538 (void)sdhc_host_reset(hp);
530 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 539 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
531 for (i = 0; i < sizeof hp->regs; i += 4) { 540 for (i = 0; i < sizeof hp->regs; i += 4) {
532 if (i + 3 < sizeof hp->regs) { 541 if (i + 3 < sizeof hp->regs) {
533 HWRITE4(hp, i, 542 HWRITE4(hp, i,
534 (hp->regs[i + 0] << 0) 543 (hp->regs[i + 0] << 0)
535 | (hp->regs[i + 1] << 8) 544 | (hp->regs[i + 1] << 8)
536 | (hp->regs[i + 2] << 16) 545 | (hp->regs[i + 2] << 16)
537 | (hp->regs[i + 3] << 24)); 546 | (hp->regs[i + 3] << 24));
538 } else { 547 } else {
539 HWRITE4(hp, i, 548 HWRITE4(hp, i,
540 (hp->regs[i + 0] << 0) 549 (hp->regs[i + 0] << 0)
541 | (hp->regs[i + 1] << 8)); 550 | (hp->regs[i + 1] << 8));
542 } 551 }
543 } 552 }
544 } else { 553 } else {
545 for (i = 0; i < sizeof hp->regs; i++) { 554 for (i = 0; i < sizeof hp->regs; i++) {
546 HWRITE1(hp, i, hp->regs[i]); 555 HWRITE1(hp, i, hp->regs[i]);
547 } 556 }
548 } 557 }
549 } 558 }
550 return true; 559 return true;
551} 560}
552 561
553bool 562bool
554sdhc_shutdown(device_t dev, int flags) 563sdhc_shutdown(device_t dev, int flags)
555{ 564{
556 struct sdhc_softc *sc = device_private(dev); 565 struct sdhc_softc *sc = device_private(dev);
557 struct sdhc_host *hp; 566 struct sdhc_host *hp;
558 567
559 /* XXX chip locks up if we don't disable it before reboot. */ 568 /* XXX chip locks up if we don't disable it before reboot. */
560 for (size_t i = 0; i < sc->sc_nhosts; i++) { 569 for (size_t i = 0; i < sc->sc_nhosts; i++) {
561 hp = sc->sc_host[i]; 570 hp = sc->sc_host[i];
562 (void)sdhc_host_reset(hp); 571 (void)sdhc_host_reset(hp);
563 } 572 }
564 return true; 573 return true;
565} 574}
566 575
567/* 576/*
568 * Reset the host controller. Called during initialization, when 577 * Reset the host controller. Called during initialization, when
569 * cards are removed, upon resume, and during error recovery. 578 * cards are removed, upon resume, and during error recovery.
570 */ 579 */
571static int 580static int
572sdhc_host_reset1(sdmmc_chipset_handle_t sch) 581sdhc_host_reset1(sdmmc_chipset_handle_t sch)
573{ 582{
574 struct sdhc_host *hp = (struct sdhc_host *)sch; 583 struct sdhc_host *hp = (struct sdhc_host *)sch;
575 uint32_t sdhcimask; 584 uint32_t sdhcimask;
576 int error; 585 int error;
577 586
578 /* Don't lock. */ 587 /* Don't lock. */
579 588
580 /* Disable all interrupts. */ 589 /* Disable all interrupts. */
581 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 590 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
582 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 591 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
583 } else { 592 } else {
584 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 593 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
585 } 594 }
586 595
587 /* 596 /*
588 * Reset the entire host controller and wait up to 100ms for 597 * Reset the entire host controller and wait up to 100ms for
589 * the controller to clear the reset bit. 598 * the controller to clear the reset bit.
590 */ 599 */
591 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 600 error = sdhc_soft_reset(hp, SDHC_RESET_ALL);
592 if (error) 601 if (error)
593 goto out; 602 goto out;
594 603
595 /* Set data timeout counter value to max for now. */ 604 /* Set data timeout counter value to max for now. */
596 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 605 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
597#if 1 606#if 1
598 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 607 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
599 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 608 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
600#endif 609#endif
601 610
602 /* Enable interrupts. */ 611 /* Enable interrupts. */
603 mutex_enter(&hp->intr_mtx); 612 mutex_enter(&hp->intr_mtx);
604 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 613 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION |
605 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 614 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY |
606 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 615 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT |
607 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 616 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE;
608 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 617 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
609 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 618 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16;
610 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 619 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
611 sdhcimask ^= 620 sdhcimask ^=
612 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 621 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16;
613 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 622 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY;
614 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 623 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
615 } else { 624 } else {
616 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 625 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
617 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 626 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK);
618 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 627 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY;
619 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 628 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
620 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 629 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK);
621 } 630 }
622 mutex_exit(&hp->intr_mtx); 631 mutex_exit(&hp->intr_mtx);
623 632
624out: 633out:
625 return error; 634 return error;
626} 635}
627 636
628static int 637static int
629sdhc_host_reset(sdmmc_chipset_handle_t sch) 638sdhc_host_reset(sdmmc_chipset_handle_t sch)
630{ 639{
631 struct sdhc_host *hp = (struct sdhc_host *)sch; 640 struct sdhc_host *hp = (struct sdhc_host *)sch;
632 int error; 641 int error;
633 642
634 mutex_enter(&hp->host_mtx); 643 mutex_enter(&hp->host_mtx);
635 error = sdhc_host_reset1(sch); 644 error = sdhc_host_reset1(sch);
636 mutex_exit(&hp->host_mtx); 645 mutex_exit(&hp->host_mtx);
637 646
638 return error; 647 return error;
639} 648}
640 649
641static uint32_t 650static uint32_t
642sdhc_host_ocr(sdmmc_chipset_handle_t sch) 651sdhc_host_ocr(sdmmc_chipset_handle_t sch)
643{ 652{
644 struct sdhc_host *hp = (struct sdhc_host *)sch; 653 struct sdhc_host *hp = (struct sdhc_host *)sch;
645 654
646 return hp->ocr; 655 return hp->ocr;
647} 656}
648 657
649static int 658static int
650sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 659sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
651{ 660{
652 struct sdhc_host *hp = (struct sdhc_host *)sch; 661 struct sdhc_host *hp = (struct sdhc_host *)sch;
653 662
654 return hp->maxblklen; 663 return hp->maxblklen;
655} 664}
656 665
657/* 666/*
658 * Return non-zero if the card is currently inserted. 667 * Return non-zero if the card is currently inserted.
659 */ 668 */
660static int 669static int
661sdhc_card_detect(sdmmc_chipset_handle_t sch) 670sdhc_card_detect(sdmmc_chipset_handle_t sch)
662{ 671{
663 struct sdhc_host *hp = (struct sdhc_host *)sch; 672 struct sdhc_host *hp = (struct sdhc_host *)sch;
664 int r; 673 int r;
665 674
666 if (hp->sc->sc_vendor_card_detect) 675 if (hp->sc->sc_vendor_card_detect)
667 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 676 return (*hp->sc->sc_vendor_card_detect)(hp->sc);
668 677
669 mutex_enter(&hp->host_mtx); 678 mutex_enter(&hp->host_mtx);
670 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 679 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
671 mutex_exit(&hp->host_mtx); 680 mutex_exit(&hp->host_mtx);
672 681
673 return r ? 1 : 0; 682 return r ? 1 : 0;
674} 683}
675 684
676/* 685/*
677 * Return non-zero if the card is currently write-protected. 686 * Return non-zero if the card is currently write-protected.
678 */ 687 */
679static int 688static int
680sdhc_write_protect(sdmmc_chipset_handle_t sch) 689sdhc_write_protect(sdmmc_chipset_handle_t sch)
681{ 690{
682 struct sdhc_host *hp = (struct sdhc_host *)sch; 691 struct sdhc_host *hp = (struct sdhc_host *)sch;
683 int r; 692 int r;
684 693
685 if (hp->sc->sc_vendor_write_protect) 694 if (hp->sc->sc_vendor_write_protect)
686 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 695 return (*hp->sc->sc_vendor_write_protect)(hp->sc);
687 696
688 mutex_enter(&hp->host_mtx); 697 mutex_enter(&hp->host_mtx);
689 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 698 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
690 mutex_exit(&hp->host_mtx); 699 mutex_exit(&hp->host_mtx);
691 700
692 return r ? 0 : 1; 701 return r ? 0 : 1;
693} 702}
694 703
695/* 704/*
696 * Set or change SD bus voltage and enable or disable SD bus power. 705 * Set or change SD bus voltage and enable or disable SD bus power.
697 * Return zero on success. 706 * Return zero on success.
698 */ 707 */
699static int 708static int
700sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 709sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
701{ 710{
702 struct sdhc_host *hp = (struct sdhc_host *)sch; 711 struct sdhc_host *hp = (struct sdhc_host *)sch;
703 uint8_t vdd; 712 uint8_t vdd;
704 int error = 0; 713 int error = 0;
705 const uint32_t pcmask = 714 const uint32_t pcmask =
706 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 715 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT));
707 716
708 mutex_enter(&hp->host_mtx); 717 mutex_enter(&hp->host_mtx);
709 718
710 /* 719 /*
711 * Disable bus power before voltage change. 720 * Disable bus power before voltage change.
712 */ 721 */
713 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 722 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)
714 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 723 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0))
715 HWRITE1(hp, SDHC_POWER_CTL, 0); 724 HWRITE1(hp, SDHC_POWER_CTL, 0);
716 725
717 /* If power is disabled, reset the host and return now. */ 726 /* If power is disabled, reset the host and return now. */
718 if (ocr == 0) { 727 if (ocr == 0) {
719 (void)sdhc_host_reset1(hp); 728 (void)sdhc_host_reset1(hp);
720 goto out; 729 goto out;
721 } 730 }
722 731
723 /* 732 /*
724 * Select the lowest voltage according to capabilities. 733 * Select the lowest voltage according to capabilities.
725 */ 734 */
726 ocr &= hp->ocr; 735 ocr &= hp->ocr;
727 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 736 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) {
728 vdd = SDHC_VOLTAGE_1_8V; 737 vdd = SDHC_VOLTAGE_1_8V;
729 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 738 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) {
730 vdd = SDHC_VOLTAGE_3_0V; 739 vdd = SDHC_VOLTAGE_3_0V;
731 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 740 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) {
732 vdd = SDHC_VOLTAGE_3_3V; 741 vdd = SDHC_VOLTAGE_3_3V;
733 } else { 742 } else {
734 /* Unsupported voltage level requested. */ 743 /* Unsupported voltage level requested. */
735 error = EINVAL; 744 error = EINVAL;
736 goto out; 745 goto out;
737 } 746 }
738 747
739 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 748 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
740 /* 749 /*
741 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 750 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus
742 * voltage ramp until power rises. 751 * voltage ramp until power rises.
743 */ 752 */
744 HWRITE1(hp, SDHC_POWER_CTL, 753 HWRITE1(hp, SDHC_POWER_CTL,
745 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 754 HREAD1(hp, SDHC_POWER_CTL) & pcmask);
746 sdmmc_delay(1); 755 sdmmc_delay(1);
747 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT)); 756 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT));
748 sdmmc_delay(1); 757 sdmmc_delay(1);
749 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 758 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER);
750 sdmmc_delay(10000); 759 sdmmc_delay(10000);
751 760
752 /* 761 /*
753 * The host system may not power the bus due to battery low, 762 * The host system may not power the bus due to battery low,
754 * etc. In that case, the host controller should clear the 763 * etc. In that case, the host controller should clear the
755 * bus power bit. 764 * bus power bit.
756 */ 765 */
757 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 766 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {
758 error = ENXIO; 767 error = ENXIO;
759 goto out; 768 goto out;
760 } 769 }
761 } 770 }
762 771
763out: 772out:
764 mutex_exit(&hp->host_mtx); 773 mutex_exit(&hp->host_mtx);
765 774
766 return error; 775 return error;
767} 776}
768 777
769/* 778/*
770 * Return the smallest possible base clock frequency divisor value 779 * Return the smallest possible base clock frequency divisor value
771 * for the CLOCK_CTL register to produce `freq' (KHz). 780 * for the CLOCK_CTL register to produce `freq' (KHz).
772 */ 781 */
773static bool 782static bool
774sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 783sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp)
775{ 784{
776 u_int div; 785 u_int div;
777 786
778 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 787 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) {
779 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 788 for (div = hp->clkbase / freq; div <= 0x3ff; div++) {
780 if ((hp->clkbase / div) <= freq) { 789 if ((hp->clkbase / div) <= freq) {
781 *divp = SDHC_SDCLK_CGM 790 *divp = SDHC_SDCLK_CGM
782 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 791 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT)
783 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 792 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT);
784 //freq = hp->clkbase / div; 793 //freq = hp->clkbase / div;
785 return true; 794 return true;
786 } 795 }
787 } 796 }
788 /* No divisor found. */ 797 /* No divisor found. */
789 return false; 798 return false;
790 } 799 }
791 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 800 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) {
792 u_int dvs = (hp->clkbase + freq - 1) / freq; 801 u_int dvs = (hp->clkbase + freq - 1) / freq;
793 u_int roundup = dvs & 1; 802 u_int roundup = dvs & 1;
794 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 803 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) {
795 if (dvs + roundup <= 16) { 804 if (dvs + roundup <= 16) {
796 dvs += roundup - 1; 805 dvs += roundup - 1;
797 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 806 *divp = (div << SDHC_SDCLK_DIV_SHIFT)
798 | (dvs << SDHC_SDCLK_DVS_SHIFT); 807 | (dvs << SDHC_SDCLK_DVS_SHIFT);
799 DPRINTF(2, 808 DPRINTF(2,
800 ("%s: divisor for freq %u is %u * %u\n", 809 ("%s: divisor for freq %u is %u * %u\n",
801 HDEVNAME(hp), freq, div * 2, dvs + 1)); 810 HDEVNAME(hp), freq, div * 2, dvs + 1));
802 //freq = hp->clkbase / (div * 2) * (dvs + 1); 811 //freq = hp->clkbase / (div * 2) * (dvs + 1);
803 return true; 812 return true;
804 } 813 }
805 /* 814 /*
806 * If we drop bits, we need to round up the divisor. 815 * If we drop bits, we need to round up the divisor.
807 */ 816 */
808 roundup |= dvs & 1; 817 roundup |= dvs & 1;
809 } 818 }
810 /* No divisor found. */ 819 /* No divisor found. */
811 return false; 820 return false;
812 } 821 }
813 if (hp->sc->sc_clkmsk != 0) { 822 if (hp->sc->sc_clkmsk != 0) {
814 div = howmany(hp->clkbase, freq); 823 div = howmany(hp->clkbase, freq);
815 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 824 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1)))
816 return false; 825 return false;
817 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 826 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1);
818 //freq = hp->clkbase / div; 827 //freq = hp->clkbase / div;
819 return true; 828 return true;
820 } 829 }
821 if (hp->specver == SDHC_SPEC_VERS_300) { 830 if (hp->specver == SDHC_SPEC_VERS_300) {
822 div = howmany(hp->clkbase, freq); 831 div = howmany(hp->clkbase, freq);
823 div = div > 1 ? howmany(div, 2) : 0; 832 div = div > 1 ? howmany(div, 2) : 0;
824 if (div > 0x3ff) 833 if (div > 0x3ff)
825 return false; 834 return false;
826 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 835 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK)
827 << SDHC_SDCLK_XDIV_SHIFT) | 836 << SDHC_SDCLK_XDIV_SHIFT) |
828 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 837 (((div >> 0) & SDHC_SDCLK_DIV_MASK)
829 << SDHC_SDCLK_DIV_SHIFT); 838 << SDHC_SDCLK_DIV_SHIFT);
830 //freq = hp->clkbase / div; 839 //freq = hp->clkbase / div;
831 return true; 840 return true;
832 } else { 841 } else {
833 for (div = 1; div <= 256; div *= 2) { 842 for (div = 1; div <= 256; div *= 2) {
834 if ((hp->clkbase / div) <= freq) { 843 if ((hp->clkbase / div) <= freq) {
835 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 844 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT;
836 //freq = hp->clkbase / div; 845 //freq = hp->clkbase / div;
837 return true; 846 return true;
838 } 847 }
839 } 848 }
840 /* No divisor found. */ 849 /* No divisor found. */
841 return false; 850 return false;
842 } 851 }
843 /* No divisor found. */ 852 /* No divisor found. */
844 return false; 853 return false;
845} 854}
846 855
847/* 856/*
848 * Set or change SDCLK frequency or disable the SD clock. 857 * Set or change SDCLK frequency or disable the SD clock.
849 * Return zero on success. 858 * Return zero on success.
850 */ 859 */
851static int 860static int
852sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 861sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
853{ 862{
854 struct sdhc_host *hp = (struct sdhc_host *)sch; 863 struct sdhc_host *hp = (struct sdhc_host *)sch;
855 u_int div; 864 u_int div;
856 u_int timo; 865 u_int timo;
857 int16_t reg; 866 int16_t reg;
858 int error = 0; 867 int error = 0;
859#ifdef DIAGNOSTIC 868#ifdef DIAGNOSTIC
860 bool present; 869 bool present;
861 870
862 mutex_enter(&hp->host_mtx); 871 mutex_enter(&hp->host_mtx);
863 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 872 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
864 mutex_exit(&hp->host_mtx); 873 mutex_exit(&hp->host_mtx);
865 874
866 /* Must not stop the clock if commands are in progress. */ 875 /* Must not stop the clock if commands are in progress. */
867 if (present && sdhc_card_detect(hp)) { 876 if (present && sdhc_card_detect(hp)) {
868 aprint_normal_dev(hp->sc->sc_dev, 877 aprint_normal_dev(hp->sc->sc_dev,
869 "%s: command in progress\n", __func__); 878 "%s: command in progress\n", __func__);
870 } 879 }
871#endif 880#endif
872 881
873 mutex_enter(&hp->host_mtx); 882 mutex_enter(&hp->host_mtx);
874 883
875 if (hp->sc->sc_vendor_bus_clock) { 884 if (hp->sc->sc_vendor_bus_clock) {
876 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 885 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq);
877 if (error != 0) 886 if (error != 0)
878 goto out; 887 goto out;
879 } 888 }
880 889
881 /* 890 /*
882 * Stop SD clock before changing the frequency. 891 * Stop SD clock before changing the frequency.
883 */ 892 */
884 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 893 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
885 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 894 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8);
886 if (freq == SDMMC_SDCLK_OFF) { 895 if (freq == SDMMC_SDCLK_OFF) {
887 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 896 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0);
888 goto out; 897 goto out;
889 } 898 }
890 } else { 899 } else {
891 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 900 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
892 if (freq == SDMMC_SDCLK_OFF) 901 if (freq == SDMMC_SDCLK_OFF)
893 goto out; 902 goto out;
894 } 903 }
895 904
896 /* 905 /*
897 * Set the minimum base clock frequency divisor. 906 * Set the minimum base clock frequency divisor.
898 */ 907 */
899 if (!sdhc_clock_divisor(hp, freq, &div)) { 908 if (!sdhc_clock_divisor(hp, freq, &div)) {
900 /* Invalid base clock frequency or `freq' value. */ 909 /* Invalid base clock frequency or `freq' value. */
901 error = EINVAL; 910 error = EINVAL;
902 goto out; 911 goto out;
903 } 912 }
904 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 913 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
905 HWRITE4(hp, SDHC_CLOCK_CTL, 914 HWRITE4(hp, SDHC_CLOCK_CTL,
906 div | (SDHC_TIMEOUT_MAX << 16)); 915 div | (SDHC_TIMEOUT_MAX << 16));
907 } else { 916 } else {
908 reg = HREAD2(hp, SDHC_CLOCK_CTL); 917 reg = HREAD2(hp, SDHC_CLOCK_CTL);
909 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 918 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE);
910 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 919 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);
911 } 920 }
912 921
913 /* 922 /*
914 * Start internal clock. Wait 10ms for stabilization. 923 * Start internal clock. Wait 10ms for stabilization.
915 */ 924 */
916 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 925 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
917 sdmmc_delay(10000); 926 sdmmc_delay(10000);
918 HSET4(hp, SDHC_CLOCK_CTL, 927 HSET4(hp, SDHC_CLOCK_CTL,
919 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 928 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE);
920 } else { 929 } else {
921 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 930 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
922 for (timo = 1000; timo > 0; timo--) { 931 for (timo = 1000; timo > 0; timo--) {
923 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 932 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL),
924 SDHC_INTCLK_STABLE)) 933 SDHC_INTCLK_STABLE))
925 break; 934 break;
926 sdmmc_delay(10); 935 sdmmc_delay(10);
927 } 936 }
928 if (timo == 0) { 937 if (timo == 0) {
929 error = ETIMEDOUT; 938 error = ETIMEDOUT;
930 goto out; 939 goto out;
931 } 940 }
932 } 941 }
933 942
934 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 943 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
935 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 944 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE);
936 /* 945 /*
937 * Sending 80 clocks at 400kHz takes 200us. 946 * Sending 80 clocks at 400kHz takes 200us.
938 * So delay for that time + slop and then 947 * So delay for that time + slop and then
939 * check a few times for completion. 948 * check a few times for completion.
940 */ 949 */
941 sdmmc_delay(210); 950 sdmmc_delay(210);
942 for (timo = 10; timo > 0; timo--) { 951 for (timo = 10; timo > 0; timo--) {
943 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 952 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET),
944 SDHC_INIT_ACTIVE)) 953 SDHC_INIT_ACTIVE))
945 break; 954 break;
946 sdmmc_delay(10); 955 sdmmc_delay(10);
947 } 956 }
948 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 957 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo));
949 958
950 /* 959 /*
951 * Enable SD clock. 960 * Enable SD clock.
952 */ 961 */
953 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 962 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
954 } else { 963 } else {
955 /* 964 /*
956 * Enable SD clock. 965 * Enable SD clock.
957 */ 966 */
958 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 967 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
959 968
960 if (freq > 25000 && 969 if (freq > 25000 &&
961 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 970 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT))
962 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 971 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
963 else 972 else
964 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 973 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
965 } 974 }
966 975
967out: 976out:
968 mutex_exit(&hp->host_mtx); 977 mutex_exit(&hp->host_mtx);
969 978
970 return error; 979 return error;
971} 980}
972 981
973static int 982static int
974sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 983sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
975{ 984{
976 struct sdhc_host *hp = (struct sdhc_host *)sch; 985 struct sdhc_host *hp = (struct sdhc_host *)sch;
977 int reg; 986 int reg;
978 987
979 switch (width) { 988 switch (width) {
980 case 1: 989 case 1:
981 case 4: 990 case 4:
982 break; 991 break;
983 992
984 case 8: 993 case 8:
985 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 994 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE))
986 break; 995 break;
987 /* FALLTHROUGH */ 996 /* FALLTHROUGH */
988 default: 997 default:
989 DPRINTF(0,("%s: unsupported bus width (%d)\n", 998 DPRINTF(0,("%s: unsupported bus width (%d)\n",
990 HDEVNAME(hp), width)); 999 HDEVNAME(hp), width));
991 return 1; 1000 return 1;
992 } 1001 }
993 1002
994 mutex_enter(&hp->host_mtx); 1003 mutex_enter(&hp->host_mtx);
995 reg = HREAD1(hp, SDHC_HOST_CTL); 1004 reg = HREAD1(hp, SDHC_HOST_CTL);
996 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1005 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
997 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1006 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE);
998 if (width == 4) 1007 if (width == 4)
999 reg |= SDHC_4BIT_MODE; 1008 reg |= SDHC_4BIT_MODE;
1000 else if (width == 8) 1009 else if (width == 8)
1001 reg |= SDHC_ESDHC_8BIT_MODE; 1010 reg |= SDHC_ESDHC_8BIT_MODE;
1002 } else { 1011 } else {
1003 reg &= ~SDHC_4BIT_MODE; 1012 reg &= ~SDHC_4BIT_MODE;
1004 if (width == 4) 1013 if (width == 4)
1005 reg |= SDHC_4BIT_MODE; 1014 reg |= SDHC_4BIT_MODE;
1006 } 1015 }
1007 HWRITE1(hp, SDHC_HOST_CTL, reg); 1016 HWRITE1(hp, SDHC_HOST_CTL, reg);
1008 mutex_exit(&hp->host_mtx); 1017 mutex_exit(&hp->host_mtx);
1009 1018
1010 return 0; 1019 return 0;
1011} 1020}
1012 1021
1013static int 1022static int
1014sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1023sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on)
1015{ 1024{
1016 struct sdhc_host *hp = (struct sdhc_host *)sch; 1025 struct sdhc_host *hp = (struct sdhc_host *)sch;
1017 1026
1018 if (hp->sc->sc_vendor_rod) 1027 if (hp->sc->sc_vendor_rod)
1019 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1028 return (*hp->sc->sc_vendor_rod)(hp->sc, on);
1020 1029
1021 return 0; 1030 return 0;
1022} 1031}
1023 1032
1024static void 1033static void
1025sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1034sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
1026{ 1035{
1027 struct sdhc_host *hp = (struct sdhc_host *)sch; 1036 struct sdhc_host *hp = (struct sdhc_host *)sch;
1028 1037
1029 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1038 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1030 mutex_enter(&hp->intr_mtx); 1039 mutex_enter(&hp->intr_mtx);
1031 if (enable) { 1040 if (enable) {
1032 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1041 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1033 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1042 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
1034 } else { 1043 } else {
1035 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1044 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
1036 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1045 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1037 } 1046 }
1038 mutex_exit(&hp->intr_mtx); 1047 mutex_exit(&hp->intr_mtx);
1039 } 1048 }
1040} 1049}
1041 1050
1042static void 1051static void
1043sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1052sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
1044{ 1053{
1045 struct sdhc_host *hp = (struct sdhc_host *)sch; 1054 struct sdhc_host *hp = (struct sdhc_host *)sch;
1046 1055
1047 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1056 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1048 mutex_enter(&hp->intr_mtx); 1057 mutex_enter(&hp->intr_mtx);
1049 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1058 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1050 mutex_exit(&hp->intr_mtx); 1059 mutex_exit(&hp->intr_mtx);
1051 } 1060 }
1052} 1061}
1053 1062
1054static int 1063static int
1055sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1064sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value)
1056{ 1065{
1057 uint32_t state; 1066 uint32_t state;
1058 int timeout; 1067 int timeout;
1059 1068
1060 for (timeout = 10; timeout > 0; timeout--) { 1069 for (timeout = 10; timeout > 0; timeout--) {
1061 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1070 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value)
1062 return 0; 1071 return 0;
1063 sdmmc_delay(10000); 1072 sdmmc_delay(10000);
1064 } 1073 }
1065 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1074 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp),
1066 value, state)); 1075 value, state));
1067 return ETIMEDOUT; 1076 return ETIMEDOUT;
1068} 1077}
1069 1078
1070static void 1079static void
1071sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1080sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
1072{ 1081{
1073 struct sdhc_host *hp = (struct sdhc_host *)sch; 1082 struct sdhc_host *hp = (struct sdhc_host *)sch;
1074 int error; 1083 int error;
1075 1084
1076 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1085 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1077 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1086 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY;
1078 mutex_enter(&hp->intr_mtx); 1087 mutex_enter(&hp->intr_mtx);
1079 if (ISSET(hp->flags, SHF_USE_DMA)) { 1088 if (ISSET(hp->flags, SHF_USE_DMA)) {
1080 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1089 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready);
1081 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1090 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready);
1082 } else { 1091 } else {
1083 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1092 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready);
1084 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1093 HSET2(hp, SDHC_NINTR_STATUS_EN, ready);
1085 } 1094 }
1086 mutex_exit(&hp->intr_mtx); 1095 mutex_exit(&hp->intr_mtx);
1087 } 1096 }
1088 1097
1089 /* 1098 /*
1090 * Start the MMC command, or mark `cmd' as failed and return. 1099 * Start the MMC command, or mark `cmd' as failed and return.
1091 */ 1100 */
1092 error = sdhc_start_command(hp, cmd); 1101 error = sdhc_start_command(hp, cmd);
1093 if (error) { 1102 if (error) {
1094 cmd->c_error = error; 1103 cmd->c_error = error;
1095 goto out; 1104 goto out;
1096 } 1105 }
1097 1106
1098 /* 1107 /*
1099 * Wait until the command phase is done, or until the command 1108 * Wait until the command phase is done, or until the command
1100 * is marked done for any other reason. 1109 * is marked done for any other reason.
1101 */ 1110 */
1102 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1111 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) {
1103 cmd->c_error = ETIMEDOUT; 1112 cmd->c_error = ETIMEDOUT;
1104 goto out; 1113 goto out;
1105 } 1114 }
1106 1115
1107 /* 1116 /*
1108 * The host controller removes bits [0:7] from the response 1117 * The host controller removes bits [0:7] from the response
1109 * data (CRC) and we pass the data up unchanged to the bus 1118 * data (CRC) and we pass the data up unchanged to the bus
1110 * driver (without padding). 1119 * driver (without padding).
1111 */ 1120 */
1112 mutex_enter(&hp->host_mtx); 1121 mutex_enter(&hp->host_mtx);
1113 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1122 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
1114 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1123 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0);
1115 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1124 if (ISSET(cmd->c_flags, SCF_RSP_136)) {
1116 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1125 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4);
1117 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1126 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8);
1118 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1127 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12);
1119 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1128 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) {
1120 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1129 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
1121 (cmd->c_resp[1] << 24); 1130 (cmd->c_resp[1] << 24);
1122 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1131 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
1123 (cmd->c_resp[2] << 24); 1132 (cmd->c_resp[2] << 24);
1124 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1133 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
1125 (cmd->c_resp[3] << 24); 1134 (cmd->c_resp[3] << 24);
1126 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1135 cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
1127 } 1136 }
1128 } 1137 }
1129 } 1138 }
1130 mutex_exit(&hp->host_mtx); 1139 mutex_exit(&hp->host_mtx);
1131 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1140 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0]));
1132 1141
1133 /* 1142 /*
1134 * If the command has data to transfer in any direction, 1143 * If the command has data to transfer in any direction,
1135 * execute the transfer now. 1144 * execute the transfer now.
1136 */ 1145 */
1137 if (cmd->c_error == 0 && cmd->c_data != NULL) 1146 if (cmd->c_error == 0 && cmd->c_data != NULL)
1138 sdhc_transfer_data(hp, cmd); 1147 sdhc_transfer_data(hp, cmd);
1139 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1148 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) {
1140 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1149 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) {
1141 cmd->c_error = ETIMEDOUT; 1150 cmd->c_error = ETIMEDOUT;
1142 goto out; 1151 goto out;
1143 } 1152 }
1144 } 1153 }
1145 1154
1146out: 1155out:
1147 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1156 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)
1148 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1157 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) {
1149 mutex_enter(&hp->host_mtx); 1158 mutex_enter(&hp->host_mtx);
1150 /* Turn off the LED. */ 1159 /* Turn off the LED. */
1151 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1160 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
1152 mutex_exit(&hp->host_mtx); 1161 mutex_exit(&hp->host_mtx);
1153 } 1162 }
1154 SET(cmd->c_flags, SCF_ITSDONE); 1163 SET(cmd->c_flags, SCF_ITSDONE);
1155 1164
1156 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1165 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp),
1157 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1166 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort",
1158 cmd->c_flags, cmd->c_error)); 1167 cmd->c_flags, cmd->c_error));
1159} 1168}
1160 1169
1161static int 1170static int
1162sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1171sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
1163{ 1172{
1164 struct sdhc_softc * const sc = hp->sc; 1173 struct sdhc_softc * const sc = hp->sc;
1165 uint16_t blksize = 0; 1174 uint16_t blksize = 0;
1166 uint16_t blkcount = 0; 1175 uint16_t blkcount = 0;
1167 uint16_t mode; 1176 uint16_t mode;
1168 uint16_t command; 1177 uint16_t command;
1169 int error; 1178 int error;
1170 1179
1171 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1180 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n",
1172 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1181 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data,
1173 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1182 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS)));
1174 1183
1175 /* 1184 /*
1176 * The maximum block length for commands should be the minimum 1185 * The maximum block length for commands should be the minimum
1177 * of the host buffer size and the card buffer size. (1.7.2) 1186 * of the host buffer size and the card buffer size. (1.7.2)
1178 */ 1187 */
1179 1188
1180 /* Fragment the data into proper blocks. */ 1189 /* Fragment the data into proper blocks. */
1181 if (cmd->c_datalen > 0) { 1190 if (cmd->c_datalen > 0) {
1182 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1191 blksize = MIN(cmd->c_datalen, cmd->c_blklen);
1183 blkcount = cmd->c_datalen / blksize; 1192 blkcount = cmd->c_datalen / blksize;
1184 if (cmd->c_datalen % blksize > 0) { 1193 if (cmd->c_datalen % blksize > 0) {
1185 /* XXX: Split this command. (1.7.4) */ 1194 /* XXX: Split this command. (1.7.4) */
1186 aprint_error_dev(sc->sc_dev, 1195 aprint_error_dev(sc->sc_dev,
1187 "data not a multiple of %u bytes\n", blksize); 1196 "data not a multiple of %u bytes\n", blksize);
1188 return EINVAL; 1197 return EINVAL;
1189 } 1198 }
1190 } 1199 }
1191 1200
1192 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1201 /* Check limit imposed by 9-bit block count. (1.7.2) */
1193 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1202 if (blkcount > SDHC_BLOCK_COUNT_MAX) {
1194 aprint_error_dev(sc->sc_dev, "too much data\n"); 1203 aprint_error_dev(sc->sc_dev, "too much data\n");
1195 return EINVAL; 1204 return EINVAL;
1196 } 1205 }
1197 1206
1198 /* Prepare transfer mode register value. (2.2.5) */ 1207 /* Prepare transfer mode register value. (2.2.5) */
1199 mode = SDHC_BLOCK_COUNT_ENABLE; 1208 mode = SDHC_BLOCK_COUNT_ENABLE;
1200 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1209 if (ISSET(cmd->c_flags, SCF_CMD_READ))
1201 mode |= SDHC_READ_MODE; 1210 mode |= SDHC_READ_MODE;
1202 if (blkcount > 1) { 1211 if (blkcount > 1) {
1203 mode |= SDHC_MULTI_BLOCK_MODE; 1212 mode |= SDHC_MULTI_BLOCK_MODE;
1204 /* XXX only for memory commands? */ 1213 /* XXX only for memory commands? */
1205 mode |= SDHC_AUTO_CMD12_ENABLE; 1214 mode |= SDHC_AUTO_CMD12_ENABLE;
1206 } 1215 }
1207 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1216 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 &&
1208 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1217 ISSET(hp->flags, SHF_MODE_DMAEN)) {
1209 mode |= SDHC_DMA_ENABLE; 1218 mode |= SDHC_DMA_ENABLE;
1210 } 1219 }
1211 1220
1212 /* 1221 /*
1213 * Prepare command register value. (2.2.6) 1222 * Prepare command register value. (2.2.6)
1214 */ 1223 */
1215 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1224 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT;
1216 1225
1217 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1226 if (ISSET(cmd->c_flags, SCF_RSP_CRC))
1218 command |= SDHC_CRC_CHECK_ENABLE; 1227 command |= SDHC_CRC_CHECK_ENABLE;
1219 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1228 if (ISSET(cmd->c_flags, SCF_RSP_IDX))
1220 command |= SDHC_INDEX_CHECK_ENABLE; 1229 command |= SDHC_INDEX_CHECK_ENABLE;
1221 if (cmd->c_data != NULL) 1230 if (cmd->c_data != NULL)
1222 command |= SDHC_DATA_PRESENT_SELECT; 1231 command |= SDHC_DATA_PRESENT_SELECT;
1223 1232
1224 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1233 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
1225 command |= SDHC_NO_RESPONSE; 1234 command |= SDHC_NO_RESPONSE;
1226 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1235 else if (ISSET(cmd->c_flags, SCF_RSP_136))
1227 command |= SDHC_RESP_LEN_136; 1236 command |= SDHC_RESP_LEN_136;
1228 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1237 else if (ISSET(cmd->c_flags, SCF_RSP_BSY))
1229 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1238 command |= SDHC_RESP_LEN_48_CHK_BUSY;
1230 else 1239 else
1231 command |= SDHC_RESP_LEN_48; 1240 command |= SDHC_RESP_LEN_48;
1232 1241
1233 /* Wait until command and data inhibit bits are clear. (1.5) */ 1242 /* Wait until command and data inhibit bits are clear. (1.5) */
1234 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1243 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0);
1235 if (error) 1244 if (error)
1236 return error; 1245 return error;
1237 1246
1238 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1247 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n",
1239 HDEVNAME(hp), blksize, blkcount, mode, command)); 1248 HDEVNAME(hp), blksize, blkcount, mode, command));
1240 1249
1241 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1250 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1242 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1251 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) <<
1243 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1252 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */
1244 } 1253 }
1245 1254
1246 mutex_enter(&hp->host_mtx); 1255 mutex_enter(&hp->host_mtx);
1247 1256
1248 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1257 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1249 /* Alert the user not to remove the card. */ 1258 /* Alert the user not to remove the card. */
1250 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1259 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
1251 } 1260 }
1252 1261
1253 /* Set DMA start address. */ 1262 /* Set DMA start address. */
1254 if (ISSET(mode, SDHC_DMA_ENABLE)) 1263 if (ISSET(mode, SDHC_DMA_ENABLE) &&
 1264 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA))
1255 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1265 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
1256 1266
1257 /* 1267 /*
1258 * Start a CPU data transfer. Writing to the high order byte 1268 * Start a CPU data transfer. Writing to the high order byte
1259 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1269 * of the SDHC_COMMAND register triggers the SD command. (1.5)
1260 */ 1270 */
1261 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1271 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
1262 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1272 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16));
1263 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1273 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1264 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1274 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16));
1265 } else { 1275 } else {
1266 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1276 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
1267 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1277 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
1268 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1278 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1269 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1279 HWRITE2(hp, SDHC_TRANSFER_MODE, mode);
1270 HWRITE2(hp, SDHC_COMMAND, command); 1280 HWRITE2(hp, SDHC_COMMAND, command);
1271 } 1281 }
1272 1282
1273 mutex_exit(&hp->host_mtx); 1283 mutex_exit(&hp->host_mtx);
1274 1284
1275 return 0; 1285 return 0;
1276} 1286}
1277 1287
1278static void 1288static void
1279sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1289sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
1280{ 1290{
1281 struct sdhc_softc *sc = hp->sc; 1291 struct sdhc_softc *sc = hp->sc;
1282 int error; 1292 int error;
1283 1293
1284 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1294 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp),
1285 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1295 MMC_R1(cmd->c_resp), cmd->c_datalen));
1286 1296
1287#ifdef SDHC_DEBUG 1297#ifdef SDHC_DEBUG
1288 /* XXX I forgot why I wanted to know when this happens :-( */ 1298 /* XXX I forgot why I wanted to know when this happens :-( */
1289 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1299 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) &&
1290 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1300 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) {
1291 aprint_error_dev(hp->sc->sc_dev, 1301 aprint_error_dev(hp->sc->sc_dev,
1292 "CMD52/53 error response flags %#x\n", 1302 "CMD52/53 error response flags %#x\n",
1293 MMC_R1(cmd->c_resp) & 0xff00); 1303 MMC_R1(cmd->c_resp) & 0xff00);
1294 } 1304 }
1295#endif 1305#endif
1296 1306
1297 if (cmd->c_dmamap != NULL) { 1307 if (cmd->c_dmamap != NULL) {
1298 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1308 if (hp->sc->sc_vendor_transfer_data_dma != NULL) {
1299 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1309 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd);
1300 if (error == 0 && !sdhc_wait_intr(hp, 1310 if (error == 0 && !sdhc_wait_intr(hp,
1301 SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) { 1311 SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) {
1302 error = ETIMEDOUT; 1312 error = ETIMEDOUT;
1303 } 1313 }
1304 } else { 1314 } else {
1305 error = sdhc_transfer_data_dma(hp, cmd); 1315 error = sdhc_transfer_data_dma(hp, cmd);
1306 } 1316 }
1307 } else 1317 } else
1308 error = sdhc_transfer_data_pio(hp, cmd); 1318 error = sdhc_transfer_data_pio(hp, cmd);
1309 if (error) 1319 if (error)
1310 cmd->c_error = error; 1320 cmd->c_error = error;
1311 SET(cmd->c_flags, SCF_ITSDONE); 1321 SET(cmd->c_flags, SCF_ITSDONE);
1312 1322
1313 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1323 DPRINTF(1,("%s: data transfer done (error=%d)\n",
1314 HDEVNAME(hp), cmd->c_error)); 1324 HDEVNAME(hp), cmd->c_error));
1315} 1325}
1316 1326
1317static int 1327static int
1318sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1328sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd)
1319{ 1329{
1320 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1330 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs;
1321 bus_addr_t posaddr; 1331 bus_addr_t posaddr;
1322 bus_addr_t segaddr; 1332 bus_addr_t segaddr;
1323 bus_size_t seglen; 1333 bus_size_t seglen;
1324 u_int seg = 0; 1334 u_int seg = 0;
1325 int error = 0; 1335 int error = 0;
1326 int status; 1336 int status;
1327 1337
1328 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1338 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT);
1329 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1339 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT);
1330 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1340 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
1331 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1341 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
1332 1342
1333 for (;;) { 1343 for (;;) {
1334 status = sdhc_wait_intr(hp, 1344 status = sdhc_wait_intr(hp,
1335 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1345 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE,
1336 SDHC_DMA_TIMEOUT); 1346 SDHC_DMA_TIMEOUT);
1337 1347
1338 if (status & SDHC_TRANSFER_COMPLETE) { 1348 if (status & SDHC_TRANSFER_COMPLETE) {
1339 break; 1349 break;
1340 } 1350 }
1341 if (!status) { 1351 if (!status) {
1342 error = ETIMEDOUT; 1352 error = ETIMEDOUT;
1343 break; 1353 break;
1344 } 1354 }
1345 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1355 if ((status & SDHC_DMA_INTERRUPT) == 0) {
1346 continue; 1356 continue;
1347 } 1357 }
1348 1358
1349 /* DMA Interrupt (boundary crossing) */ 1359 /* DMA Interrupt (boundary crossing) */
1350 1360
1351 segaddr = dm_segs[seg].ds_addr; 1361 segaddr = dm_segs[seg].ds_addr;
1352 seglen = dm_segs[seg].ds_len; 1362 seglen = dm_segs[seg].ds_len;
1353 mutex_enter(&hp->host_mtx); 1363 mutex_enter(&hp->host_mtx);
1354 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1364 posaddr = HREAD4(hp, SDHC_DMA_ADDR);
1355 mutex_exit(&hp->host_mtx); 1365 mutex_exit(&hp->host_mtx);
1356 1366
1357 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1367 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) {
1358 continue; 1368 continue;
1359 } 1369 }
1360 mutex_enter(&hp->host_mtx); 1370 mutex_enter(&hp->host_mtx);
1361 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1371 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen)))
1362 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1372 HWRITE4(hp, SDHC_DMA_ADDR, posaddr);
1363 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1373 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs)
1364 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1374 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr);
1365 mutex_exit(&hp->host_mtx); 1375 mutex_exit(&hp->host_mtx);
1366 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1376 KASSERT(seg < cmd->c_dmamap->dm_nsegs);
1367 } 1377 }
1368 1378
1369 return error; 1379 return error;
1370} 1380}
1371 1381
1372static int 1382static int
1373sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1383sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd)
1374{ 1384{
1375 uint8_t *data = cmd->c_data; 1385 uint8_t *data = cmd->c_data;
1376 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1386 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int);
1377 u_int len, datalen; 1387 u_int len, datalen;
1378 u_int imask; 1388 u_int imask;
1379 u_int pmask; 1389 u_int pmask;
1380 int error = 0; 1390 int error = 0;
1381 1391
1382 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1392 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
1383 imask = SDHC_BUFFER_READ_READY; 1393 imask = SDHC_BUFFER_READ_READY;
1384 pmask = SDHC_BUFFER_READ_ENABLE; 1394 pmask = SDHC_BUFFER_READ_ENABLE;
1385 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1395 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1386 pio_func = esdhc_read_data_pio; 1396 pio_func = esdhc_read_data_pio;
1387 } else { 1397 } else {
1388 pio_func = sdhc_read_data_pio; 1398 pio_func = sdhc_read_data_pio;
1389 } 1399 }
1390 } else { 1400 } else {
1391 imask = SDHC_BUFFER_WRITE_READY; 1401 imask = SDHC_BUFFER_WRITE_READY;
1392 pmask = SDHC_BUFFER_WRITE_ENABLE; 1402 pmask = SDHC_BUFFER_WRITE_ENABLE;
1393 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1403 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1394 pio_func = esdhc_write_data_pio; 1404 pio_func = esdhc_write_data_pio;
1395 } else { 1405 } else {
1396 pio_func = sdhc_write_data_pio; 1406 pio_func = sdhc_write_data_pio;
1397 } 1407 }
1398 } 1408 }
1399 datalen = cmd->c_datalen; 1409 datalen = cmd->c_datalen;
1400 1410
1401 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1411 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask);
1402 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1412 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
1403 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1413 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
1404 1414
1405 while (datalen > 0) { 1415 while (datalen > 0) {
1406 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1416 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) {
1407 mutex_enter(&hp->intr_mtx); 1417 mutex_enter(&hp->intr_mtx);
1408 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1418 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
1409 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1419 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask);
1410 } else { 1420 } else {
1411 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1421 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask);
1412 } 1422 }
1413 mutex_exit(&hp->intr_mtx); 1423 mutex_exit(&hp->intr_mtx);
1414 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1424 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) {
1415 error = ETIMEDOUT; 1425 error = ETIMEDOUT;
1416 break; 1426 break;
1417 } 1427 }
1418 1428
1419 error = sdhc_wait_state(hp, pmask, pmask); 1429 error = sdhc_wait_state(hp, pmask, pmask);
1420 if (error) 1430 if (error)
1421 break; 1431 break;
1422 } 1432 }
1423 1433
1424 len = MIN(datalen, cmd->c_blklen); 1434 len = MIN(datalen, cmd->c_blklen);
1425 (*pio_func)(hp, data, len); 1435 (*pio_func)(hp, data, len);
1426 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1436 DPRINTF(2,("%s: pio data transfer %u @ %p\n",
1427 HDEVNAME(hp), len, data)); 1437 HDEVNAME(hp), len, data));
1428 1438
1429 data += len; 1439 data += len;
1430 datalen -= len; 1440 datalen -= len;
1431 } 1441 }
1432 1442
1433 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1443 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
1434 SDHC_TRANSFER_TIMEOUT)) 1444 SDHC_TRANSFER_TIMEOUT))
1435 error = ETIMEDOUT; 1445 error = ETIMEDOUT;
1436 1446
1437 return error; 1447 return error;
1438} 1448}
1439 1449
1440static void 1450static void
1441sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1451sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
1442{ 1452{
1443 1453
1444 if (((__uintptr_t)data & 3) == 0) { 1454 if (((__uintptr_t)data & 3) == 0) {
1445 while (datalen > 3) { 1455 while (datalen > 3) {
1446 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1456 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA));
1447 data += 4; 1457 data += 4;
1448 datalen -= 4; 1458 datalen -= 4;
1449 } 1459 }
1450 if (datalen > 1) { 1460 if (datalen > 1) {
1451 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1461 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA));
1452 data += 2; 1462 data += 2;
1453 datalen -= 2; 1463 datalen -= 2;
1454 } 1464 }
1455 if (datalen > 0) { 1465 if (datalen > 0) {
1456 *data = HREAD1(hp, SDHC_DATA); 1466 *data = HREAD1(hp, SDHC_DATA);
1457 data += 1; 1467 data += 1;
1458 datalen -= 1; 1468 datalen -= 1;
1459 } 1469 }
1460 } else if (((__uintptr_t)data & 1) == 0) { 1470 } else if (((__uintptr_t)data & 1) == 0) {
1461 while (datalen > 1) { 1471 while (datalen > 1) {
1462 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1472 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA));
1463 data += 2; 1473 data += 2;
1464 datalen -= 2; 1474 datalen -= 2;
1465 } 1475 }
1466 if (datalen > 0) { 1476 if (datalen > 0) {
1467 *data = HREAD1(hp, SDHC_DATA); 1477 *data = HREAD1(hp, SDHC_DATA);
1468 data += 1; 1478 data += 1;
1469 datalen -= 1; 1479 datalen -= 1;
1470 } 1480 }
1471 } else { 1481 } else {
1472 while (datalen > 0) { 1482 while (datalen > 0) {
1473 *data = HREAD1(hp, SDHC_DATA); 1483 *data = HREAD1(hp, SDHC_DATA);
1474 data += 1; 1484 data += 1;
1475 datalen -= 1; 1485 datalen -= 1;
1476 } 1486 }
1477 } 1487 }
1478} 1488}
1479 1489
1480static void 1490static void
1481sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1491sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
1482{ 1492{
1483 1493
1484 if (((__uintptr_t)data & 3) == 0) { 1494 if (((__uintptr_t)data & 3) == 0) {
1485 while (datalen > 3) { 1495 while (datalen > 3) {
1486 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1496 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data));
1487 data += 4; 1497 data += 4;
1488 datalen -= 4; 1498 datalen -= 4;
1489 } 1499 }
1490 if (datalen > 1) { 1500 if (datalen > 1) {
1491 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1501 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data));
1492 data += 2; 1502 data += 2;
1493 datalen -= 2; 1503 datalen -= 2;
1494 } 1504 }
1495 if (datalen > 0) { 1505 if (datalen > 0) {
1496 HWRITE1(hp, SDHC_DATA, *data); 1506 HWRITE1(hp, SDHC_DATA, *data);
1497 data += 1; 1507 data += 1;
1498 datalen -= 1; 1508 datalen -= 1;
1499 } 1509 }
1500 } else if (((__uintptr_t)data & 1) == 0) { 1510 } else if (((__uintptr_t)data & 1) == 0) {
1501 while (datalen > 1) { 1511 while (datalen > 1) {
1502 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1512 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data));
1503 data += 2; 1513 data += 2;
1504 datalen -= 2; 1514 datalen -= 2;
1505 } 1515 }
1506 if (datalen > 0) { 1516 if (datalen > 0) {
1507 HWRITE1(hp, SDHC_DATA, *data); 1517 HWRITE1(hp, SDHC_DATA, *data);
1508 data += 1; 1518 data += 1;
1509 datalen -= 1; 1519 datalen -= 1;
1510 } 1520 }
1511 } else { 1521 } else {
1512 while (datalen > 0) { 1522 while (datalen > 0) {
1513 HWRITE1(hp, SDHC_DATA, *data); 1523 HWRITE1(hp, SDHC_DATA, *data);
1514 data += 1; 1524 data += 1;
1515 datalen -= 1; 1525 datalen -= 1;
1516 } 1526 }
1517 } 1527 }
1518} 1528}
1519 1529
1520static void 1530static void
1521esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1531esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
1522{ 1532{
1523 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1533 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
1524 uint32_t v; 1534 uint32_t v;
1525 1535
1526 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1536 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK;
1527 size_t count = 0; 1537 size_t count = 0;
1528 1538
1529 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1539 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
1530 if (count == 0) { 1540 if (count == 0) {
1531 /* 1541 /*
1532 * If we've drained "watermark" words, we need to wait 1542 * If we've drained "watermark" words, we need to wait
1533 * a little bit so the read FIFO can refill. 1543 * a little bit so the read FIFO can refill.
1534 */ 1544 */
1535 sdmmc_delay(10); 1545 sdmmc_delay(10);
1536 count = watermark; 1546 count = watermark;
1537 } 1547 }
1538 v = HREAD4(hp, SDHC_DATA); 1548 v = HREAD4(hp, SDHC_DATA);
1539 v = le32toh(v); 1549 v = le32toh(v);
1540 *(uint32_t *)data = v; 1550 *(uint32_t *)data = v;
1541 data += 4; 1551 data += 4;
1542 datalen -= 4; 1552 datalen -= 4;
1543 status = HREAD2(hp, SDHC_NINTR_STATUS); 1553 status = HREAD2(hp, SDHC_NINTR_STATUS);
1544 count--; 1554 count--;
1545 } 1555 }
1546 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1556 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
1547 if (count == 0) { 1557 if (count == 0) {
1548 sdmmc_delay(10); 1558 sdmmc_delay(10);
1549 } 1559 }
1550 v = HREAD4(hp, SDHC_DATA); 1560 v = HREAD4(hp, SDHC_DATA);
1551 v = le32toh(v); 1561 v = le32toh(v);
1552 do { 1562 do {
1553 *data++ = v; 1563 *data++ = v;
1554 v >>= 8; 1564 v >>= 8;
1555 } while (--datalen > 0); 1565 } while (--datalen > 0);
1556 } 1566 }
1557} 1567}
1558 1568
1559static void 1569static void
1560esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1570esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
1561{ 1571{
1562 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1572 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
1563 uint32_t v; 1573 uint32_t v;
1564 1574
1565 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1575 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK;
1566 size_t count = watermark; 1576 size_t count = watermark;
1567 1577
1568 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1578 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
1569 if (count == 0) { 1579 if (count == 0) {
1570 sdmmc_delay(10); 1580 sdmmc_delay(10);
1571 count = watermark; 1581 count = watermark;
1572 } 1582 }
1573 v = *(uint32_t *)data; 1583 v = *(uint32_t *)data;
1574 v = htole32(v); 1584 v = htole32(v);
1575 HWRITE4(hp, SDHC_DATA, v); 1585 HWRITE4(hp, SDHC_DATA, v);
1576 data += 4; 1586 data += 4;
1577 datalen -= 4; 1587 datalen -= 4;
1578 status = HREAD2(hp, SDHC_NINTR_STATUS); 1588 status = HREAD2(hp, SDHC_NINTR_STATUS);
1579 count--; 1589 count--;
1580 } 1590 }
1581 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1591 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
1582 if (count == 0) { 1592 if (count == 0) {
1583 sdmmc_delay(10); 1593 sdmmc_delay(10);
1584 } 1594 }
1585 v = *(uint32_t *)data; 1595 v = *(uint32_t *)data;
1586 v = htole32(v); 1596 v = htole32(v);
1587 HWRITE4(hp, SDHC_DATA, v); 1597 HWRITE4(hp, SDHC_DATA, v);
1588 } 1598 }
1589} 1599}
1590 1600
1591/* Prepare for another command. */ 1601/* Prepare for another command. */
1592static int 1602static int
1593sdhc_soft_reset(struct sdhc_host *hp, int mask) 1603sdhc_soft_reset(struct sdhc_host *hp, int mask)
1594{ 1604{
1595 int timo; 1605 int timo;
1596 1606
1597 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1607 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask));
1598 1608
1599 /* Request the reset. */ 1609 /* Request the reset. */
1600 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1610 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);
1601 1611
1602 /* 1612 /*
1603 * If necessary, wait for the controller to set the bits to 1613 * If necessary, wait for the controller to set the bits to
1604 * acknowledge the reset. 1614 * acknowledge the reset.
1605 */ 1615 */
1606 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1616 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) &&
1607 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1617 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) {
1608 for (timo = 10000; timo > 0; timo--) { 1618 for (timo = 10000; timo > 0; timo--) {
1609 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1619 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
1610 break; 1620 break;
1611 /* Short delay because I worry we may miss it... */ 1621 /* Short delay because I worry we may miss it... */
1612 sdmmc_delay(1); 1622 sdmmc_delay(1);
1613 } 1623 }
1614 if (timo == 0) 1624 if (timo == 0)
1615 return ETIMEDOUT; 1625 return ETIMEDOUT;
1616 } 1626 }
1617 1627
1618 /* 1628 /*
1619 * Wait for the controller to clear the bits to indicate that 1629 * Wait for the controller to clear the bits to indicate that
1620 * the reset has completed. 1630 * the reset has completed.
1621 */ 1631 */
1622 for (timo = 10; timo > 0; timo--) { 1632 for (timo = 10; timo > 0; timo--) {
1623 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1633 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
1624 break; 1634 break;
1625 sdmmc_delay(10000); 1635 sdmmc_delay(10000);
1626 } 1636 }
1627 if (timo == 0) { 1637 if (timo == 0) {
1628 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1638 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp),
1629 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1639 HREAD1(hp, SDHC_SOFTWARE_RESET)));
1630 return ETIMEDOUT; 1640 return ETIMEDOUT;
1631 } 1641 }
1632 1642
1633 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1643 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1634 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1644 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP);
1635 } 1645 }
1636 1646
1637 return 0; 1647 return 0;
1638} 1648}
1639 1649
1640static int 1650static int
1641sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1651sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo)
1642{ 1652{
1643 int status; 1653 int status;
1644 1654
1645 mask |= SDHC_ERROR_INTERRUPT; 1655 mask |= SDHC_ERROR_INTERRUPT;
1646 1656
1647 mutex_enter(&hp->intr_mtx); 1657 mutex_enter(&hp->intr_mtx);
1648 status = hp->intr_status & mask; 1658 status = hp->intr_status & mask;
1649 while (status == 0) { 1659 while (status == 0) {
1650 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1660 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo)
1651 == EWOULDBLOCK) { 1661 == EWOULDBLOCK) {
1652 status |= SDHC_ERROR_INTERRUPT; 1662 status |= SDHC_ERROR_INTERRUPT;
1653 break; 1663 break;
1654 } 1664 }
1655 status = hp->intr_status & mask; 1665 status = hp->intr_status & mask;
1656 } 1666 }
1657 hp->intr_status &= ~status; 1667 hp->intr_status &= ~status;
1658 1668
1659 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1669 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status,
1660 hp->intr_error_status)); 1670 hp->intr_error_status));
1661 1671
1662 /* Command timeout has higher priority than command complete. */ 1672 /* Command timeout has higher priority than command complete. */
1663 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1673 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) {
1664 hp->intr_error_status = 0; 1674 hp->intr_error_status = 0;
1665 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1675 hp->intr_status &= ~SDHC_ERROR_INTERRUPT;
1666 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1676 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1667 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1677 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
1668 } 1678 }
1669 status = 0; 1679 status = 0;
1670 } 1680 }
1671 mutex_exit(&hp->intr_mtx); 1681 mutex_exit(&hp->intr_mtx);
1672 1682
1673 return status; 1683 return status;
1674} 1684}
1675 1685
1676/* 1686/*
1677 * Established by attachment driver at interrupt priority IPL_SDMMC. 1687 * Established by attachment driver at interrupt priority IPL_SDMMC.
1678 */ 1688 */
1679int 1689int
1680sdhc_intr(void *arg) 1690sdhc_intr(void *arg)
1681{ 1691{
1682 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1692 struct sdhc_softc *sc = (struct sdhc_softc *)arg;
1683 struct sdhc_host *hp; 1693 struct sdhc_host *hp;
1684 int done = 0; 1694 int done = 0;
1685 uint16_t status; 1695 uint16_t status;
1686 uint16_t error; 1696 uint16_t error;
1687 1697
1688 /* We got an interrupt, but we don't know from which slot. */ 1698 /* We got an interrupt, but we don't know from which slot. */
1689 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1699 for (size_t host = 0; host < sc->sc_nhosts; host++) {
1690 hp = sc->sc_host[host]; 1700 hp = sc->sc_host[host];
1691 if (hp == NULL) 1701 if (hp == NULL)
1692 continue; 1702 continue;
1693 1703
1694 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1704 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
1695 /* Find out which interrupts are pending. */ 1705 /* Find out which interrupts are pending. */
1696 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1706 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS);
1697 status = xstatus; 1707 status = xstatus;
1698 error = xstatus >> 16; 1708 error = xstatus >> 16;
1699 if (error) 1709 if (error)
1700 xstatus |= SDHC_ERROR_INTERRUPT; 1710 xstatus |= SDHC_ERROR_INTERRUPT;
1701 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1711 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK))
1702 continue; /* no interrupt for us */ 1712 continue; /* no interrupt for us */
1703 /* Acknowledge the interrupts we are about to handle. */ 1713 /* Acknowledge the interrupts we are about to handle. */
1704 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1714 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus);
1705 } else { 1715 } else {
1706 /* Find out which interrupts are pending. */ 1716 /* Find out which interrupts are pending. */
1707 error = 0; 1717 error = 0;
1708 status = HREAD2(hp, SDHC_NINTR_STATUS); 1718 status = HREAD2(hp, SDHC_NINTR_STATUS);
1709 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1719 if (!ISSET(status, SDHC_NINTR_STATUS_MASK))
1710 continue; /* no interrupt for us */ 1720 continue; /* no interrupt for us */
1711 /* Acknowledge the interrupts we are about to handle. */ 1721 /* Acknowledge the interrupts we are about to handle. */
1712 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1722 HWRITE2(hp, SDHC_NINTR_STATUS, status);
1713 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1723 if (ISSET(status, SDHC_ERROR_INTERRUPT)) {
1714 /* Acknowledge error interrupts. */ 1724 /* Acknowledge error interrupts. */
1715 error = HREAD2(hp, SDHC_EINTR_STATUS); 1725 error = HREAD2(hp, SDHC_EINTR_STATUS);
1716 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1726 HWRITE2(hp, SDHC_EINTR_STATUS, error);
1717 } 1727 }
1718 } 1728 }
1719 1729
1720 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1730 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp),
1721 status, error)); 1731 status, error));
1722 1732
1723 mutex_enter(&hp->intr_mtx); 1733 mutex_enter(&hp->intr_mtx);
1724 1734
1725 /* Claim this interrupt. */ 1735 /* Claim this interrupt. */
1726 done = 1; 1736 done = 1;
1727 1737
1728 /* 1738 /*
1729 * Service error interrupts. 1739 * Service error interrupts.
1730 */ 1740 */
1731 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1741 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|
1732 SDHC_DATA_TIMEOUT_ERROR)) { 1742 SDHC_DATA_TIMEOUT_ERROR)) {
1733 hp->intr_error_status |= error; 1743 hp->intr_error_status |= error;
1734 hp->intr_status |= status; 1744 hp->intr_status |= status;
1735 cv_broadcast(&hp->intr_cv); 1745 cv_broadcast(&hp->intr_cv);
1736 } 1746 }
1737 1747
1738 /* 1748 /*
1739 * Wake up the sdmmc event thread to scan for cards. 1749 * Wake up the sdmmc event thread to scan for cards.
1740 */ 1750 */
1741 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1751 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) {
1742 if (hp->sdmmc != NULL) { 1752 if (hp->sdmmc != NULL) {
1743 sdmmc_needs_discover(hp->sdmmc); 1753 sdmmc_needs_discover(hp->sdmmc);
1744 } 1754 }
1745 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1755 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1746 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1756 HCLR4(hp, SDHC_NINTR_STATUS_EN,
1747 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1757 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION));
1748 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1758 HCLR4(hp, SDHC_NINTR_SIGNAL_EN,
1749 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1759 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION));
1750 } 1760 }
1751 } 1761 }
1752 1762
1753 /* 1763 /*
1754 * Wake up the blocking process to service command 1764 * Wake up the blocking process to service command
1755 * related interrupt(s). 1765 * related interrupt(s).
1756 */ 1766 */
1757 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1767 if (ISSET(status, SDHC_COMMAND_COMPLETE|
1758 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1768 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY|
1759 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1769 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) {
1760 hp->intr_status |= status; 1770 hp->intr_status |= status;
1761 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1771 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1762 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1772 HCLR4(hp, SDHC_NINTR_SIGNAL_EN,
1763 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1773 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY));
1764 } 1774 }
1765 cv_broadcast(&hp->intr_cv); 1775 cv_broadcast(&hp->intr_cv);
1766 } 1776 }
1767 1777
1768 /* 1778 /*
1769 * Service SD card interrupts. 1779 * Service SD card interrupts.
1770 */ 1780 */
1771 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1781 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)
1772 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1782 && ISSET(status, SDHC_CARD_INTERRUPT)) {
1773 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1783 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp)));
1774 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1784 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1775 sdmmc_card_intr(hp->sdmmc); 1785 sdmmc_card_intr(hp->sdmmc);
1776 } 1786 }
1777 mutex_exit(&hp->intr_mtx); 1787 mutex_exit(&hp->intr_mtx);
1778 } 1788 }
1779 1789
1780 return done; 1790 return done;
1781} 1791}
1782 1792
1783#ifdef SDHC_DEBUG 1793#ifdef SDHC_DEBUG
1784void 1794void
1785sdhc_dump_regs(struct sdhc_host *hp) 1795sdhc_dump_regs(struct sdhc_host *hp)
1786{ 1796{
1787 1797
1788 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1798 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE,
1789 HREAD4(hp, SDHC_PRESENT_STATE)); 1799 HREAD4(hp, SDHC_PRESENT_STATE));
1790 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1800 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
1791 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1801 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL,
1792 HREAD1(hp, SDHC_POWER_CTL)); 1802 HREAD1(hp, SDHC_POWER_CTL));
1793 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1803 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS,
1794 HREAD2(hp, SDHC_NINTR_STATUS)); 1804 HREAD2(hp, SDHC_NINTR_STATUS));
1795 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1805 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS,
1796 HREAD2(hp, SDHC_EINTR_STATUS)); 1806 HREAD2(hp, SDHC_EINTR_STATUS));
1797 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1807 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN,
1798 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1808 HREAD2(hp, SDHC_NINTR_STATUS_EN));
1799 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1809 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN,
1800 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1810 HREAD2(hp, SDHC_EINTR_STATUS_EN));
1801 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1811 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN,
1802 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1812 HREAD2(hp, SDHC_NINTR_SIGNAL_EN));
1803 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1813 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN,
1804 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1814 HREAD2(hp, SDHC_EINTR_SIGNAL_EN));
1805 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1815 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES,
1806 HREAD4(hp, SDHC_CAPABILITIES)); 1816 HREAD4(hp, SDHC_CAPABILITIES));
1807 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1817 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES,
1808 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1818 HREAD4(hp, SDHC_MAX_CAPABILITIES));
1809} 1819}
1810#endif 1820#endif
cvs diff -r1.15 -r1.16 src/sys/dev/sdmmc/sdhcvar.h (switch to unified diff)

--- src/sys/dev/sdmmc/sdhcvar.h 2014/10/04 18:09:32 1.15
+++ src/sys/dev/sdmmc/sdhcvar.h 2015/04/14 18:34:29 1.16
@@ -1,75 +1,76 @@ @@ -1,75 +1,76 @@
1/* $NetBSD: sdhcvar.h,v 1.15 2014/10/04 18:09:32 jmcneill Exp $ */ 1/* $NetBSD: sdhcvar.h,v 1.16 2015/04/14 18:34:29 bouyer Exp $ */
2/* $OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $ */ 2/* $OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $ */
3 3
4/* 4/*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 * 6 *
7 * Permission to use, copy, modify, and distribute this software for any 7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above 8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies. 9 * copyright notice and this permission notice appear in all copies.
10 * 10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */ 18 */
19 19
20#ifndef _SDHCVAR_H_ 20#ifndef _SDHCVAR_H_
21#define _SDHCVAR_H_ 21#define _SDHCVAR_H_
22 22
23#include <sys/bus.h> 23#include <sys/bus.h>
24#include <sys/device.h> 24#include <sys/device.h>
25#include <sys/pmf.h> 25#include <sys/pmf.h>
26 26
27struct sdhc_host; 27struct sdhc_host;
28struct sdmmc_command; 28struct sdmmc_command;
29 29
30struct sdhc_softc { 30struct sdhc_softc {
31 device_t sc_dev; 31 device_t sc_dev;
32 32
33 struct sdhc_host **sc_host; 33 struct sdhc_host **sc_host;
34 int sc_nhosts; 34 int sc_nhosts;
35 35
36 bus_dma_tag_t sc_dmat; 36 bus_dma_tag_t sc_dmat;
37 37
38 uint32_t sc_flags; 38 uint32_t sc_flags;
39#define SDHC_FLAG_USE_DMA 0x0001 39#define SDHC_FLAG_USE_DMA 0x00000001
40#define SDHC_FLAG_FORCE_DMA 0x0002 40#define SDHC_FLAG_FORCE_DMA 0x00000002
41#define SDHC_FLAG_NO_PWR0 0x0004 /* Freescale ESDHC */ 41#define SDHC_FLAG_NO_PWR0 0x00000004 /* Freescale ESDHC */
42#define SDHC_FLAG_HAVE_DVS 0x0008 /* Freescale ESDHC */ 42#define SDHC_FLAG_HAVE_DVS 0x00000008 /* Freescale ESDHC */
43#define SDHC_FLAG_32BIT_ACCESS 0x0010 /* Freescale ESDHC */ 43#define SDHC_FLAG_32BIT_ACCESS 0x00000010 /* Freescale ESDHC */
44#define SDHC_FLAG_ENHANCED 0x0020 /* Freescale ESDHC */ 44#define SDHC_FLAG_ENHANCED 0x00000020 /* Freescale ESDHC */
45#define SDHC_FLAG_8BIT_MODE 0x0040 /* MMC 8bit mode is supported */ 45#define SDHC_FLAG_8BIT_MODE 0x00000040 /* MMC 8bit mode is supported */
46#define SDHC_FLAG_HAVE_CGM 0x0080 /* Netlogic XLP */ 46#define SDHC_FLAG_HAVE_CGM 0x00000080 /* Netlogic XLP */
47#define SDHC_FLAG_NO_LED_ON 0x0100 /* LED_ON unsupported in HOST_CTL */ 47#define SDHC_FLAG_NO_LED_ON 0x00000100 /* LED_ON unsupported in HOST_CTL */
48#define SDHC_FLAG_HOSTCAPS 0x0200 /* No device provided capabilities */ 48#define SDHC_FLAG_HOSTCAPS 0x00000200 /* No device provided capabilities */
49#define SDHC_FLAG_RSP136_CRC 0x0400 /* Resp 136 with CRC and end-bit */ 49#define SDHC_FLAG_RSP136_CRC 0x00000400 /* Resp 136 with CRC and end-bit */
50#define SDHC_FLAG_SINGLE_ONLY 0x0800 /* Single transfer only */ 50#define SDHC_FLAG_SINGLE_ONLY 0x00000800 /* Single transfer only */
51#define SDHC_FLAG_WAIT_RESET 0x1000 /* Wait for soft resets to start */ 51#define SDHC_FLAG_WAIT_RESET 0x00001000 /* Wait for soft resets to start */
52#define SDHC_FLAG_NO_HS_BIT 0x2000 /* Don't set SDHC_HIGH_SPEED bit */ 52#define SDHC_FLAG_NO_HS_BIT 0x00002000 /* Don't set SDHC_HIGH_SPEED bit */
53#define SDHC_FLAG_EXTERNAL_DMA 0x4000 53#define SDHC_FLAG_EXTERNAL_DMA 0x00004000
 54#define SDHC_FLAG_EXTDMA_DMAEN 0x00008000 /* ext. dma need SDHC_DMA_ENABLE */
54 55
55 uint32_t sc_clkbase; 56 uint32_t sc_clkbase;
56 int sc_clkmsk; /* Mask for SDCLK */ 57 int sc_clkmsk; /* Mask for SDCLK */
57 uint32_t sc_caps;/* attachment provided capabilities */ 58 uint32_t sc_caps;/* attachment provided capabilities */
58 59
59 int (*sc_vendor_rod)(struct sdhc_softc *, int); 60 int (*sc_vendor_rod)(struct sdhc_softc *, int);
60 int (*sc_vendor_write_protect)(struct sdhc_softc *); 61 int (*sc_vendor_write_protect)(struct sdhc_softc *);
61 int (*sc_vendor_card_detect)(struct sdhc_softc *); 62 int (*sc_vendor_card_detect)(struct sdhc_softc *);
62 int (*sc_vendor_bus_clock)(struct sdhc_softc *, int); 63 int (*sc_vendor_bus_clock)(struct sdhc_softc *, int);
63 int (*sc_vendor_transfer_data_dma)(struct sdhc_softc *, struct sdmmc_command *); 64 int (*sc_vendor_transfer_data_dma)(struct sdhc_softc *, struct sdmmc_command *);
64}; 65};
65 66
66/* Host controller functions called by the attachment driver. */ 67/* Host controller functions called by the attachment driver. */
67int sdhc_host_found(struct sdhc_softc *, bus_space_tag_t, 68int sdhc_host_found(struct sdhc_softc *, bus_space_tag_t,
68 bus_space_handle_t, bus_size_t); 69 bus_space_handle_t, bus_size_t);
69int sdhc_intr(void *); 70int sdhc_intr(void *);
70int sdhc_detach(struct sdhc_softc *, int); 71int sdhc_detach(struct sdhc_softc *, int);
71bool sdhc_suspend(device_t, const pmf_qual_t *); 72bool sdhc_suspend(device_t, const pmf_qual_t *);
72bool sdhc_resume(device_t, const pmf_qual_t *); 73bool sdhc_resume(device_t, const pmf_qual_t *);
73bool sdhc_shutdown(device_t, int); 74bool sdhc_shutdown(device_t, int);
74 75
75#endif /* _SDHCVAR_H_ */ 76#endif /* _SDHCVAR_H_ */