 @@ -1,382 +1,576 @@
-/*	$NetBSD: omap3_sdhc.c,v 1.15 2015/01/12 01:02:35 jakllsch Exp $	*/
+/*	$NetBSD: omap3_sdhc.c,v 1.16 2015/04/14 18:45:25 bouyer Exp $	*/
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.15 2015/01/12 01:02:35 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.16 2015/04/14 18:45:25 bouyer Exp $");
 #include "opt_omap.h"
 #include "edma.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <sys/bus.h>
 #include <arm/omap/omap2_obiovar.h>
 #include <arm/omap/omap2_reg.h>
 #include <arm/omap/omap3_sdmmcreg.h>
 #ifdef TI_AM335X
 #  include <arm/omap/am335x_prcm.h>
 #  include <arm/omap/omap2_prcm.h>
 #endif
 #if NEDMA > 0
 #  include <arm/omap/omap_edma.h>
 #endif
 #include <dev/sdmmc/sdhcreg.h>
 #include <dev/sdmmc/sdhcvar.h>
 #include <dev/sdmmc/sdmmcvar.h>
 #ifdef TI_AM335X
 #define EDMA_MAX_PARAMS		32
 #endif
 #ifdef OM3SDHC_DEBUG
 int om3sdhcdebug = 1;
 #define DPRINTF(n,s)    do { if ((n) <= om3sdhcdebug) device_printf s; } while (0)
 #else
 #define DPRINTF(n,s)    do {} while (0)
 #endif
 #define CLKD(kz)	(sc->sc.sc_clkbase / (kz))
 #define SDHC_READ(sc, reg) \
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg))
 #define SDHC_WRITE(sc, reg, val) \
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val))
 static int obiosdhc_match(device_t, cfdata_t, void *);
 static void obiosdhc_attach(device_t, device_t, void *);
 static int obiosdhc_detach(device_t, int);
 static int obiosdhc_bus_clock(struct sdhc_softc *, int);
 static int obiosdhc_rod(struct sdhc_softc *, int);
 static int obiosdhc_write_protect(struct sdhc_softc *);
 static int obiosdhc_card_detect(struct sdhc_softc *);
 struct obiosdhc_softc {
 	struct sdhc_softc	sc;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	bus_space_handle_t	sc_sdhc_bsh;
 	struct sdhc_host	*sc_hosts[1];
 	void 			*sc_ih;		/* interrupt vectoring */
 #if NEDMA > 0
 	struct edma_channel	*sc_edma_tx;
 	struct edma_channel	*sc_edma_rx;
 	uint16_t		sc_edma_param_tx[EDMA_MAX_PARAMS];
 	uint16_t		sc_edma_param_rx[EDMA_MAX_PARAMS];
 	kmutex_t		sc_edma_lock;
 	kcondvar_t		sc_edma_cv;
 	bus_addr_t		sc_edma_fifo;
 	bool			sc_edma_pending;
 #endif
 };
 #if NEDMA > 0
 static void obiosdhc_edma_init(struct obiosdhc_softc *, unsigned int);
 static int obiosdhc_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *);
 static void obiosdhc_edma_done(void *);
 #endif
 #ifdef TI_AM335X
 struct am335x_sdhc {
 	const char *as_name;
 	bus_addr_t as_base_addr;
 	int as_intr;
 	struct omap_module as_module;
 };
 static const struct am335x_sdhc am335x_sdhc[] = {
 	/* XXX All offset by 0x100 because of the am335x's mmc registers.  */
 	{ "MMCHS0", SDMMC1_BASE_TIAM335X, 64, { AM335X_PRCM_CM_PER, 0x3c } },
 	{ "MMC1",   SDMMC2_BASE_TIAM335X, 28, { AM335X_PRCM_CM_PER, 0xf4 } },
 	{ "MMCHS2", SDMMC3_BASE_TIAM335X, 29, { AM335X_PRCM_CM_WKUP, 0xf8 } },
 };
 #endif
 CFATTACH_DECL_NEW(obiosdhc, sizeof(struct obiosdhc_softc),
     obiosdhc_match, obiosdhc_attach, obiosdhc_detach, NULL);
 static int
 obiosdhc_match(device_t parent, cfdata_t cf, void *aux)
+{
 #if defined(OMAP_3430) || defined(OMAP_3530) || defined(OMAP4)
 	struct obio_attach_args * const oa = aux;
 #endif
 #ifdef TI_AM335X
 	struct obio_attach_args * const oa = aux;
 	size_t i;
 #endif
 #if defined(OMAP_3430)
 	if (oa->obio_addr == SDMMC1_BASE_3430
 	    || oa->obio_addr == SDMMC2_BASE_3430
 	    || oa->obio_addr == SDMMC3_BASE_3430)
                 return 1;
 #elif defined(OMAP_3530)
 	if (oa->obio_addr == SDMMC1_BASE_3530
 	    || oa->obio_addr == SDMMC2_BASE_3530
 	    || oa->obio_addr == SDMMC3_BASE_3530)
                 return 1;
 #elif defined(OMAP4) || defined(OMAP5)
 	if (oa->obio_addr == SDMMC1_BASE_4430
 	    || oa->obio_addr == SDMMC2_BASE_4430
 	    || oa->obio_addr == SDMMC3_BASE_4430
 	    || oa->obio_addr == SDMMC4_BASE_4430
 	    || oa->obio_addr == SDMMC5_BASE_4430)
                 return 1;
 #endif
 #ifdef TI_AM335X
 	for (i = 0; i < __arraycount(am335x_sdhc); i++)
 		if ((oa->obio_addr == am335x_sdhc[i].as_base_addr) &&
 		    (oa->obio_intr == am335x_sdhc[i].as_intr))
 			return 1;
 #endif
         return 0;
+}
 static void
 obiosdhc_attach(device_t parent, device_t self, void *aux)
+{
 	struct obiosdhc_softc * const sc = device_private(self);
 	struct obio_attach_args * const oa = aux;
 	prop_dictionary_t prop = device_properties(self);
 	uint32_t clkd, stat;
 	int error, timo, clksft, n;
 	bool support8bit = false;
 	const char *transfer_mode = "PIO";
 #ifdef TI_AM335X
 	size_t i;
 #endif
 	prop_dictionary_get_bool(prop, "8bit", &support8bit);
 	sc->sc.sc_dmat = oa->obio_dmat;
 	sc->sc.sc_dev = self;
 	//sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
 	sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
 	sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
 	sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
 	sc->sc.sc_flags |= SDHC_FLAG_SINGLE_ONLY;
 	if (support8bit)
 		sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
 #ifdef TI_AM335X
 	sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET;
 	sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
 #endif
 #if defined(OMAP_3530)
 	sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
 #endif
 	sc->sc.sc_host = sc->sc_hosts;
 	sc->sc.sc_clkbase = 96000;	/* 96MHZ */
 	if (!prop_dictionary_get_uint32(prop, "clkmask", &sc->sc.sc_clkmsk))
 		sc->sc.sc_clkmsk = 0x0000ffc0;
 	sc->sc.sc_vendor_rod = obiosdhc_rod;
 	sc->sc.sc_vendor_write_protect = obiosdhc_write_protect;
 	sc->sc.sc_vendor_card_detect = obiosdhc_card_detect;
 	sc->sc.sc_vendor_bus_clock = obiosdhc_bus_clock;
 	sc->sc_bst = oa->obio_iot;
 	clksft = ffs(sc->sc.sc_clkmsk) - 1;
 	error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
 	    &sc->sc_bsh);
 	if (error) {
 		aprint_error_dev(self,
 		    "can't map registers: %d\n", error);
 		return;
+	}
 	bus_space_subregion(sc->sc_bst, sc->sc_bsh, OMAP3_SDMMC_SDHC_OFFSET,
 	    OMAP3_SDMMC_SDHC_SIZE, &sc->sc_sdhc_bsh);
-	aprint_naive(": SDHC controller\n");
+#if NEDMA > 0
-	aprint_normal(": SDHC controller\n");
+	if (oa->obio_edmabase != -1) {
 		mutex_init(&sc->sc_edma_lock, MUTEX_DEFAULT, IPL_SCHED);
 		cv_init(&sc->sc_edma_cv, "sdhcedma");
 		sc->sc_edma_fifo = oa->obio_addr +
 		    OMAP3_SDMMC_SDHC_OFFSET + SDHC_DATA;
 		obiosdhc_edma_init(sc, oa->obio_edmabase);
 		sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
 		sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
 		sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
 		sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
 		sc->sc.sc_vendor_transfer_data_dma = obiosdhc_edma_xfer_data;
 		transfer_mode = "EDMA";
+	}
 #endif
 	aprint_naive("\n");
 	aprint_normal(": SDHC controller (%s)\n", transfer_mode);
 #ifdef TI_AM335X
 	/* XXX Not really AM335X-specific.  */
 	for (i = 0; i < __arraycount(am335x_sdhc); i++)
 		if ((oa->obio_addr == am335x_sdhc[i].as_base_addr) &&
 		    (oa->obio_intr == am335x_sdhc[i].as_intr)) {
 			prcm_module_enable(&am335x_sdhc[i].as_module);
 			break;
+		}
 	KASSERT(i < __arraycount(am335x_sdhc));
 #endif
 	/* XXXXXX: Turn-on regulator via I2C. */
 	/* XXXXXX: And enable ICLOCK/FCLOCK. */
 	/* MMCHS Soft reset */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
 	    SYSCONFIG_SOFTRESET);
 	timo = 3000000;	/* XXXX 3 sec. */
 	while (timo--) {
 		if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
 		    SYSSTATUS_RESETDONE)
 			break;
 		delay(1);
+	}
 	if (timo == 0)
 		aprint_error_dev(self, "Soft reset timeout\n");
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
 	    SYSCONFIG_ENAWAKEUP | SYSCONFIG_AUTOIDLE | SYSCONFIG_SIDLEMODE_AUTO |
 	    SYSCONFIG_CLOCKACTIVITY_FCLK | SYSCONFIG_CLOCKACTIVITY_ICLK);
 	sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
 	    sdhc_intr, &sc->sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt %d\n",
 		     oa->obio_intr);
 		goto fail;
+	}
 	error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh,
 	    oa->obio_size - OMAP3_SDMMC_SDHC_OFFSET);
 	if (error != 0) {
 		aprint_error_dev(self, "couldn't initialize host, error=%d\n",
 		    error);
 		goto fail;
+	}
 	/* Set SDVS 1.8v and DTW 1bit mode */
 	SDHC_WRITE(sc, SDHC_HOST_CTL,
 	    SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_OD);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
 							SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_HOST_CTL,
 	    SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
 	/*
 	 * 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
 	 * from 'OMAP35x Applications Processor  Technical Reference Manual'.
+	 *
 	 * During the INIT procedure, the MMCHS controller generates 80 clock
 	 * periods. In order to keep the 1ms gap, the MMCHS controller should
 	 * be configured to generate a clock whose frequency is smaller or
 	 * equal to 80 KHz.
 	 */
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
 	clkd = CLKD(80);
 	n = 1;
 	while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) {
 		clkd >>= 1;
 		n <<= 1;
+	}
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
 	for (; n > 0; n--) {
 		SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000);
 		timo = 3000000;	/* XXXX 3 sec. */
 		stat = 0;
 		while (!(stat & SDHC_COMMAND_COMPLETE)) {
 			stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
 			if (--timo == 0)
 				break;
 			delay(1);
+		}
 		if (timo == 0) {
 			aprint_error_dev(self, "INIT Procedure timeout\n");
 			break;
+		}
 		SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat);
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
 	return;
 fail:
 	if (sc->sc_ih) {
 		intr_disestablish(sc->sc_ih);
 		sc->sc_ih = NULL;
+	}
 	bus_space_unmap(sc->sc_bst, sc->sc_bsh, oa->obio_size);
+}
 static int
 obiosdhc_detach(device_t self, int flags)
+{
 //	struct obiosdhc_softc *sc = device_private(self);
 	int error;
 	error = config_detach_children(self, flags);
 	/* XXXXXX: Regurator turn-off via I2C. */
 	/* XXXXXX: And disable ICLOCK/FCLOCK. */
 	return error;
+}
 static int
 obiosdhc_rod(struct sdhc_softc *sc, int on)
+{
 	struct obiosdhc_softc *osc = (struct obiosdhc_softc *)sc;
 	uint32_t con;
 	con = bus_space_read_4(osc->sc_bst, osc->sc_bsh, MMCHS_CON);
 	if (on)
 		con |= CON_OD;
 	else
 		con &= ~CON_OD;
 	bus_space_write_4(osc->sc_bst, osc->sc_bsh, MMCHS_CON, con);
 	return 0;
+}
 static int
 obiosdhc_write_protect(struct sdhc_softc *sc)
+{
 	/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
 	return 0;	/* XXXXXXX */
+}
 static int
 obiosdhc_card_detect(struct sdhc_softc *sc)
+{
 	/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
 	return 1;	/* XXXXXXXX */
+}
 static int
 obiosdhc_bus_clock(struct sdhc_softc *sc, int clk)
+{
 	struct obiosdhc_softc *osc = (struct obiosdhc_softc *)sc;
 	uint32_t ctl;
 	ctl = bus_space_read_4(osc->sc_bst, osc->sc_bsh, MMCHS_SYSCTL);
 	if (clk == 0) {
 		ctl &= ~SYSCTL_CEN;
 	} else {
 		ctl |= SYSCTL_CEN;
+	}
 	bus_space_write_4(osc->sc_bst, osc->sc_bsh, MMCHS_SYSCTL, ctl);
 	return 0;
+}
 #if NEDMA > 0
 static void
 obiosdhc_edma_init(struct obiosdhc_softc *sc, unsigned int edmabase)
+{
 	int i;
 	/* Request tx and rx DMA channels */
 	sc->sc_edma_tx = edma_channel_alloc(EDMA_TYPE_DMA, edmabase + 0,
 	    obiosdhc_edma_done, sc);
 	KASSERT(sc->sc_edma_tx != NULL);
 	sc->sc_edma_rx = edma_channel_alloc(EDMA_TYPE_DMA, edmabase + 1,
 	    obiosdhc_edma_done, sc);
 	KASSERT(sc->sc_edma_rx != NULL);
 	device_printf(sc->sc.sc_dev, "EDMA tx channel %d, rx channel %d\n",
 	    edma_channel_index(sc->sc_edma_tx),
 	    edma_channel_index(sc->sc_edma_rx));
 	/* Allocate some PaRAM pages */
 	for (i = 0; i < __arraycount(sc->sc_edma_param_tx); i++) {
 		sc->sc_edma_param_tx[i] = edma_param_alloc(sc->sc_edma_tx);
 		KASSERT(sc->sc_edma_param_tx[i] != 0xffff);
+	}
 	for (i = 0; i < __arraycount(sc->sc_edma_param_rx); i++) {
 		sc->sc_edma_param_rx[i] = edma_param_alloc(sc->sc_edma_rx);
 		KASSERT(sc->sc_edma_param_rx[i] != 0xffff);
+	}
 	return;
+}
 static int
 obiosdhc_edma_xfer_data(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd)
+{
 	struct obiosdhc_softc *sc = device_private(sdhc_sc->sc_dev);
 	struct edma_channel *edma;
 	uint16_t *edma_param;
 	struct edma_param ep;
 	size_t seg;
 	int error;
 	int blksize = MIN(cmd->c_datalen, cmd->c_blklen);
 	edma = ISSET(cmd->c_flags, SCF_CMD_READ) ?
 	    sc->sc_edma_rx : sc->sc_edma_tx;
 	edma_param = ISSET(cmd->c_flags, SCF_CMD_READ) ?
 	    sc->sc_edma_param_rx : sc->sc_edma_param_tx;
 	DPRINTF(1, (sc->sc.sc_dev, "edma xfer: nsegs=%d ch# %d\n",
 	    cmd->c_dmamap->dm_nsegs, edma_channel_index(edma)));
 	if (cmd->c_dmamap->dm_nsegs > EDMA_MAX_PARAMS) {
 		return ENOMEM;
+	}
 	for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
 		ep.ep_opt = __SHIFTIN(2, EDMA_PARAM_OPT_FWID) /* 32-bit */;
 		ep.ep_opt |= __SHIFTIN(edma_channel_index(edma),
 				       EDMA_PARAM_OPT_TCC);
 		if (seg == cmd->c_dmamap->dm_nsegs - 1) {
 			ep.ep_opt |= EDMA_PARAM_OPT_TCINTEN;
 			ep.ep_link = 0xffff;
 		} else {
 			ep.ep_link = EDMA_PARAM_BASE(edma_param[seg+1]);
+		}
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			ep.ep_opt |= EDMA_PARAM_OPT_SAM;
 			ep.ep_src = sc->sc_edma_fifo;
 			ep.ep_dst = cmd->c_dmamap->dm_segs[seg].ds_addr;
 		} else {
 			ep.ep_opt |= EDMA_PARAM_OPT_DAM;
 			ep.ep_src = cmd->c_dmamap->dm_segs[seg].ds_addr;
 			ep.ep_dst = sc->sc_edma_fifo;
+		}
 		KASSERT(cmd->c_dmamap->dm_segs[seg].ds_len <= 65536 * 4);
                 /*
 		 * For unknown reason, the A-DMA transfers never completes for
 		 * transfers larger than 64 butes. So use a AB transfer,
 		 * with a 64 bytes A len
 		 */
 		ep.ep_bcntrld = 0;	/* not used for AB-synchronous mode */
 		ep.ep_opt |= EDMA_PARAM_OPT_SYNCDIM;
 		ep.ep_acnt = min(cmd->c_dmamap->dm_segs[seg].ds_len, 64);
 		ep.ep_bcnt = min(cmd->c_dmamap->dm_segs[seg].ds_len, blksize) /
 			     ep.ep_acnt;
 		ep.ep_ccnt = cmd->c_dmamap->dm_segs[seg].ds_len /
 			     (ep.ep_acnt * ep.ep_bcnt);
 		ep.ep_srcbidx = ep.ep_dstbidx = 0;
 		ep.ep_srccidx = ep.ep_dstcidx = 0;
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			ep.ep_dstbidx = ep.ep_acnt;
 			ep.ep_dstcidx = ep.ep_acnt * ep.ep_bcnt;
 		} else {
 			ep.ep_srcbidx = ep.ep_acnt;
 			ep.ep_srccidx = ep.ep_acnt * ep.ep_bcnt;
+		}
 		edma_set_param(edma, edma_param[seg], &ep);
 #ifdef OM3SDHC_DEBUG
 		if (om3sdhcdebug >= 1) {
 			printf("target OPT: %08x\n", ep.ep_opt);
 			edma_dump_param(edma, edma_param[seg]);
+		}
 #endif
+	}
 	mutex_enter(&sc->sc_edma_lock);
 	error = 0;
 	sc->sc_edma_pending = true;
 	edma_transfer_enable(edma, edma_param[0]);
 	while (sc->sc_edma_pending) {
 		error = cv_timedwait(&sc->sc_edma_cv, &sc->sc_edma_lock, hz*10);
 		if (error == EWOULDBLOCK) {
 			device_printf(sc->sc.sc_dev, "transfer timeout!\n");
 			edma_dump(edma);
 			edma_dump_param(edma, edma_param[0]);
 			edma_halt(edma);
 			sc->sc_edma_pending = false;
 			error = ETIMEDOUT;
 			break;
+		}
+	}
 	edma_halt(edma);
 	mutex_exit(&sc->sc_edma_lock);
 	return error;
+}
 static void
 obiosdhc_edma_done(void *priv)
+{
 	struct obiosdhc_softc *sc = priv;
 	mutex_enter(&sc->sc_edma_lock);
 	KASSERT(sc->sc_edma_pending == true);
 	sc->sc_edma_pending = false;
 	cv_broadcast(&sc->sc_edma_cv);
 	mutex_exit(&sc->sc_edma_lock);
+}
 #endif