Tue Apr 14 18:45:58 2015 UTC ()
Add the edma controller, and enable DMA for sdhc0 and sdhc1


(bouyer)
diff -r1.30 -r1.31 src/sys/arch/evbarm/conf/BEAGLEBONE
cvs diff -r1.30 -r1.31 src/sys/arch/evbarm/conf/Attic/BEAGLEBONE (expand / switch to unified diff)

--- src/sys/arch/evbarm/conf/Attic/BEAGLEBONE 2014/12/04 16:50:15 1.30
+++ src/sys/arch/evbarm/conf/Attic/BEAGLEBONE 2015/04/14 18:45:57 1.31
@@ -1,15 +1,15 @@ @@ -1,15 +1,15 @@
1# 1#
2# $NetBSD: BEAGLEBONE,v 1.30 2014/12/04 16:50:15 riz Exp $ 2# $NetBSD: BEAGLEBONE,v 1.31 2015/04/14 18:45:57 bouyer Exp $
3# 3#
4# BEAGLEBONE -- TI AM335x board Kernel 4# BEAGLEBONE -- TI AM335x board Kernel
5# 5#
6 6
7include "arch/evbarm/conf/std.beagle" 7include "arch/evbarm/conf/std.beagle"
8 8
9# estimated number of users 9# estimated number of users
10 10
11maxusers 32 11maxusers 32
12 12
13# Standard system options 13# Standard system options
14 14
15options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT 15options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
@@ -186,34 +186,37 @@ obio0 at mainbus? base 0x44000000 size  @@ -186,34 +186,37 @@ obio0 at mainbus? base 0x44000000 size
186 186
187# General Purpose Memory Controller 187# General Purpose Memory Controller
188gpmc0 at mainbus? base 0x50000000 188gpmc0 at mainbus? base 0x50000000
189 189
190# Interrupt Controller 190# Interrupt Controller
191omapicu0 at obio0 addr 0x48200000 size 0x1000 intrbase 0 191omapicu0 at obio0 addr 0x48200000 size 0x1000 intrbase 0
192 192
193# Power, Reset and Clock Management 193# Power, Reset and Clock Management
194prcm0 at obio0 addr 0x44e00000 size 0x2000 # PRM Module 194prcm0 at obio0 addr 0x44e00000 size 0x2000 # PRM Module
195 195
196# Control Module 196# Control Module
197sitaracm0 at obio0 addr 0x44e10000 size 0x2000 197sitaracm0 at obio0 addr 0x44e10000 size 0x2000
198 198
 199# Enhanced Direct Memory Access controller
 200edma0 at obio0 addr 0x49000000 size 0x100000 intrbase 12
 201
199# SDHC controllers 202# SDHC controllers
200# XXX Kludge -- the am335x's mmc registers start at an offset of #x100 203# XXX Kludge -- the am335x's mmc registers start at an offset of #x100
201# from other omap3. (What about omap4?) Need to adapt the omap sdhc 204# from other omap3. (What about omap4?) Need to adapt the omap sdhc
202# driver to handle this. 205# driver to handle this.
203sdhc0 at obio0 addr 0x48060100 size 0x0f00 intr 64 206sdhc0 at obio0 addr 0x48060100 size 0x0f00 intr 64 edmabase 24
204sdmmc0 at sdhc0 207sdmmc0 at sdhc0
205ld0 at sdmmc0 208ld0 at sdmmc0
206sdhc1 at obio0 addr 0x481d8100 size 0x0f00 intr 28 # BB Black 209sdhc1 at obio0 addr 0x481d8100 size 0x0f00 intr 28 edmabase 2 # BB Black
207sdmmc1 at sdhc1 210sdmmc1 at sdhc1
208ld1 at sdmmc1 211ld1 at sdmmc1
209#sdhc2 at obio0 addr 0x47810100 size 0xff00 intr 29 212#sdhc2 at obio0 addr 0x47810100 size 0xff00 intr 29
210#sdmmc2 at sdhc2 213#sdmmc2 at sdhc2
211#ld2 at sdmmc2 214#ld2 at sdmmc2
212sdmmc* at sdhc? # SD/MMC bus 215sdmmc* at sdhc? # SD/MMC bus
213ld* at sdmmc? 216ld* at sdmmc?
214#options SDMMC_DEBUG 217#options SDMMC_DEBUG
215#options SDHC_DEBUG 218#options SDHC_DEBUG
216 219
217# General-purpose I/O pins 220# General-purpose I/O pins
218# XXX These are the GPIO v2 in the AM335x, not v1 as in the OMAP35xx. 221# XXX These are the GPIO v2 in the AM335x, not v1 as in the OMAP35xx.
219#omapgpio0 at obio0 addr 0x44e07000 size 0x1000 intrbase 128 intr 29 222#omapgpio0 at obio0 addr 0x44e07000 size 0x1000 intrbase 128 intr 29